CN104157648B - Semiconductor device having switching element and free wheel diode and method for controlling the same - Google Patents

Semiconductor device having switching element and free wheel diode and method for controlling the same Download PDF

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Publication number
CN104157648B
CN104157648B CN201410381254.2A CN201410381254A CN104157648B CN 104157648 B CN104157648 B CN 104157648B CN 201410381254 A CN201410381254 A CN 201410381254A CN 104157648 B CN104157648 B CN 104157648B
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gate electrode
type
base
drift layer
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CN104157648A (en
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西角拓高
山本刚
水野祥司
住友正清
藤井哲夫
榊原纯
山口仁
服部佳晋
田口理惠
桑原诚
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Denso Corp
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Denso Corp
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Priority claimed from JP2010210302A external-priority patent/JP5229288B2/en
Priority claimed from JP2011027994A external-priority patent/JP5768395B2/en
Application filed by Denso Corp filed Critical Denso Corp
Priority claimed from CN201110211992.9A external-priority patent/CN102347356B/en
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Abstract

The present disclosure relates to a semiconductor device having a semiconductor switching element with an insulated gate structure and a free wheel diode coupled in parallel with each other. The semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region arranged in a surface part of the base region; an element-side gate electrode in the base region sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode electrically coupled with the element-side first impurity region and the base region; and an element-side second electrode electrically coupled with the second impurity region. The free wheel diode includes: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region arranged in a surface part of the second conductive layer; and a diode-side gate electrode including a first gate electrode which provides an excess carrier injection suppression gate.

Description

Semiconductor device and its control method with switch element and fly-wheel diode
It is on July 27th, 2011 that the present invention is the applying date, and Application No. 201110211992.9 is entitled " to have The divisional application of the Chinese patent application of the semiconductor device and its control method of switch element and fly-wheel diode ".
Technical field
The present invention relates to the thyristor (switching element) with the insulated gate being connected in parallel construction With the semiconductor device and its control method of fly-wheel diode.
Background technology
In the past, for the simplification of the construction of MOSFET used in inverter (inverter), it is proposed that by longitudinal type The construction (referring for example to patent document 1) of MOSFET and the chips of FWD mono-.So by longitudinal type MOSFET and the chips of FWD mono- Semiconductor device in, by body by possessing in longitudinal type MOSFET layer (body layer) and drift layer (drift Layer) PN junction for constituting constitutes FWD.
Patent document 1：Japanese Unexamined Patent Publication 2004-22716 publications
But, in above-mentioned conventional structure, although even if due to not needing the FWD of tyre also can when inverter is acted Enough realize diode action and have the advantages that to need that component count is less, can minimize, cost degradation, but due in two poles Excess carriers are discharged and are flowed out as QRR Qrr when pipe is acted, so have recovery (recovery) to lose becoming Big problem.
Grid using the driving of MOSFET is proposed in order to solve the problem, before the present inventors, in diode Action when apply the slightly lower positive voltage of threshold value than MOSFET so as to the excess carriers for forming weak inversion layer, promoting injection It is compound, form depletion layer and reduce the area that uses as diode, the method that the injection to carry out excess carriers suppresses (with reference to Japanese Patent Application 2010-6549).
Loss when the method can not be made diode action increases and suppresses the injection of excess carriers, reduces instead To the effect of recovery charge Qrr.But, due to being undertaken by same grid, MOSFET is acted and excess carriers inject and suppress Action, so when excess carriers inject suppression, when interference (noise) is entered into grid and the situation of grid voltage variation Under, it is possible to the easily threshold value more than MOSFET.In the case, holding certainly for MOSFET conductings can occur although undesirable Open (self turn on).
In addition, here as insulated gate construction thyristor and said by taking the MOSFET of longitudinal type as an example It is bright, but trench gate (trench gate) type, plane (planar) type and recessed (concave) type any one all on longitudinal type MOSFET there is also above mentioned problem, also have same problem for the MOSFET of horizontal type.Additionally, the IGBT on longitudinal type and horizontal type Also there is same problem.And then, as long as by thyristor and FWD that insulated gate is constructed be connected in parallel obtained by construction Semiconductor device, then such problem be not limited to thyristor and the chips of FWD mono- for constructing insulated gate Structure, the semiconductor device for being formed at different chips also occurs.That is, by the different cores of thyristor and FWD In the case that piece is constituted, it is also possible to carry out above-mentioned excess carriers injection and suppress, even if using the method, although can carry out Restoration strategy but can also be produced from the problem of unlatching.
And then, in the past as the semiconductor switch unit used in the inverter that the electric induction for drive motor etc. is loaded Part, employs and for IGBT to be formed at different chips, the construction for being connected in parallel them from fly-wheel diode (hereinafter referred to as FWD) System.Also, for the purpose of the further miniaturization of the system, IGBT is replaced with into longitudinal type MOSFET, make to be built in vertical Body diode (body diode) in type MOSFET is used as FWD functions.
But, in the case of so by the construction of the chip of longitudinal type MOSFET and FWD mono-, in order to reduce the recovery of FWD Lose and control minority carrier lifetime etc., it is intended that injection efficiency step-down, but on the contrary, conducting (on) electricity when backflow is acted Buckling is high, return loss increase, so there is the problem of the reduction for being difficult to realize the reduction and return loss that recover loss simultaneously.
Therefore, in patent document 2, following technology is disclosed：For the chip for forming thyristor, in injection Less efficient diode area forms the deeper trench gate of depth, and negative bias is applied by trench gate when backflow is acted (bias) accumulation layer and in access areas is formed, so as to improve injection efficiency, reduces cut-in voltage.
Patent document 2：Japanese Unexamined Patent Publication 2009-170670 publications
But, as shown in above-mentioned patent document 2, the construction of the deeper trench gate of depth is formed in diode area In, it is necessary to formed depth from for constituting the trench gate of the different diode area of the trench gate of thyristor.Cause This causes the increase of manufacturing process and the increase of manufacturing cost, it is necessary to be used for being formed the operation of the different trench gate of depth.
The content of the invention
The present invention be in view of such problem and make, it is therefore an objective to provide it is a kind of be connected in parallel insulated gate construction Thyristor and fly-wheel diode semiconductor device.It is an object of the invention to provide one kind to being connected in parallel Insulated gate construction thyristor and the method that is controlled of semiconductor device of fly-wheel diode.Semiconductor device With the construction from unlatching for realizing recovering the reduction lost and being not susceptible to interference fringe.
According to the first technical scheme of the disclosure, semiconductor device has the thyristor that insulated gate is constructed and continues Stream diode.Thyristor is made up of following part：The drift layer of the 1st conductivity type；The base of the 2nd conductivity type, configuration On the drift layer of above-mentioned 1st conductivity type；The extrinsic region of component side the 1st of the 1st conductivity type, top layer of the configuration in above-mentioned base Portion, discretely configures across the base with above-mentioned drift layer, and higher than above-mentioned drift layer impurity concentration；Component side gate electrode, The above-mentioned base being clipped between above-mentioned 1st extrinsic region and above-mentioned drift layer is configured at across gate insulating film；1st conductivity type or 2nd extrinsic region of the 2nd conductivity type, contacts with above-mentioned drift layer, higher than the drift layer impurity concentration, is configured to and above-mentioned base Separate；The electrode of component side the 1st, electrically connects with the extrinsic region of said elements side the 1st and above-mentioned base；And the electrode of component side the 2nd, Electrically connected with above-mentioned 2nd extrinsic region.Thyristor, it is in above-mentioned base, positioned at across above-mentioned gate insulating film And with the part of above-mentioned gate electrode opposition side in formed transoid raceway groove.Thyristor, by the raceway groove above-mentioned Electric current is flowed through between the electrode of component side the 1st and the electrode of said elements side the 2nd.Fly-wheel diode is made up of following part：1st is conductive Type layer；2nd conductive layer, configures on above-mentioned 1st conductive layer；The electrode of diode side the 1st, is connected to above-mentioned 2nd conductivity type Layer side；And the electrode of diode side the 2nd, it is connected to above-mentioned 1st conductive layer side.Fly-wheel diode provides conductive by the above-mentioned 1st The PN junction that type layer and above-mentioned 2nd conductive layer are formed.Fly-wheel diode, in the electrode of above-mentioned diode side the 1st and above-mentioned diode Electric current is flowed through between the electrode of side the 2nd.Above-mentioned thyristor is connected in parallel with above-mentioned fly-wheel diode.The pole of above-mentioned afterflow two Pipe also has：The extrinsic region of diode side the 1st of the 1st conductivity type, configures the skin section in above-mentioned 2nd conductive layer, than above-mentioned 1st conductive layer impurity concentration is high；And diode side gate electrode, it is configured at across gate insulating film and is clipped in the 1st impurity Above-mentioned 2nd conductive layer between region and above-mentioned 1st conductive layer.Above-mentioned diode side gate electrode has the 1st grid electricity Pole.1st gate electrode provides excess carriers injection suppressor grid.When to diode side gate electrode applying grid voltage When, the 1st gate electrode forms raceway groove in a part for above-mentioned 2nd conductive layer.The part configuration of above-mentioned 2nd conductive layer In the extrinsic region of above-mentioned diode side the 1st and from the extrinsic region of above-mentioned diode side the 1st towards the midway of above-mentioned 1st conductive layer Assigned position between.
Above-mentioned semiconductor device possesses the 1st gate electrode, when apply grid voltage when, by it is in the 2nd conductive layer, From the 1st extrinsic region side to towards be located at across the 2nd conductive layer and with the 1st conductive layer of the 1st extrinsic region opposition side Half-way and form raceway groove, can make excess carriers injection suppressor grid.Thus, when dynamic from making FWD carry out diode When the timing of work is to the exchange-column shift for turning on thyristor, injection excess carriers can be suppressed and reduced and be present in Excess carriers in 2nd conductive layer, can reduce recovery loss.Further, since by only applying grid to the 1st gate electrode Pole tension forms inversion layer and does not apply any voltage to the 2nd gate electrode such that it is able to realize recovering the reduction of loss, Even if so the grid voltage for applying to be come by interference fringe to the 2nd gate electrode, being not easy to exceed turns on thyristor Threshold value.Thus, it is possible to make the semiconductor device from the construction opened for being not susceptible to be come by interference fringe.
According to the second technical scheme of the disclosure, in the control method of the semiconductor device described in above-mentioned first technical scheme In, from making above-mentioned fly-wheel diode carry out the state of diode action to cutting the state of above-mentioned thyristor conducting Change；In above-mentioned switching, before above-mentioned thyristor is turned on, grid voltage is applied to above-mentioned 1st gate electrode, The part opposed with above-mentioned 1st gate electrode across above-mentioned gate insulating film in above-mentioned 2nd conductive layer forms reversion Layer.
The control method of above-mentioned semiconductor device, from making FWD carry out the timing of diode action to making semiconductor switch During the exchange-column shift of element conductive, can suppress to inject the superfluous load that excess carriers and reducing are present in the 2nd conductive layer Stream, can reduce recovery loss.Further, since by only to the 1st gate electrode apply grid voltage come formed inversion layer and Any voltage is not applied to the 2nd gate electrode such that it is able to realize recovering the reduction of loss, even if so to the 2nd gate electrode Apply the grid voltage come by interference fringe, be not easy to exceed the threshold value for turning on thyristor.Thus, it is possible to make not Easily there is the semiconductor device from the construction opened come by interference fringe.
According to the 3rd technical scheme of the disclosure, semiconductor device possesses：1st conductive-type semiconductor layer；1st conductivity type Drift layer, configures on above-mentioned 1st conductive-type semiconductor layer, lower than above-mentioned 1st conductive-type semiconductor layer impurity concentration；2nd The base of conductivity type, forms on the contrary on above-mentioned drift layer and with above-mentioned 1st conductive-type semiconductor layer；1st conductivity type Extrinsic region, is formed on above-mentioned base, higher than above-mentioned drift layer concentration；2nd conductive-type impurity layer, is formed in than above-mentioned base The position of Qu Shen, with base contact；Groove, forms from the surface of above-mentioned base, and groove is extended along its length, and above-mentioned 1 conductive type impurity region and the configuration of above-mentioned base are in the both sides of groove；Gate insulating film, is formed in the surface of above-mentioned groove；Grid Pole electrode, in above-mentioned groove, is formed by above-mentioned gate insulating film；Surface electrode, with above-mentioned 1st conductive type impurity region And above-mentioned base electrical connection；And backplate, be formed in above-mentioned 1st conductive-type semiconductor layer as with above-mentioned drift layer The rear side in the face of opposition side.When to above-mentioned gate electrode applied voltage, positioned at the above-mentioned base of above-mentioned groove side surface Surface element forms inversion layer.Via above-mentioned 1st conductive type impurity region, inversion layer and above-mentioned drift layer, in above-mentioned surface electrode And flow through electric current between above-mentioned backplate, there is provided the vertical semiconductor switch element of transoid.In above-mentioned base and above-mentioned drift PN junction is provided between layer, there is provided carry out the fly-wheel diode of diode action.Thyristor and fly-wheel diode are configured In 1 chip.Groove has the 1st groove and the 2nd groove.1st groove is than above-mentioned base depth and reaches above-mentioned drift layer.The 2 grooves reach above-mentioned 2nd conductive-type impurity layer with the 1st groove identical depth, and than above-mentioned 2nd conductive-type impurity layer Bottom shallow.Above-mentioned gate electrode has for driving the driving gate electrode of above-mentioned vertical semiconductor switch element and being used for It is being formed with the position of above-mentioned fly-wheel diode and is being formed in above-mentioned base the diode gate electrode of inversion layer.Driving grid Pole electrode configuration is in the 1st groove.Diode gate electrode is configured at the 2nd groove.
In above-mentioned semiconductor device, formed using the 1st of same depth the, the 2nd groove and be used for driving vertical semiconductor to open Close the driving gate electrode and the diode gate electrode for forming inversion layer in FWD sides of element.Also, on two Pole pipe gate electrode, is formed on the region of the 2nd conductive-type impurity layer, has made the of configuration diode gate electrode 2 grooves are not up to the construction of drift layer.If using the semiconductor device of such construction, under making the injection efficiency of carrier Drop.Thus, even if not needing the trench-gate of different depth, it is also possible to while realizing the reduction of return loss and recovering loss Reduce.
According to the 4th technical scheme of the disclosure, the semiconductor device of above-mentioned 3rd technical scheme is being connected in series two It is individual and connect the control method of device obtained from inductive load at two contact points of above-mentioned semiconductor device, will The above-mentioned vertical semiconductor switch element possessed in the above-mentioned semiconductor device of upside is configured at is switched to from cut-off state leads Logical state, and the above-mentioned fly-wheel diode that will possess in the above-mentioned semiconductor device of downside is configured at is from turn-on action state Switch to blocking action state；Unit is switched in the above-mentioned vertical semiconductor that will possess in the above-mentioned semiconductor device of above-mentioned upside Before part switches to conducting state from cut-off state, to the above-mentioned diode possessed in the above-mentioned semiconductor device of above-mentioned downside Apply grid voltage with gate electrode, be pointed to configure at the side of above-mentioned 2nd groove of above-mentioned diode gate electrode Above-mentioned base forms inversion layer.
According to the control method of such device, decline the injection efficiency of carrier.Thus, even if not needing different depths The trench-gate of degree, it is also possible to while realizing the reduction of return loss and recovering the reduction of loss.
On above-mentioned purpose of the invention and other objects, features and advantages referring to the drawings by following detailed description meetings Become more apparent.
Brief description of the drawings
Fig. 1 be about the 1st implementation method formation have longitudinal type MOSFET and FWD semiconductor device sectional view.
Fig. 2A to Fig. 2 C is the action specification figure of the semiconductor device shown in Fig. 1.
Fig. 3 A to Fig. 3 B are the action specification figures of the then semiconductor device of Fig. 2.
Fig. 4 is the timing diagram in the action of the semiconductor device shown in Fig. 1.
Fig. 5 is the schematic perspective view of the trench gate construction of the semiconductor device shown in Fig. 1.
Fig. 6 be about the 2nd implementation method formation have longitudinal type MOSFET and FWD semiconductor device sectional view.
Fig. 7 be about the 3rd implementation method formation have longitudinal type MOSFET and FWD semiconductor device sectional view.
Fig. 8 A to Fig. 8 D are the sectional views of the formation process of the trench gate construction for representing the semiconductor device shown in Fig. 7.
Fig. 9 be about the 4th implementation method formation have longitudinal type MOSFET and FWD semiconductor device sectional view.
Figure 10 A are the semiconductor dresses of the horizontal type MOSFET and FWD for possessing trench gate construction for representing relevant 5th implementation method Layout (layout) figure put, Figure 10 B are the sectional views of the XB-XB of Figure 10 A.
Figure 11 A are the semiconductor dresses of the horizontal type MOSFET and FWD for possessing trench gate construction for representing relevant 6th implementation method The layout put, Figure 11 B are the sectional views of the XIB-XIB of Figure 11 A, and Figure 11 C are the sectional views of the XIC-XIC of Figure 11 A.
Figure 12 is the sectional view of the longitudinal type IGBT and FWD of the trench gate construction about the 7th implementation method.
Figure 13 is the sectional view of the longitudinal type IGBT and FWD of the trench gate construction about the 8th implementation method.
Figure 14 A are the semiconductor devices of the traverse type IGBT for the possessing trench gate construction and FWD for representing relevant 9th implementation method Layout, Figure 14 B are the sectional views of the XIVB-XIVB of Figure 14 A, and Figure 14 C are the sectional views of the XIVC-XIVC of Figure 14 A.
Figure 15 A are the semiconductor dresses of the traverse type IGBT for the possessing trench gate construction and FWD for representing relevant 10th implementation method The layout put, Figure 15 B are the sectional views of the XVB-XVB of Figure 15 A, and Figure 15 C are the sectional views of the XVC-XVC of Figure 15 A.
Figure 16 is the section view of the semiconductor device of the longitudinal type MOSFET and FWD that possess plane of relevant 11st implementation method Figure.
Figure 17 is the section view of the semiconductor device of the longitudinal type MOSFET and FWD that possess plane of relevant 12nd implementation method Figure.
Figure 18 A are the semiconductor devices of the horizontal type MOSFET and FWD for possessing plane for representing relevant 13rd implementation method Layout, Figure 18 B are the sectional views of the XVIIIB-XVIIIB of Figure 18 A.
Figure 19 A are the semiconductor devices of the horizontal type MOSFET and FWD for possessing plane for representing relevant 14th implementation method Layout, Figure 19 B are the sectional views of the XIXB-XIXB of Figure 19 A, and Figure 19 C are the sectional views of the XIXC-XIXC of Figure 19 A.
Figure 20 is the semiconductor device of the longitudinal type MOSFET and FWD that possess trench gate construction of relevant 15th implementation method Sectional view.
Figure 21 is the semiconductor device of the longitudinal type MOSFET and FWD that possess trench gate construction of relevant 16th implementation method Sectional view.
Figure 22 is partly leading for the longitudinal type MOSFET and FWD that possess trench gate construction of the variation about the 16th implementation method The sectional view of body device.
Figure 23 corresponds to the three-dimensional signal of Fig. 1, semiconductor device about other embodiment trench gate construction Figure.
Figure 24 corresponds to the stereogram of Fig. 1, semiconductor device about other embodiment layout example.
Figure 25 corresponds to the three-dimensional signal of Fig. 6, semiconductor device about other embodiment trench gate construction Figure.
Figure 26 corresponds to the stereogram of Fig. 6, semiconductor device about other embodiment layout example.
Figure 27 A to Figure 27 C are the stereoscopic arrangement figures of the semiconductor device about other embodiment.
Figure 28 be relevant other embodiment longitudinal type MOSFET is employed superjunction (super junction) construction The sectional view of semiconductor device.
Figure 29 is the situation that the longitudinal type IGBT and FWD of groove construction is constituted with different chips of relevant other embodiment Under schematic sectional view.
Figure 30 is the feelings that the longitudinal type MOSFET and FWD of groove construction is constituted with different chips of relevant other embodiment Sectional view under condition.
Figure 31 is the situation that the longitudinal type IGBT and FWD of groove construction is constituted with different chips of relevant other embodiment Under schematic sectional view.
Figure 32 is the feelings that the longitudinal type MOSFET and FWD of groove construction is constituted with different chips of relevant other embodiment Sectional view under condition.
Figure 33 is the sectional view of the semiconductor device 100 about the 17th implementation method.
Figure 34 is layout above semiconductor device 100 shown in Figure 33.
Figure 35 is that the distribution of the semiconductor device 100 shown in Figure 33 draws the schematic diagram for constructing.
Figure 36 is the circuit diagram of of the inverter circuit for representing the semiconductor device 100 shown in use Figure 33.
Figure 37 is the timing diagram of the action for representing the semiconductor device 100 in inverter circuit.
Figure 38 A~Figure 38 F are the action specification figures of inverter circuit and represent the state in semiconductor device 100 now Sectional view.
Figure 39 be about the 18th implementation method formation have longitudinal type MOSFET and FWD semiconductor device sectional view.
Figure 40 be about the 19th implementation method formation have longitudinal type MOSFET and FWD semiconductor device sectional view.
Figure 41 be about the 20th implementation method formation have longitudinal type IGBT and FWD semiconductor device sectional view.
Figure 42 is the figure for representing the example being laid out above the semiconductor device 100 for illustrating in other embodiments.
Specific embodiment
(the 1st implementation method)
One embodiment of the present invention is illustrated.In the present embodiment, to being formed in unit (cell) region The semiconductor device for having the longitudinal type MOSFET and FWD of n-channel type is illustrated.Fig. 1 is the semiconductor dress about present embodiment The sectional view put.Hereinafter, the construction of the semiconductor device of present embodiment is illustrated based on the figure.
The construction of the semiconductor device shown in Fig. 1 is possess the unit area and shape for being formed with longitudinal type MOSFET and FWD Into the outer region for having the pressure-resistant construction in periphery for surrounding unit area, but unit area is illustrate only in Fig. 1.On partly leading The construction beyond unit area in body device, and was in the past likewise, so only being illustrated to unit area here.
Semiconductor device uses n+Type Semiconductor substrate 1 and formed, the n+Type Semiconductor substrate 1 is by making impurity concentration be height The semi-conducting materials such as the silicon of concentration are constituted.In n+On the surface of the Semiconductor substrate 1 of type, being sequentially formed with makes impurity concentration compare n+ The n of the low concentration of Semiconductor substrate 1 of type-Type drift layer 2 and impurity concentration is set to relatively low p-type base (base region)3。
Additionally, in the skin section of p-type base 3, possessing makes impurity concentration be to compare n-The high concentration of type drift layer 2 equivalent to source The n in polar region domain+Type extrinsic region 4, and being formed with makes impurity concentration be than the p of the high concentration of p-type base 3+Type contact area (contact region)5.Also, it is formed with from substrate surface side insertion n+Type extrinsic region 4 and p-type base 3 reach n-Type The groove 6 of drift layer 2, is formed with gate insulating film 7 in the way of covering the internal face of the groove 6, and in the gate insulator The surface of film 7 possesses the gate electrode 8 being made up of DOPOS doped polycrystalline silicon (Poly-Si).By these grooves 6, gate insulating film 7 and grid Pole electrode 8 constitute trench gate construction using for example by a plurality of groove 6 along paper vertical direction arrangement form bar (stripe) The layout of shape.
Additionally, the interlayer dielectric (not shown) being made up of oxide-film etc. is formed with the way of to cover gate electrode 8, The 1st electrode 9 equivalent to source electrode is formed with the interlayer dielectric.1st electrode 9 is by being formed at interlayer dielectric Contact hole and n+Type extrinsic region 4 and p+Type contact area 5 is electrically connected.In addition, here only to the configuration in the 1st electrode 9 in contact Part in hole is shown, but the 1st electrode 9 is actually also formed with interlayer dielectric (not shown).
And then, in n+In the Semiconductor substrate 1 of type and n-The face of the opposition side of type drift layer 2 is formed with equivalent to drain electrode electricity 2nd electrode 10 of pole.By such structure, the essential structure of longitudinal type MOSFET is constituted.Also, illustrate only in Fig. 1 vertical Two units of type MOSFET, but the multiple units of longitudinal type power MOSFET set shown in Fig. 1 and Component units region.
In the longitudinal type MOSFET with such essential structure, in the semiconductor device of present embodiment, by grid Electrode 8 has made double gated architecture.Specifically, gate electrode 8 is configured to, with the 1st grid for configuring the upper side in groove 6 Pole electrode 8a and configuration are in the lower section of the 1st gate electrode 8a, i.e. 2nd gate electrode 8b of the configuration in the bottom side of groove 6.1st Gate electrode 8a injects suppressor grid and MOSFET drivings grid function, the 2nd gate electrode 8b as excess carriers With the 1st gate electrode 8a together as MOSFET drivings grid function.
1st gate electrode 8a is formed as, and depth top, the 2nd grid are reached from the depth in the centre position of p-type base 3 Electrode 8b is formed as, and n is reached from the depth in the centre position of p-type base 3-The depth of type drift layer 2.These the 1st gate electrodes 8a and the 2nd gate electrode 8b, by insulated separation, is by by configuring dielectric film 11 that oxide-film between them etc. constitutes It is capable of the structure of separately control voltage.I.e., as shown in FIG., the 1st, the 2nd gate electrode 8a, 8b is matched somebody with somebody by each grid Line and external electrical connections, can independently control the voltage for applying respectively.In addition, in figure, by the 1st gate electrode 8a and and its The gate wirings of connection are expressed as " A ", the 2nd gate electrode 8b and connected gate wirings are expressed as into " B ", based on these " A ", the statement of " B " are illustrated to the state of the 1st, the 2nd gate electrode 8a.
By such construction, composition possesses the semiconductor device of longitudinal type MOSFET and FWD, and longitudinal type MOSFET passes through Pass through n in the formation inversion layer of p-type base 3 positioned at the side of groove 6+Type extrinsic region 4 and n-Type drift layer 2 and equivalent to The n of drain region+The Semiconductor substrate 1 of type flows through electric current between source drain, the FWD make use of be formed in p-type base 3 with n-PN junction between type drift layer 2.
Then, the action of the semiconductor device for possessing longitudinal type MOSFET and FWD to constituting as described above is illustrated.
First, if the 1st electrode 9 being grounded and applying positive voltage to the 2nd electrode 10, p-type base 3 and n are formed in- PN junction between type drift layer 2 is counter voltage state.Therefore, when not ending to the 1st, the 2nd gate electrode 8a, 8b applied voltage State when, depletion layer is formed in above-mentioned PN junction, by the failure of current between source drain.
Then, when longitudinal type MOSFET is turned on, the 1st electrode 9 is being grounded and positive voltage is being applied to the 2nd electrode 10 Under state, the state of conducting is turned into by all applying positive voltage to the 1st, the 2nd gate electrode 8a, 8b.Thus, the 1st, The periphery of 2 gate electrode 8a, 8b, the part connected with groove 6 in p-type base 3 forms inversion layer, between source drain Flow through electric current.
Additionally, when ending, FWD is carried out diode action longitudinal type MOSFET, switching to the 1st electrode 9 and the 2nd electrode 10 voltages for applying, apply positive voltage and are grounded the 2nd electrode 10 to the 1st electrode 9, and stop to the 1st, the 2nd grid electricity The voltage of pole 8a, 8b applies and is set to the state ended.Thus, inversion layer is not formed in p-type base 3, so being formed in source FWD between gate-drain carries out diode action.
So, FWD is made to carry out diode action by making during longitudinal type MOSFET conductings and ending longitudinal type MOSFET When switch over, can carry out by using present embodiment semiconductor device inverter realize DC-AC conversion.
When such action is carried out, from longitudinal type MOSFET is ended and to will when making FWD carry out diode action Before longitudinal type MOSFET is switched into conducting, recover for reducing the control of loss.For the control method, with reference to expression The timing diagram in action shown in the schematic diagram and Fig. 4 of the action of the semiconductor device shown in Fig. 2A~Fig. 2 C and Fig. 3 A~Fig. 3 B Illustrate.
Fig. 2A is represented and is ended longitudinal type MOSFET and FWD is carried out the state of diode action.It is Fig. 4 by the state representation During T1, between source drain, due to being formed with using being formed in p-type base 3 and n-PN junction between type drift layer 2 FWD, if so applying positive voltage to the 1st electrode 9, applying negative voltage to the 2nd electrode 10, FWD is turned on, superfluous current-carrying Son is injected into PN junction portion.Now, the shape of the cut-off for being set to not apply the 1st, the 2nd gate electrode 8a, 8b grid voltage State.By carrying out from the state control shown in Fig. 2 B, following action is carried out.
Specifically, during Fig. 4 T2 it is initial when, as shown in Figure 2 B, make the 2nd gate electrode 8b remain turned-off and Positive voltage is applied to the 1st gate electrode 8a and the 1st gate electrode 8a is turned into the state opened.Thus, in p-type base 3 The periphery of the 1st gate electrode 8a is attracted to as the electronics of minority carrier, it is electric with the 1st grid in the side of groove 6 8a corresponding positions in pole form inversion layer 12.
Additionally, during Fig. 4 T2 it is later half, as shown in Figure 2 C, due in p-type base 3 minority carrier reduce, from And due to neutral charge condition, the hole as majority carrier in p-type base 3 also tails off.Thus, the electricity of p-type base 3 More than in the past, injection efficiency declines resistance composition.As a result, the Vf of FWD also increases, and suppresses excess carriers injection, or transoid Majority carrier in layer 12 is combined with the majority carrier in p-type base 3.
Then, as shown in Figure 3A, injected by suppressing excess carriers, originally by being largely injected into n-Type drift layer 2 And the excess carriers for accumulating reach the life-span, so not existing and disappearing.That is, common two pole is being carried out as in the past It is n in the case that pipe is acted-The state that excess carriers in type drift layer 2 are largely injected, so while excess carriers Can not reduce, but be injected by suppressing excess carriers, can reduce excess carriers.
So, n-After excess carriers in type drift layer 2 tail off, as shown in Figure 3 B, switching is to the electricity of the 1st electrode the 9 and the 2nd The voltage that pole 10 applies.That is, carry out applying negative voltage to the 1st electrode 9, apply the counter voltage of positive voltage to the 2nd electrode 10 Apply.Thus, during Fig. 4 in T3, recovery action is carried out, QRR Qrr occurs, but due to n-Type drift layer 2 Interior excess carriers are less, so, only make above-mentioned 1st gate electrode 8a turn into opening and with do not suppress excess carriers The situation of injection is compared, and QRR Qrr can be made to turn into sufficiently small value.Also, by the 1st, the 2nd gate electrode 8a, 8b apply positive voltage and are set to the state for turning on, during Fig. 4 in T4, in the 1st, the 2nd gate electrode 8a, 8b Periphery, the part that connects with groove 6 in p-type base 3 forms inversion layer, electric current flowed through between source drain, can Turn on longitudinal type MOSFET.
It is as described above, in the present embodiment, gate electrode 8 has been made possess depth it is different the 1st, the 2nd grid The double gated architecture of electrode 8a, 8b.Therefore, by only making the 1st, the 2nd gate electrode 8a, 8b in the 1st gate electrode 8a open, Inversion layer 12 can be formed to p-type base 3 and causes that the inversion layer 12 is not formed n-Type drift layer 2 and n+Type extrinsic region The depth of 4 connections.Therefore, it is possible to make the 1st gate electrode 8a inject suppressor grid function as excess carriers.
Specifically, when when making FWD carry out the timing of diode action to the exchange-column shift for turning on longitudinal type MOSFET, The control for only opening the 1st gate electrode 8a.Thus, when from making FWD carry out the timing of diode action to making longitudinal type During the exchange-column shift of MOSFET conductings, injection excess carriers can be suppressed and reduced and be present in n-Surplus in type drift layer 2 Carrier, can reduce recovery loss.
Also, according to the semiconductor device of such construction, the shape by voltage only positive to the 1st gate electrode 8a applyings Any voltage can not applied inversion layer, to the 2nd gate electrode 8b such that it is able to realize recovering the reduction of loss, even if so right 2nd gate electrode 8b applies the grid voltage come by interference fringe, is not easy to exceed the threshold value for turning on longitudinal type MOSFET.Thus, The semiconductor device from the construction opened for being not susceptible to be come by interference fringe can be realized.
In addition, gate electrode 8 substantially with is as in the past made 1 by the manufacture method of the semiconductor device for so being formed The situation of layer construction is substantially same, as long as changed just can be with for the operation to forming double gated architecture.
Specifically, it is many by that will adulterate after gate insulating film 7 is formed by thermal oxide etc. after the formation of groove 6 Crystal silicon film forming and gate electrode 8 is formed in the way of filling in groove 6, but now by DOPOS doped polycrystalline silicon be etched back (etch back) To the position that the top than p-type base 3 is deep.Then, it is many by that will adulterate again after dielectric film 11 is formed by thermal oxide etc. Crystal silicon film forming and will landfill in groove 6, this be etched back so that DOPOS doped polycrystalline silicon remain in it is higher than the top of p-type base 3 Position.In such manner, it is possible to constitute double gated architecture.
Additionally, in double gated architecture as the present embodiment, by the 1st gate electrode 8a and the 2nd gate electrode 8b points Gate wirings are not drawn not each.Thus, for example shown in the schematic perspective view of trench gate construction as shown in Figure 5, as long as in groove 6 Length direction midway (such as middle position) make the 2nd gate electrode 8b formed to substrate surface, the position draw grid Distribution or form pad (pad) in the position just can be with.In order that the 2nd gate electrode 8b is partly formed substrate surface, Can be realized by configuring etching mask at the part in eatch-back.
(the 2nd implementation method)
2nd implementation method of the invention is illustrated.The semiconductor device of present embodiment is relative to the 1st embodiment party It is likewise, so only pair real with the 1st with the 1st implementation method on other obtained by the change of structure that formula constructs trench gate The different part of mode is applied to illustrate.
Fig. 6 be about present embodiment formation have longitudinal type MOSFET and FWD semiconductor device sectional view.Reference should Figure, the semiconductor device to present embodiment is illustrated.
As shown in fig. 6, in the present embodiment, by changing the depth of groove 6 in unit, gate electrode 8 is used in Different positions changes the 1st of depth the, the 2nd gate electrode 8c, 8d compositions.1st gate electrode 8c is noted as excess carriers Enter suppressor grid function, gate electrode 8d is shallow for depth ratio the 2nd, to be not reaching to n-The depth of type drift layer 2.2nd grid Electrode 8d as MOSFET drivings grid function, to reach n-The depth of type drift layer 2.
So, gate electrode 8 has been made change depth and formed in different position the 1st, the 2nd gate electrode In the case of 8c, 8d, by making the 1st gate electrode 8c earthquakes same with the 1st gate electrode 8a illustrated in the 1st implementation method Make and make the 2nd gate electrode 8d to be acted in the same manner as the 2nd gate electrode 8b illustrated in the 1st implementation method, it is also possible to To effect in a same manner as in the first embodiment.
In addition, the semiconductor device for constructing as the present embodiment with the conventional trench gate that possesses by substantially constructing The same method of manufacture method of semiconductor device of longitudinal type MOSFET formed, but due to configuration the 1st gate electrode 8c and the 2nd The depth of the groove 6 of gate electrode 8d is different, so they are formed using respective etching mask.On the work beyond it Sequence, the manufacture method with the semiconductor device of the conventional longitudinal type MOSFET for possessing trenched gate configuration is same.
(the 3rd implementation method)
3rd implementation method of the invention is illustrated.The semiconductor device of present embodiment is also to implement relative to the 1st It is likewise, so only pair with the 1st with the 1st implementation method on other obtained by the change of structure that mode constructs trench gate The different part of implementation method illustrates.
Fig. 7 be about present embodiment formation have longitudinal type MOSFET and FWD semiconductor device sectional view.Reference should Figure, the semiconductor device to present embodiment is illustrated.
As shown in fig. 7, in the present embodiment, the depth on gate electrode 8 is all set to identical depth, but by changing Become the structure around gate electrode 8, constitute the 1st gate electrode that suppressor grid function is injected as excess carriers 8e and as MOSFET drivings the 2nd gate electrode 8f of grid function.
Specifically, make the thickness change of the gate insulating film 7 being formed in around the 1st gate electrode 8e, make to be located at grid N on the lower and is compared in the top than p-type base 3 in pole dielectric film 7-The part by the top of type drift layer 2 and than from p-type base 3 Top leave predetermined distance deep part (part 1) 7a in centre position thickness and the part (part 2) more shallow than its 7b is thicker.That is, by changing the thickness of gate insulating film 7, in the part 7a for making thickness thick, and the part 7b of thickness of thin is made Compare, uprise the threshold value that by the formation of inversion layer longitudinal type MOSFET can turn on.
Thus, when positive voltage is applied to the 1st gate electrode 8e, the thickness of thin in gate insulating film 7 is enabled to Part 7b forms inversion layer, does not form inversion layer in the thick part 7a of thickness.That is, around the 1st gate electrode 8e, can be only Formation does not reach n-The inversion layer of the depth of type drift layer 2.Thus, in the semiconductor device for constructing as the present embodiment In, by making the 1st gate electrode 8e be acted in the same manner as the 1st gate electrode 8a illustrated in the 1st implementation method and making the 2 gate electrode 8f are acted in the same manner as the 2nd gate electrode 8b illustrated in the 1st implementation method, it is also possible to obtain implementing with the 1st The same effect of mode.
In addition, the semiconductor device for constructing as the present embodiment with conventional also by substantially possessing trench gate structure The method that the manufacture method of the semiconductor device of the longitudinal type MOSFET for making is same is formed, but before the formation of gate insulating film 7, is entered Row forms the operation for damaging layer (damage layer) in the bottom for forming the groove 6 of the 1st gate electrode 8e.Fig. 8 A~Fig. 8 D are Represent the sectional view of the operation.First, as shown in Figure 8 A, by the surface configuration mask (not shown) in p-type base 3 and etch And form groove 6.Then, as shown in Figure 8 B, oxonium ion (O is carried out to the bottom for forming the groove 6 of the 1st gate electrode 8e+) or Argon ion (Ar+) ion implanting.Thus, as shown in Figure 8 C, formed in the bottom of groove 6 and damage layer 20.Also, such as Fig. 8 D institutes Show, when gate insulating film 7 is formed by thermal oxide, be then formed with the position oxidation rate for damaging layer 20 than other positions Hurry up, gate insulating film 7 is formed as, it is thicker than its part 7b by the top at the part 7a of the bottom side of groove 6.Then, lead to Crossing carries out operation same, can manufacture the semiconductor device of present embodiment.
Here, in Fig. 8 A~Fig. 8 D, n is formed to the skin section in p-type base 3+Type extrinsic region 4 and p+Type contact zone The situation that groove 6 is formed before domain 5 is illustrated, but it is also possible to groove 6 is formed after them are formed.Additionally, on The ion implanting of layer 20 is damaged to be formed, after being also not limited to the formation of groove 6, it is also possible to carried out before the formation of groove 6.
(the 4th implementation method)
4th implementation method of the invention is illustrated.The semiconductor device of present embodiment is also to implement relative to the 1st It is likewise, so only pair with the 1st with the 1st implementation method on other obtained by the change of structure that mode constructs trench gate The different part of implementation method illustrates.
Fig. 9 be about present embodiment formation have longitudinal type MOSFET and FWD semiconductor device sectional view.Reference should Figure, the semiconductor device to present embodiment is illustrated.
As shown in figure 9, in the present embodiment, the depth also on gate electrode 8 is all set to identical depth, but passes through Change the structure around gate electrode 8, constitute the 1st gate electrode that suppressor grid function is injected as excess carriers 8g and as MOSFET drivings the 2nd gate electrode 8h of grid function.
Specifically, having made the position connected with the side of groove 6 around 1 gate electrode 8g, to possess impurity dense The different p of degree-Type region (the 1st region) 30 and p+The construction in type region (the 2nd region) 31.p-Type region 30 is formed at ratio N on the lower and is compared in the top of p-type base 3-The part by the top of type drift layer 2, p+Type region 31 is formed as comparing p-Type region 30 Position that is deep and leaving predetermined distance from the top of p-type base 3 reaches n-The depth of type drift layer 2.So, due to being formed Impurity concentration different p-Type region 30 and p+Type region 31, so in p+In type region 31, with p-Type region 30 is compared, shape The threshold value for turning on longitudinal type MOSFET into inversion layer is uprised.
Thus, when positive voltage is applied to the 1st gate electrode 8g, enable in p-Transoid is formed in type region 30 Layer, in p+Inversion layer is not formed in type region 31.Thus, in the semiconductor device for constructing as the present embodiment, pass through The 1st gate electrode 8g is acted in the same manner as the 1st gate electrode 8a illustrated in the 1st implementation method and make the 2nd grid electricity Pole 8h is acted in the same manner as the 2nd gate electrode 8b illustrated in the 1st implementation method, it is also possible to obtain same with the 1st implementation method The effect of sample.
The semiconductor device for constructing as the present embodiment with conventional also by substantially possessing trench gate construction The method that the manufacture method of the semiconductor device of longitudinal type MOSFET is same is formed, but in the shape of groove 6 for making to form 1 gate electrode 8e Into carrying out p before-Type region 30 and p+The formation process in type region 31.Their formation can have p by using opening-Type area Domain 30 and p+The ion implanting of the n-type impurity that the mask of the plan forming region in type region 31 is carried out and activation are carried out.Only To form p-With formation p during type region 30+Change the dosage of n-type impurity and ion implantation energy during type region 31, with regard to energy Enough form the different p of impurity concentration-Type region 30 and p+Type region 31.
In addition, on p-Type region 30, as long as impurity concentration compares p+Type region 31 is low just can be with so p-type can also be made The former state of base 3 is used as p-The function of type region 30.I.e., it is also possible to only form p+Type region 31, makes to be located at the side of groove 6 Ratio p in p-type base 3+The part by the top of type region 31 is used as p-Type region 30.Additionally, forming p-During type region 30, and It is not limited to carry out n-type impurity the situation of ion implanting, it is also possible to make a part for p-type base 3 by ion implanting p-type impurity Carrier concentration reduction form p-Type region 30.
(the 5th implementation method)
5th implementation method of the invention is illustrated.The semiconductor device of present embodiment be by with the 1st implementation method It is same with the 1st implementation method on other obtained by the horizontal type MOSFET that same Structural application is constructed to trench gate , so only pair part different from the 1st implementation method illustrates.
Figure 10 A~Figure 10 B are the half of the horizontal type MOSFET and FWD for possessing trench gate construction for representing relevant present embodiment The figure of conductor device, Figure 10 A are layouts, and Figure 10 B are the sectional views of the XB-XB of Figure 10 A.With reference to the figure, to present embodiment Semiconductor device illustrate.
As shown in Figure 10 A~Figure 10 B, the semiconductor device of present embodiment is by constituting the n-type region of n-type drift layer 50 predetermined region forms each portion of the horizontal type MOSFET and FWD for constituting trench gate construction and constitutes.N-type region 50 can also lead to Cross n-type substrate composition, but it is also possible to be made up of N-shaped trap (well) region for being formed in Semiconductor substrate etc..
In the predetermined region of the skin section of n-type region 50, the p-type base 51 of prescribed depth is formed with, and in the p-type base Predetermined region in area 51 is formed with the n equivalent to source region more shallow than p-type base 51+The extrinsic region 52 and p of type+Type Contact area 53.These p-type bases 51, n+The extrinsic region 52 and p of type+The contact area 53 of type is with equidirectional as length direction And be extended.
Additionally, in the skin section of n-type region 50 and p-type base 51, across n+The extrinsic region 52 of type and with p+Type The opposite side of contact area 53, with from n+The insertion p-type base 51 of extrinsic region 52 of type reaches the mode shape of n-type region 50 Into there is groove 54.In the groove 54, it is formed with the 1st gate electrode 56a and the 2nd gate electrode across gate insulating film 55 The gate electrode 56 of the double gated architecture of 56b.1st gate electrode 56a and the 2nd gate electrode 56b are divided by dielectric film 55a From.1st gate electrode 56a as excess carriers inject suppressor grid function, from across gate insulating film 55 and and n+ The position that the extrinsic region 52 of type is opposed is formed to the position opposed with the half-way of p-type base 51.2nd gate electrode 56b As MOSFET drivings grid function, be formed as, from across gate insulating film 55 and with the half-way of p-type base 51 Opposed position reaches the position opposed with n-type region 50.
And then, in the skin section of n-type region 50, from p-type base 51, n+The extrinsic region 52 and p of type+The contact area of type 53 leave and form the n equivalent to drain region+The extrinsic region 57 of type.Also, it is configured to, n+The extrinsic region 52 and p of type+ The contact area 53 of type is electrically connected with the 1st electrode 58 equivalent to source electrode, and n+The extrinsic region 57 of type with equivalent to 2nd electrode 59 of drain electrode is electrically connected, and then, the 1st gate electrode 56a and the 2nd gate electrode 56b match somebody with somebody with each grid respectively Line is connected such that it is able to independently control the voltage for applying.
By such construction, composition is connected in parallel the semiconductor device of the horizontal type MOSFET and FWD of trench gate construction. In the semiconductor device, the horizontal type MOSFET of trench gate construction, by the 1st gate electrode 56a and the 2nd gate electrode 56b Both sides apply positive voltage, and raceway groove is formed in the p-type base 51 positioned at the side of gate electrode 56, thus, in the 1st electrode 58 and the Between 2 electrodes 59, flowed through along substrate level direction (transverse direction) action of electric current.The semiconductor device of such construction, stream The direction of overcurrent is different from substrate transverse direction (longitudinal direction) as the 1st implementation method, but in addition substantially move It is same to make with the 1st implementation method.
It is as described above, it is also possible to the horizontal type that Structural application in a same manner as in the first embodiment is constructed in trench gate MOSFET.If making such construction, it is also possible to obtain effect in a same manner as in the first embodiment.
In addition, the semiconductor device for constructing as the present embodiment, by substantially possessing trench gate structure with conventional The method that the manufacture method of the semiconductor device of the horizontal type MOSFET for making is same is formed, but on the 1st gate electrode 56a and the 2nd The forming method of gate electrode 56b and dielectric film 55a is different.For example, DOPOS doped polycrystalline silicon is patterned and by the 1st, the 2nd Gate electrode 56a, 56b are formed simultaneously after, when their top is covered with interlayer dielectric, by also into the 1st, Dielectric film 55a is formed between 2nd gate electrode 56a, 56b.So, then the trench gate shown in Figure 10 A~Figure 10 B can be manufactured The horizontal type MOSFET of construction.
(the 6th implementation method)
6th implementation method of the invention is illustrated.The semiconductor device of present embodiment be by with the 2nd implementation method Obtained by same Structural application to the horizontal type MOSFET of trench gate construction as explanation in the 5th implementation method, on this The essential structure of the semiconductor device of implementation method, is likewise, so only pair with the 5th implementation method not with the 5th implementation method Same part illustrates.
Figure 11 A~Figure 11 C are the half of the horizontal type MOSFET and FWD for possessing trench gate construction for representing relevant present embodiment The figure of conductor device, Figure 11 A are layouts, and Figure 11 B are the sectional views of the XIB-XIB of Figure 11 A, and Figure 11 C are the XIC- of Figure 11 A The sectional view of XIC.With reference to the figure, the semiconductor device to present embodiment is illustrated.
As shown in Figure 11 A~Figure 11 C, the semiconductor device of present embodiment, by the length for changing groove 54 in unit Degree, gate electrode 56 is constituted with the 1st of length the, the 2nd gate electrode 56c, 56d is changed on different positions.1st grid electricity Pole 56c is to inject suppressor grid function as excess carriers, and length is shorter than the 2nd gate electrode 56d, although from n+Type Extrinsic region 52 towards n+The side of extrinsic region 57 of type is extended, but is not reaching to n-type region 50, but length is, from Across gate insulating film 55 and and n+The opposed position of the extrinsic region 52 of type starts to opposed with the half-way of p-type base 51 Position untill length.2nd gate electrode 56d is that, used as MOSFET driving grid functions, length is, from across Gate insulating film 55 and and n+Untill the opposed position of the extrinsic region 52 of type starts to reach the position opposed with n-type region 50 Length.
So, gate electrode 56 has been made change length and formed in different position the 1st, the 2nd gate electrode In the case of 56c, 56d, by making the 1st gate electrode 56c same with the 1st gate electrode 56a illustrated in the 5th implementation method Ground is acted and the 2nd gate electrode 56d is acted in the same manner as the 2nd gate electrode 56b illustrated in the 5th implementation method, Effect in a same manner as in the fifth embodiment can be obtained.
In addition, the semiconductor device for constructing as the present embodiment, by substantially possessing trench gate structure with conventional The method that the manufacture method of the semiconductor device of the horizontal type MOSFET for making is same is formed, but the design for passing through mask pattern, is changed Configure the length of the groove 54 of the 1st gate electrode 56c and the 2nd gate electrode 56d.On the operation beyond it, with conventional tool The manufacture method of the semiconductor device of the horizontal type MOSFET of standby trench gate construction is same.
(the 7th implementation method)
7th implementation method of the invention is illustrated.The semiconductor device of present embodiment be by with the 1st implementation method Same Structural application is in longitudinal type IGBT rather than being applied to obtained by longitudinal type MOSFET.Semiconductor dress on present embodiment The essential structure put is likewise, so only pair part different with the 1st implementation method illustrates from the 1st implementation method.
Figure 12 is the sectional view of the longitudinal type IGBT and FWD of the trench gate construction about present embodiment.As shown in the drawing, exist In present embodiment, Semiconductor substrate 1 is made n+Type extrinsic region 1a and p+Type extrinsic region 1b is for example alternately formed It is the construction of strip.n+Type extrinsic region 1a and p+Type extrinsic region 1b can use n by by Semiconductor substrate 1+Type is constituted, led to Cross ion implanting etc. and form p+The method of type extrinsic region 1b or Semiconductor substrate 1 is used into p+Type constitute, by ion implanting Etc. forming n+Method of type extrinsic region 1a etc. is formed.
If making such construction, can be by n+Type extrinsic region 1a and n-Type drift layer 2 and p-type base 3 And p+The PN junction of type contact area 5 and constitute FWD, by p+Type extrinsic region 1b, n-Type drift layer 2, p-type base 3, n+Type is miscellaneous Matter region 4 and trench gate are constructed and constitute longitudinal type IGBT.
It is same with the 1st implementation method in the construction that the such longitudinal type IGBT for constructing trench gate and FWD is connected in parallel Sample, can make the double gated architecture with the 1st, the 2nd gate electrode 8a, 8b by gate electrode 8, make the 1st gate electrode 8a For excess carriers inject suppressor grid and IGBT driving grid functions, and make the 2nd gate electrode 8b and the 1st grid Electrode 8a is together as IGBT drivings grid function.Thereby, it is possible to obtain effect in a same manner as in the first embodiment.
(the 8th implementation method)
8th implementation method of the invention is illustrated.The semiconductor device of present embodiment be by with the 2nd implementation method Same Structural application is in longitudinal type IGBT rather than being applied to obtained by longitudinal type MOSFET.Semiconductor dress on present embodiment The essential structure put is likewise, so only pair part different with the 2nd implementation method illustrates from the 2nd implementation method.
Figure 13 is the sectional view of the longitudinal type IGBT and FWD of the trench gate construction about present embodiment.As shown in the drawing, originally Implementation method also in a same manner as in the seventh embodiment, Semiconductor substrate 1 has been made n+Type extrinsic region 1a and p+Type extrinsic region 1b for example alternately forms the construction for strip.
If making such construction, can be by n+Type extrinsic region 1a and n-Type drift layer 2 and p-type base 3 And p+The PN junction of type contact area 5 and constitute FWD, by p+Type extrinsic region 1b, n-Type drift layer 2, p-type base 3, n+Type is miscellaneous Matter region 4 and trench gate are constructed and constitute longitudinal type IGBT.
It is same with the 2nd implementation method in the construction that the such longitudinal type IGBT for constructing trench gate and FWD is connected in parallel Sample, can make gate electrode 8 has in different parts with the 1st of different depth formation the, the 2nd gate electrode 8c, 8d's Construction, makes the 1st gate electrode 8c inject suppressor grid function as excess carriers, and make the 2nd gate electrode 8d It is MOSFET driving grid functions.Thereby, it is possible to obtain effect in a same manner as in the second embodiment.
(the 9th implementation method)
9th implementation method of the invention is illustrated.The semiconductor device of present embodiment be by with the 5th implementation method Same Structural application is in traverse type IGBT rather than being applied to obtained by horizontal type MOSFET.Semiconductor dress on present embodiment The essential structure put is likewise, so only pair part different with the 1st implementation method illustrates from the 1st implementation method.
Figure 14 A~Figure 14 C are to represent the traverse type IGBT for possessing trench gate construction of relevant present embodiment and partly leading for FWD The figure of body device, Figure 14 A are layouts, and Figure 14 B are the sectional views of the XIVB-XIVB of Figure 14 A, and Figure 14 C are Figure 14 A The sectional view of XIVC-XIVC.With reference to the figure, the semiconductor device to present embodiment is illustrated.
As shown in Figure 14 A~Figure 14 C, the semiconductor device of present embodiment is configured to, by extrinsic region 57 along with n+Type The identical direction of extrinsic region 52 is extended and has alternately formed n+1st extrinsic region 57a and p of type+The 2nd of type is miscellaneous Matter region 57b.
If making such construction, can be by n+The 1st extrinsic region 57a and n-type region 50 and p-type base of type Area 51 and p+The PN junction of type contact area 53 and constitute FWD, by p+2nd extrinsic region 57b of type, n-type region 50, p-type base 51、n+The extrinsic region 52 and trench gate of type are constructed and constitute traverse type IGBT.
The construction being connected in parallel with FWD by such traverse type IGBT for constructing trench gate, it is same with the 5th implementation method Sample, can make the double gated architecture with the 1st, the 2nd gate electrode 56a, 56b by gate electrode 56, make the 1st gate electrode 56a as excess carriers inject suppressor grid and IGBT drivings grid function, and make the 2nd gate electrode 56b with 1st gate electrode 56a is together as MOSFET drivings grid function.Thereby, it is possible to obtain in a same manner as in the fifth embodiment Effect.
(the 10th implementation method)
10th implementation method of the invention is illustrated.The semiconductor device of present embodiment be by with the 6th embodiment party Obtained by the same Structural application of formula to the traverse type IGBT of trench gate construction as explanation in the 9th implementation method, on this The essential structure of the semiconductor device of implementation method is likewise, so only pair different with the 9th implementation method from the 9th implementation method Part illustrate.
Figure 15 A~Figure 15 C are to represent the traverse type IGBT for possessing trench gate construction of relevant present embodiment and partly leading for FWD The figure of body device, Figure 15 A are layouts, and Figure 15 B are the sectional views of the XVB-XVB of Figure 15 A, and Figure 15 C are the XVC- of Figure 15 A The sectional view of XVC.With reference to the figure, the semiconductor device to present embodiment is illustrated.
As shown in Figure 15 A~Figure 15 C, the semiconductor device of present embodiment also by extrinsic region 57 along with n+Type impurity range The identical direction of domain 52 is extended and has made extrinsic region 57 and alternately formed n+1st extrinsic region 57a of type and p+The construction of the 1st extrinsic region 57b of type.Also, by changing the length of groove 54 in unit, gate electrode 56 is used in The 1st of length the, the 2nd gate electrode 56c, 56d is changed on different positions to constitute.By the horizontal stroke for constructing such trench gate The construction that type IGBT and FWD are connected in parallel, in a same manner as in the sixth embodiment, can make the 1st gate electrode 56c as superfluous current-carrying Son injects suppressor grid function and makes the 2nd gate electrode 56d as IGBT driving grid functions.
In such manner, it is possible to will make gate electrode 56 on different positions change length formed the 1st, the 2nd grid electricity The form of pole 56c, 56d is applied in the traverse type IGBT of trench gate construction.Thereby, it is possible to obtain in a same manner as in the sixth embodiment Effect.
(the 11st implementation method)
11st implementation method of the invention is illustrated.The semiconductor device of present embodiment be by with the 1st embodiment party The same Structural application of formula to plane longitudinal type MOSFET obtained by, on other, be with the 1st implementation method likewise, institute Illustrated with the only pair part different from the 1st implementation method.
Figure 16 is the section view of the semiconductor device of the longitudinal type MOSFET and FWD that possess plane of relevant present embodiment Figure.With reference to the figure, the semiconductor device to present embodiment is illustrated.
As shown in figure 16, in n+N is formed with the Semiconductor substrate 1 of type-Type drift layer 2, in n-The table of type drift layer 2 The predetermined region in layer portion is formed with p-type base 3, and is formed with the n for constituting source region+Type extrinsic region 4 and p+Type contact zone Domain 5.These p-type bases 3, n+Type extrinsic region 4 and p+Type contact area 5 is extended as length direction with paper vertical direction and sets Put, by adjacent p-type base 3, n+Type extrinsic region 4 and p+Type contact area 5 separates predetermined distance configuration, and n is made in-between- Expose on the surface portion ground of type drift layer 2.Also, by p-type base 3 positioned at n+The n that type extrinsic region 4 exposes with surface- The surface element of the part between type drift layer 2 as channel region, in the channel region and n-On the exposing surface of type drift layer 2 Gate electrode 8 is formed with across gate insulating film 7.
Gate electrode 8 is extended along channel width dimension (length direction of the grade of p-type base 3), by channel length It is divided on direction and constitutes the 1st, the 2nd gate electrode 8a, 8b, is divided by insulation by the dielectric film 11 for configuring between them From.1st gate electrode 8a injects suppressor grid and MOSFET drivings grid function as excess carriers, from across grid Pole dielectric film 7 and and n+The opposed position of type extrinsic region 4 is formed to position opposed with the half-way of p-type base 3.2nd grid Pole electrode 8b is formed as MOSFET drivings grid function, from the midway across gate insulating film 7 Yu p-type base 3 The opposed position in position reaches and n-The opposed position of type drift layer 2.
Also, by possessing and n+Type extrinsic region 4 and p+Type contact area 5 electrical connection equivalent to the 1st of source electrode Electrode 9 and the 2nd electrode 10 equivalent to drain electrode is formed at the back side of Semiconductor substrate 1, constitute the half of present embodiment Conductor device.
By such construction, the semiconductor device for being connected in parallel the longitudinal type MOSFET of plane and FWD is constituted.At this In semiconductor device, the longitudinal type MOSFET of plane applies just by the 1st gate electrode 8a and the 2nd gate electrode 8b both sides Voltage, forming raceway groove in the p-type base 3 of the lower section of gate electrode 8, thus carry out with n-The surface of type drift layer 2 The action for making electric current be flowed through between the 1st electrode 9 and the 2nd electrode 10 on parallel direction.So, in the present embodiment, exist On this point of gate electrode 8 being formed in into substrate surface, raceway groove is formed in substrate surface is different from the 1st implementation method, but closes Elemental motion beyond it is same with the 1st implementation method.
It is as described above, it is also possible to by the longitudinal type MOSFET of Structural application in a same manner as in the first embodiment to plane. As such construction, it is also possible to obtain effect in a same manner as in the first embodiment.
In addition, the semiconductor device for constructing as the present embodiment with conventional by substantially possessing the vertical of plane The method that the manufacture method of the semiconductor device of type MOSFET is same is formed, but on the 1st gate electrode 8a and the 2nd gate electrode The forming method of 8b and dielectric film 11 is different.For example DOPOS doped polycrystalline silicon patterning is same by the 1st, the 2nd gate electrode 8a, 8b When formed after, when covering with interlayer dielectric their top, by also between the 1st, the 2nd gate electrode 8a, 8b And form dielectric film 11.If so, can then manufacture the longitudinal type MOSFET of the plane shown in Figure 16.
(the 12nd implementation method)
12nd implementation method of the invention is illustrated.The semiconductor device of present embodiment be by with the 2nd embodiment party Obtained by the same Structural application of formula longitudinal type MOSFET of plane to as being illustrated in the 11st implementation method.On this reality The essential structure of the semiconductor device of mode is applied, is likewise, so only pair with the 11st implementation method not with the 11st implementation method Same part illustrates.
Figure 17 is the semiconductor device of the longitudinal type MOSFET and FWD that possess plane that represent relevant present embodiment Figure.
As shown in figure 17, the semiconductor device of present embodiment is provided with different positions and is injected as excess carriers The unit of suppressor grid function and as the MOSFET drivings unit of grid function.Specifically, as mistake In the unit of surplus carrier injection suppressor grid function, possess as gate electrode 8 from across gate insulating film 7 and with n+The opposed position of type extrinsic region 4 forms the 1st gate electrode 8c to the position opposed with the half-way of p-type base 3.This Outward, in the unit as MOSFET drivings with grid function, possess from across gate insulating film as gate electrode 8 7 and and n+The opposed position of type extrinsic region 4 is passed through the position opposed with p-type base 3 and is reached and n-Type drift layer 2 is opposed The 2nd gate electrode 8d at position.
So make gate electrode 8 on different positions change length formed the 1st, the 2nd gate electrode 8c, 8d In the case of, by make the 1st gate electrode 8c with the 2nd implementation method illustrate the 1st gate electrode 8a it is same act and The 2nd gate electrode 8d is set same to be acted with the 2nd gate electrode 8b illustrated in the 2nd implementation method, it is also possible to obtain and the 2nd is real Apply the same effect of mode.
In addition, the semiconductor device for constructing as the present embodiment by substantially with the construction of the 11st implementation method The same method of manufacture method for possessing the semiconductor device of the longitudinal type MOSFET of plane is formed, and only change forms gate electrode Mask pattern when 8 just can be with.
(the 13rd implementation method)
13rd implementation method of the invention is illustrated.The semiconductor device of present embodiment be by with the 1st embodiment party The same Structural application of formula to plane horizontal type MOSFET obtained by.The essential structure of the horizontal type MOSFET of plane with the The horizontal type MOSFET of the trench gate construction illustrated in 5 implementation methods is likewise, so only pair portion different from the 5th implementation method Divide and illustrate.
Figure 18 A~Figure 18 B are the semiconductors of the horizontal type MOSFET and FWD for possessing plane for representing relevant present embodiment The figure of device, Figure 18 A are layouts, and Figure 18 B are the sectional views of the XVIIIB-XVIIIB of Figure 18 A.Though Figure 18 A are not section views Figure, but in order that figure is easily observed and partly represents shade.Hereinafter, the semiconductor device of present embodiment is entered with reference to the figure Row explanation.
As shown in Figure 18 A~Figure 18 B, p-type base 51 is formed with the predetermined region of the skin section of n-type region 50, and Predetermined region in the p-type base 51 is formed with n+The extrinsic region 52 and p of type+The contact area 53 of type.
Gate electrode 56 is extended along channel width dimension (length direction of the grade of p-type base 51), by long in raceway groove It is divided on degree direction and constitutes the 1st, the 2nd gate electrode 56a, 56b, by configures dielectric film 55a between them and quilt Insulated separation.1st gate electrode 56a injects suppressor grid and MOSFET drivings grid function as excess carriers, From across gate insulating film 55 and and n+The opposed position of type extrinsic region 52 is formed arrives opposed with the half-way of p-type base 51 Position.2nd gate electrode 56b is formed as MOSFET drivings grid function, from across gate insulating film 55 and The position opposed with the half-way of p-type base 51 reaches the position opposed with n-type region 50.
Also, by possessing and n+The extrinsic region 52 and p of type+Type contact area 53 electrical connection the 1st electrode 58 and And possess with from p-type base 51, n+Type extrinsic region 52 and p+The n that type contact area 53 leaves and formed+The electricity of type extrinsic region 57 2nd electrode 59 of connection, constitutes the semiconductor device of present embodiment.
By such construction, the semiconductor device for being connected in parallel the horizontal type MOSFET of plane and FWD is constituted.At this In semiconductor device, the horizontal type MOSFET of plane applies by the 1st gate electrode 56a and the 2nd gate electrode 56b both sides Positive voltage, is forming raceway groove in the p-type base 51 of the lower section of gate electrode 56, thus carries out in the electricity of the 1st electrode the 58 and the 2nd The action of electric current is flowed through between pole 59 along substrate level direction (transverse direction), and on the elemental motion beyond it and the 1st embodiment party Formula is same.
It is as described above, it is also possible to by the horizontal type MOSFET of Structural application in a same manner as in the first embodiment to plane. As such construction, it is also possible to obtain effect in a same manner as in the first embodiment.
In addition, the semiconductor device for constructing as the present embodiment by substantially with the conventional horizontal stroke for possessing plane The method that the manufacture method of the semiconductor device of type MOSFET is same is formed, but on the 1st gate electrode 56a and the 2nd grid electricity The forming method of pole 56b and dielectric film 55a is different.For example DOPOS doped polycrystalline silicon is patterned and by the 1st, the 2nd gate electrode When their top is covered 56a, 56b are formed simultaneously after, with interlayer dielectric, by also into the 1st, the 2nd gate electrode Dielectric film 55a is formed between 56a, 56b.If so, can then manufacture the horizontal type of the plane shown in Figure 18 A~Figure 18 B MOSFET。
(the 14th implementation method)
14th implementation method of the invention is illustrated.The semiconductor device of present embodiment be by with the 2nd embodiment party Obtained by the same Structural application of formula horizontal type MOSFET of plane to as being illustrated in the 13rd implementation method.On this reality The essential structure of the semiconductor device of mode is applied, is likewise, so only pair with the 13rd implementation method not with the 13rd implementation method Same part illustrates.
Figure 19 A~Figure 19 B are the semiconductors of the horizontal type MOSFET and FWD for possessing plane for representing relevant present embodiment The figure of device, Figure 19 A are layouts, and Figure 19 B are the sectional views of the XIXB-XIXB of Figure 19 A, and Figure 19 C are the XIXC- of Figure 19 A The sectional view of XIXC.
As shown in Figure 19 A~Figure 19 C, the semiconductor device of present embodiment is provided with different positions and is carried as surplus The unit of stream injection suppressor grid function and as the MOSFET drivings unit of grid function.Specifically, In as the unit of excess carriers injection suppressor grid function, possess as gate electrode 56 from exhausted across grid Velum 55 and and n+The opposed position of type extrinsic region 52 forms the 1st to the position opposed with the half-way of p-type base 51 Gate electrode 56c.Additionally, in the unit as MOSFET drivings with grid function, possessing as gate electrode 56 From across gate insulating film 55 and and n+The opposed position of type extrinsic region 52 is passed through the position opposed with p-type base 51 and is reached The 2nd gate electrode 56d at the position opposed with n-type region 50.
So make gate electrode 56 on different positions change length formed the 1st, the 2nd gate electrode 56c, In the case of 56d, by making the 1st gate electrode 56c same with the 1st gate electrode 56a illustrated in the 2nd implementation method dynamic Make and make the 2nd gate electrode 56d same to be acted with the 2nd gate electrode 56b illustrated in the 2nd implementation method, it is also possible to must To effect in a same manner as in the second embodiment.
In addition, the semiconductor device for constructing as the present embodiment by substantially with the construction of the 13rd implementation method The same method of manufacture method for possessing the semiconductor device of the longitudinal type MOSFET of plane is formed, and only change forms gate electrode Mask pattern when 56 just can be with.
(the 15th implementation method)
15th implementation method of the invention is illustrated.The semiconductor device of present embodiment is using only in gate electrode 8 part forms the form of double gated architecture in a same manner as in the first embodiment, with the 1st implementation method is same on other , so only pair part different from the 1st implementation method illustrates.
Figure 20 is cuing open for the semiconductor device of the longitudinal type MOSFET and FWD that possess trench gate construction of relevant present embodiment View.As shown in the drawing, in the present embodiment, the trench gate construction arranged in parallel being extended in paper vertical direction has It is a plurality of.Using the certain proportion in them as double gated architecture gate electrode 8.For example, in the example of Figure 20, it is laid out and is, For as the MOSFET drivings gate electrode 8 of single gate configuration of grid function, with the 1st gate electrode 8a and The ratio of the gate electrode 8 of the double gated architecture of 2 gate electrode 8b is 3：1.
So, it is also possible to the whole of gate electrode 8 is not made into double gated architecture and only by gate electrode 8 Divide and make double gated architecture.Additionally, in the case where such construction is made, on playing work(with grid as MOSFET drivings The gate electrode 8 of single gate configuration of energy, can be than the narrow width of gate electrode 8 of double gated architecture, it is possible to correspondingly real It is existing integrated.Smallerization or realization thereby, it is possible to realize semiconductor device are being constituted semiconductor device with same size In the case of the increase of the magnitude of current flowed through.
(the 16th implementation method)
16th implementation method of the invention is illustrated.The semiconductor device of present embodiment be by with the 1st embodiment party The structure that the same double gated architecture of formula is constituted with gate electrode 8 without dielectric film 11, be with the 1st implementation method on other Likewise, so only pair part different from the 1st implementation method illustrates.
Figure 21 is cuing open for the semiconductor device of the longitudinal type MOSFET and FWD that possess trench gate construction of relevant present embodiment View.As shown in the drawing, in the present embodiment, do not possess dielectric film between the 1st gate electrode 8a and the 2nd gate electrode 8b 11, but the 1st gate electrode 8a and the 2nd gate electrode 8b is constituted with the different material of work function, the work function based on them Difference, makes the 1st gate electrode 8a inject suppressor grid function as excess carriers, and make the 2nd gate electrode 8b and the 1st Gate electrode 8a is together as MOSFET drivings grid function.
For example, the 1st gate electrode 8a is made up of the polysilicon that p-type is adulterated, the polycrystalline that the 2nd gate electrode 8b is adulterated by N-shaped Silicon is constituted.In this case, if applying positive voltage to gate electrode 8, applied by the 1st gate electrode 8a first Plus the voltage, there is transoid in the depth until the 1st gate electrode 8a in p-type base 3.Thus, it is possible to make the 1st gate electrode 8a For excess carriers inject suppressor grid function.Then, if making to increase by the 1st grid to the voltage that gate electrode 8 applies More than the work function difference between electrode 8a and the 2nd gate electrode 8b, then p-type base 3 is sent out in the depth until the 2nd gate electrode 8b Raw transoid, forms raceway groove.Thereby, it is possible to act MOSFET.Thus, it is possible to make the 2nd gate electrode 8b and the 1st gate electrode 8a Together as MOSFET drivings grid function.
So, the 1st gate electrode 8a and the 2nd gate electrode 8b is constituted with the different material of work function, it is also possible to obtain Effect in a same manner as in the first embodiment.But, on the work function difference between the 1st gate electrode 8a and the 2nd gate electrode 8b, Need selection the 1st, material of the 2nd gate electrode 8a, 8b, so that work content between the 1st gate electrode 8a and the 2nd gate electrode 8b Number difference is smaller than the work function difference between the 1st gate electrode 8a and gate insulating film 7.If that is, the 1st gate electrode 8a is exhausted with grid Work function difference between velum 7 is smaller than the work function difference between the 1st gate electrode 8a and the 2nd gate electrode 8b, then as not right 2nd gate electrode 8b applied voltages and substantially the entirety of grid voltage is applied to the 1st gate electrode 8a and gate insulating film 7 Between.Therefore, selection the 1st, material of the 2nd gate electrode 8a, 8b, so that it meets the condition.
In addition, here to by the 1st gate electrode 8a and the 2nd gate electrode respectively with p-type adulterate or N-shaped adulterate polysilicon The situation of composition is illustrated, but it is also possible to constitute the 1st, the 2nd gate electrode by two kinds of different metal materials of work function 8a、8b。
And then, it is also possible to variation as shown in figure 22 like that, possess between the 1st, the 2nd gate electrode 8a, 8b by with The intermediate member 13 that their different materials are constituted.For example, the 1st gate electrode 8a, the gate electrode 8b of intermediate member 13 and the 2nd according to Polysilicon that the secondary polysilicon adulterated by p-type, metal, N-shaped adulterate etc. is constituted.In the case of such form, if applied Grid voltage, then as the order applying grid voltage with the 1st gate electrode 8a → intermediate member 13 → the 2nd gate electrode 8b, By controlling the voltage, the position for forming inversion layer in p-type base 3 can be made until the depth or straight of the 1st gate electrode 8a To the depth of the 2nd gate electrode 8b.If so, can also carry out the action same with the semiconductor device shown in Figure 12.Separately Outward, in the case where such construction is made, the 1st gate electrode 8a, the material of the gate electrode 8b of intermediate member 13 and the 2nd are not limited It is that what kind of combination can in metal or semi-conducting material.Additionally, in such a configuration, it is also possible in the 1st, the 2nd grid The intermediate materials 13 that not only possess 1 layer between electrode 8a, 8b, the material for being also laminated many different work functions etc..
(other embodiment)
In above-mentioned 1st implementation method, in the case where gate electrode 8 is made into double gated architecture, by the 2nd gate electrode 8b is formed to substrate surface in the midway of the length direction of groove 6.But, this only shows the lead-out mode of gate electrode 8 One, or other construction.For example, it is also possible to shown in the schematic perspective view of trench gate construction as shown in figure 23 that Sample, the 2nd gate electrode 8b is formed match somebody with somebody grid to substrate surface, in the position in the length direction front position of groove 6 Line is drawn or forms pad in the position.
Figure 24 is to represent as shown in Figure 6 to form the 2nd gate electrode 8b to lining in the midway of the length direction of groove 6 Form in the case of basal surface and in the length direction front position of groove 6 feelings for arriving substrate surface like that as shown in figure 23 The stereogram of the layout example of the semiconductor device under condition.As shown in the drawing, in the middle position of the chip for constituting semiconductor device Pad 40 is formed with, and pad 41 is formed with the end of chip.
As shown in fig. 6, the 2nd gate electrode 8b to be formed the situation to substrate surface in the midway of the length direction of groove 6 Under, the pad 40 shown in Figure 24 is used as the part being connected with the 2nd gate electrode 8b, using pad 41 as with the 1st grid The part of electrode 8a connections is used.Additionally, as shown in figure 23, by the 2nd gate electrode in the length direction front position of groove 6 In the case that 8b is formed to substrate surface, the pad 40 shown in Figure 24 is used as the part being connected with the 1st gate electrode 8a, Used pad 41 as the part being connected with the 2nd gate electrode 8b.
Additionally, in the 2nd~the 4th implementation method, to make trench gate be configured to strip situation, will the 1st gate electrode 8c, 8e, 8g and the situation that the 2nd gate electrode 8d, 8f, 8h layouts are strip are illustrated.But, these only represent single Pure one, can make various layouts.Figure 25 be represent about the 2nd implementation method the 1st, the cloth of the 2nd gate electrode 8c, 8d The stereogram of office's example.As shown in the drawing, can make and the 2nd gate electrode 8d is configured to strip and by the 1st gate electrode 8d portions Divide ground configuration such structure between the 2nd gate electrode 8d.
Figure 26 is to represent make as described above the 1st gate electrode 8c is partially disposed between the 2nd gate electrode 8d The stereogram of the layout example of the semiconductor device in the case of such structure.As shown in the drawing, semiconductor device is being constituted The middle position of chip is formed with pad 40, and is formed with pad 41 in the end of chip.
Is made as shown in Figure 25 the 1st gate electrode 8c is partially disposed in the 2nd gate electrode 8d between such knot In the case of structure, used pad 40 as the part being connected with the 1st gate electrode 8c, using pad 41 as with the 2nd grid electricity The part of pole 8d connections is used.In addition, here as the semiconductor device of the 2nd implementation method and be illustrated, but the 3rd, Same layout can also be used in 4th implementation method.
Additionally, in the respective embodiments described above, so that the 1st conductivity type is N-shaped, makes the n-channel type that the 2nd conductivity type is p-type MOSFET as a example by be illustrated, but for making the MOSFET of the p-channel type of the conductivity type transoid of each inscape also can Using the present invention.
Additionally, in above-mentioned 2nd~the 4th implementation method, MOSFET drivings grid and excess carriers note will be constituted The gate electrode 8 for entering suppressor grid is configured and by them with 1 adjacent to each other：Said as a example by the layout that 1 ratio is formed It is bright, but this is only to have enumerated simple one, or other layouts.Figure 27 A~Figure 27 C represent other layout examples Stereoscopic arrangement figure.In addition, in Figure 27 A~Figure 27 C, illustrate only the layout of gate electrode 8.Additionally, though Figure 27 is not section view Figure, but gate electrode 8 is easily used into shadow representation in order to easily watch figure.
Following layout can also as shown in fig. 27 a be made：Often configure a plurality of (being in detail in this figure two) composition Gate electrode 8d, 8f, 8h of MOSFET driving grids and configure 1 constitute excess carriers injection suppressor grid grid electricity Pole 8c, 8e, 8g.If so, then with will constitute the grid that MOSFET drivings grid and excess carriers inject suppressor grid Electrode 8 is with 1：The situation that 1 ratio is formed is compared, by increasing capacitance it is possible to increase the area of the part acted as MOSFET.
In addition it is also possible to make following layout as shown in figure 27b：Composition excess carriers are made to inject suppressor grid The central portion that gate electrode 8c, 8e, 8g are partly focused in the gate electrode 8 of a plurality of arranged in parallel grades, makes beyond it Position be constitute MOSFET driving grids gate electrode 8d, 8f, 8h.
And then, it is also possible to following layout is made as seen in fig. 27 c：The grid electricity of MOSFET driving grids will be constituted Pole 8d, 8f, 8h are a plurality of to be arranged, only partly possesses composition excess carriers injection suppressor in-between in central portion side by side The gate electrode 8c of pole, 8e, 8g, the position beyond it be only constitute the gate electrode 8d of MOSFET driving grids, 8f, 8h。
Equally, in both single gate configurations and the gate electrode 8 of double gated architecture that will be illustrated in the 15th implementation method In the case of all being formed, it is also possible to using the construction shown in Figure 27 A~Figure 27 C.I.e., it is possible to by the structure shown in Figure 27 A~Figure 27 C Into excess carriers injection suppressor grid gate electrode 8c, 8e, 8g position as double gated architecture gate electrode 8, will Constitute MOSFET driving grids gate electrode 8d, 8f, 8h position as single gate configuration gate electrode 8.
In addition, being illustrated to the layout shown in Figure 27 A~Figure 27 C here, but it can certainly be Figure 27 A~figure Layout beyond 27C.
Additionally, using longitudinal type or horizontal type and plane for the thyristor constructed as above-mentioned insulated gate The semiconductor device of MOSFET, it is also possible to using superjunction construction.
Figure 28 is for the semiconductor device with longitudinal type MOSFET of explanation in the 1st implementation method, in longitudinal type Using the figure of superjunction construction in MOSFET.Specifically, in n-Groove is formed in type drift layer 2 and imbed p-Type layer or n-N-type impurity is divided into multiple stages in the growth of type drift layer 2 carries out ion implanting, so as to possess n-Type arranges (column) 2a And p-The superjunction construction that type row 2b is alternately repeated.When so, for being constructed for superjunction, by making and the 1st embodiment party The same trench gate construction of formula, it is also possible to obtain effect in a same manner as in the first embodiment.In addition, implementing there is illustrated to the 1st The situation that mode is constructed using superjunction, but can also use superstructure certainly for the semiconductor device using other MOSFET Make.
Additionally, in the respective embodiments described above, as the thyristor that insulated gate is constructed, with longitudinal type or horizontal type and It is illustrated as a example by the MOSFET or IGBT of plane, but the MOSFET that constructs for other or IGBT, such as matrix etc. Any one thyristor can be using the present invention.Additionally, in above-mentioned 1st~the 14th implementation method, with MOSFET As a example by, but it is also possible to constitute the IGBT of same construction.That is, Semiconductor substrate 1 is passed through into n+Type extrinsic region 1a and p+Type impurity Region 1b is constituted, extrinsic region 57 is passed through into n+Type the 1st extrinsic region 57a and p+The extrinsic region 57b of type the 2nd is constituted just can be with.Enter And, in the respective embodiments described above, thyristor and the construction of the chips of FWD mono- to insulated gate is constructed are carried out Illustrate, but as long as being the semiconductor device of the construction for being connected in parallel them, be then not limited to the semiconductor for constructing insulated gate The structure of switch element and the chips of FWD mono-, the semiconductor device for being formed at different chips also can be using the present invention.
In addition, in the case of igbts, in the case where IGBT and FWD is constituted with different chips, in Semiconductor substrate 1 N need not be formed+Type extrinsic region 1a, n need not be formed in extrinsic region 57+The extrinsic region 57a of type the 1st.
Figure 29 is the schematic sectional view in the case that the longitudinal type IGBT and FWD of groove construction is constituted with different chips.This Outward, Figure 30 is the sectional view in the case that the longitudinal type MOSFET and FWD of groove construction is constituted with different chips.
As shown in these figures, in the chip of longitudinal type IGBT or longitudinal type MOSFET is formed with, by with above-mentioned each embodiment party The same construction of formula constitutes longitudinal type IGBT or longitudinal type MOSFET.That is, in p+Type or n+N is formed on the Semiconductor substrate 1 of type-Type Drift layer 2 and p-type base 3, the skin section in p-type base 3 are formed with n+Type extrinsic region 4.Also, across grid in groove 6 Pole dielectric film 7 forms gate electrode 8, is also formed with across n+Type extrinsic region 4 and p+Type contact area 5 is connected with p-type base 3 The 1st electrode 9 and the 2nd electrode 10 that is electrically connected with Semiconductor substrate 1.
In the chip for being formed with FWD, by the structure for constituting the N-shaped cathode layer 60 of the 1st conductive layer and be formed thereon P-type anode layer 61 into the 2nd conductive layer constitutes PN junction.Additionally, being electrically connected to form the 1st of anode electrode to p-type anode layer 61 Electrode 62, and the cathode electrode that is electrically connected to form to N-shaped cathode layer 60 the 2nd electrode 63.And then, in the table of p-type anode layer 61 Layer portion is formed with the n of composition 1st extrinsic region higher than the impurity concentration of N-shaped cathode layer 60+Type extrinsic region 64, and be formed with from The n+Type extrinsic region 64 reaches the groove 65 of p-type anode region 61.Also, formed across gate insulating film 66 in groove 65 There is the gate electrode 67 for constituting the 1st gate electrode.
By such construction, FWD can be formed at different chips.Also, by the way that mutual the 1st of each chip is electric Pole 9,62 electrically connects and electrically connects mutual the 2nd electrode 10,63, so as to constitute the longitudinal type that will be constituted with different chips The semiconductor device that IGBT or longitudinal type MOSFET and FWD is connected in parallel.So, it is also possible to by longitudinal type IGBT or longitudinal type MOSFET with FWD is constituted with different chips.
In the case where longitudinal type IGBT is constituted from FWD with different chips, because longitudinal type IGBT is not recovered, so Excess carriers are needed to inject suppressor grid in FWD.Thus, constitute excess carriers note by being formed to the chip for forming FWD Enter the gate electrode 67 of suppressor grid, can obtain and the same effect such as the 1st implementation method.Additionally, forming longitudinal type It is different chips from longitudinal type MOSFET and FWD is made by the construction of their chips in the case of MOSFET and FWD Situation is compared, and anyway the performance of FWD is all deteriorated.Accordingly it is also possible to FWD is constituted with the chip different from longitudinal type MOSFET And by FWD exteriors.
In addition, here to FWD constituted relative to the longitudinal type IGBT or longitudinal type MOSFET of groove construction with different chips Situation is illustrated, but is not limited to groove construction, it is also possible to longitudinal type IGBT or longitudinal type by FWD relative to plane MOSFET is constituted with different chips.In addition, however it is not limited to longitudinal type IGBT or longitudinal type MOSFET, it may be said that for traverse type IGBT or horizontal stroke Type MOSFET is also same.
Additionally, on the semiconductor device shown in Fig. 7, Fig. 9 for illustrating in the 3rd, the 4th implementation method, it is also possible to will be vertical Type IGBT is constituted from FWD with different chips.Figure 31 and Figure 32 are by the longitudinal type of groove construction for the 3rd, the 4th implementation method MOSFET and schematic sectional views of the FWD in the case of different chips composition.
In the semiconductor device shown in Figure 31, the chip on being formed with longitudinal type MOSFET has been made same with Figure 30 Construction, the chip on being formed with FWD has made the construction substantially same with Figure 30, but excess carriers injection suppressor The construction of pole is different.That is, for gate insulating film 66, than the top depth of N-shaped cathode layer 60, also, by than N-shaped cathode layer 60 Thickness is not as centre position, in the part 1 66a and shallow part 2 66b deeper than the centre position for the shallow position in top Together, make thickness thicker than part 2 66b in part 1 66a.By making such construction, will can carry out implementing with the 3rd The longitudinal type MOSFET and FWD of the semiconductor device of the same action of mode is constituted with different chips.
Additionally, in semiconductor device shown in Figure 32, the chip on being formed with longitudinal type MOSFET has also been made and Figure 30 Same construction, the chip on being formed with FWD has also made the construction substantially same with Figure 30, but in excess carriers injection Around suppressor grid, the construction of p-type anode layer 61 is different.That is, by than the top of the p-type anode layer 61 depth and than N-shaped negative electrode The shallow position in the top of side 60 as centre position, positioned at the side of groove 65 p-type anode layer 61 impurity concentration than this It is different in 2nd region 61b of the 1st shallow region 61a of centre position and depth, impurity concentration is made in the 2nd region 61b than the 1st area Domain 61a is dense.By making such construction, will can carry out action in a same manner as in the fourth embodiment semiconductor device it is vertical Type MOSFET and FWD is constituted with different chips.
(the 17th implementation method)
17th implementation method of the invention is illustrated.In the present embodiment, to being formed with n ditches in unit area The semiconductor device 100 of the longitudinal type MOSFET and FWD of channel type is illustrated.Figure 33 is the semiconductor device about present embodiment 100 sectional view.Figure 34 is layout above semiconductor device 100 shown in Figure 33.Hereinafter, based on these figures to this implementation The construction of the semiconductor device 100 of mode is illustrated.
Semiconductor device 100 shown in Figure 33 as shown in figure 34 like that, is configured to possess and is formed with longitudinal type MOSFET and FWD Unit area R1 and be formed with the outer region R2 of the pressure-resistant construction in periphery for surrounding unit area R1, but in fig. 33 only Illustrate unit area R1.Construction beyond on semiconductor device 100, unit area R1, and was in the past likewise, institute Only to be illustrated to unit area R1 here.
Semiconductor device 100 uses the n being made up of for the semi-conducting material such as silicon of high concentration impurity concentration+Type substrate the (the 1st Conductive-type semiconductor layer) 101 and formed.In n+On the surface of type substrate 101, it is sequentially formed with impurity concentration and compares n+Type substrate 101 The n of low concentration-Type drift layer 102 and impurity concentration are set to relatively low p-type base 103.And then, in n-Type drift layer 102, Equally spaced it is formed with the p-type body layer 103a of the lower position for reaching p-type base 103.P-type body layer 103a is used for constituting body two The anode of pole pipe, the body diode constitutes FWD, and p-type body layer 103a is by a direction, specifically by the paper vertical direction of Figure 33 It is extended as length direction.
Additionally, in the skin section of p-type base 103, it is to compare n to possess impurity concentration-The high concentration of type drift layer 102 equivalent to The n of source region+Type extrinsic region (the 1st conductive type impurity region) 104, and it is more highly concentrated than p-type base 103 to be formed with impurity The p of degree+Type contact area 105.Also, the multiple grooves 106 for identical depth away from substrate surface side are formed with, are somebody's turn to do with covering The mode of the internal face of groove 106 is formed with gate insulating film 107, and possesses by mixing on the surface of the gate insulating film 107 The gate electrode 108 that miscellaneous polysilicon is constituted.The groove being made up of these grooves 106, gate insulating film 107 and gate electrode 108 Grid are constructed, such as shown in figure 34 like that, for groove 106 to be arranged the layout of a plurality of strip for being formed in the same direction.
Here, gate electrode 108 is provided with two kinds, and a kind of is the driving gate electrode 108a of longitudinal type MOSFET, another It is diode gate electrode 108b.
Driving gate electrode 108a is formed in the region for not forming p-type body layer 103a, configuration driven gate electrode Groove (the 1st groove) 106a of 108a is configured to, from substrate surface side insertion n+Type extrinsic region 104 and p-type base 103 and reach To n-Type drift layer 102.Therefore, if applying grid voltage with gate electrode 108a to driving, positioned at gate electrode Inversion layer is formed in the p-type base 103 of the side of 108a, n can be made by raceway groove of the inversion layer+Type extrinsic region 104 and n- Type drift layer 102 is turned on.
Diode gate electrode 108b is formed on the region of p-type body layer 103a, configuration diode grid electricity Groove (the 2nd groove) 106b of pole 108b is more shallow than p-type body layer 103a, and bottom is located in p-type body layer 103a and does not have so as to turn into Reach n-The construction of type drift layer 102.Therefore, if applying grid voltage with gate electrode 108b to diode, it is being located at Inversion layer, but n are formed in the p-type base 103 of the side of gate electrode 108b+Type extrinsic region 104 and n-Type drift layer 102 is not Conducting.
Driving is separately carried out voltage applying with gate electrode 108a and diode with gate electrode 108b.On The formation ratio of these driving gate electrode 108a and diode gate electrode 108b is arbitrary, but in present embodiment In, alternately it is laid out successively by by driving gate electrode 108a and diode gate electrode 108b, make to form ratio and be 1：1.
Additionally, the interlayer dielectric (not shown) being made up of oxide-film etc. is formed in the way of to cover gate electrode 108, On the interlayer dielectric, in addition to the surface electrode 109 equivalent to source electrode, driving gate wirings are also formed with 110a and diode gate wirings 110b.Also, by interlayer dielectric, by surface electrode 109, driving gate wirings 110a and diode gate wirings 110b are insulated, and they are electrically connected with the hope position of MOSFET respectively.It is specific and Speech, surface electrode 109 by be formed at the contact hole of interlayer dielectric and and n+Type extrinsic region 104 and p+Type contact area 105 Electrical connection.Additionally, driving gate wirings 110a and diode gate wirings 110b is also by being formed at interlayer dielectric Contact hole and electrically connected with driving gate electrode 108a and diode gate electrode 108b respectively.
In addition, the substantially whole region for making unit area R1 is surface electrode 109, by driving gate wirings 110a and two Pole pipe gate wirings 110b avoids surface electrode 109 and is laid out.For example, driving gate wirings 110a and diode grid Distribution 110b is winding around the R1 of unit area, and as shown in figure 34 like that, the driving to configuring in the corner of paper upper right is used Gate pads 111a and diode gate pads 111b are electrically connected.
In the case, if the distribution made for example shown in Figure 35 draws the construction of the schematic diagram of construction, distribution cloth Office becomes easy.That is, on driving gate wirings 110a, it is connected to the one of the length direction of each driving gate electrode 108a Side, and it is winding to driving gate pads 111a.Additionally, on diode gate wirings 110b, being connected to each diode It is with the another side of the length direction of gate electrode 108b and winding to diode gate pads 111b.That is, by each distribution 110a, 110b draw on chip to different directions.If so, then in the periphery of unit area R1, can not make by The layout that driving gate wirings 110a and diode gate wirings 110b both sides overlap, can be laid out distribution becomes Easily.
And then, in n+In type substrate 101 and n-The face of the opposition side of type drift layer 2 is formed with the back of the body equivalent to drain electrode Face electrode 112.In fig. 33, illustrate only and possess 1 part of the FWD of unit between two longitudinal type MOSFET of unit, But arranged and the unit area R1 of the layout of pie graph 34 by by many units alternatelies of such longitudinal type MOSFET and FWD.
By such construction, composition possesses the semiconductor device 100 of longitudinal type MOSFET and FWD, and longitudinal type MOSFET leads to Cross and forming inversion layer in the p-type base 103 of the side of groove 106, electric current is passed through n+Type extrinsic region 104 and n-Type Drift layer 102 and n+Between type substrate 101 flows through source drain, the FWD is using the p-type body layer 103a in composition anode and composition The n of negative electrode-The PN junction formed between type drift layer 102.
Then, the action to the semiconductor device 100 for possessing the longitudinal type MOSFET and FWD that constitute as described above is said It is bright.
First, the elemental motion of the longitudinal type MOSFET and FWD to possessing in the semiconductor device 100 of said structure is carried out Explanation.
(1) if surface electrode 109 being grounded and applying positive voltage to backplate 112, it is formed in p-type body layer 103a and n-PN junction between type drift layer 102 is counter voltage state.Therefore, do not apply when to each gate electrode 108a, 108b Voltage and be cut-off state when, depletion layer is formed in above-mentioned PN junction, by the failure of current between source drain.
(2) then, when longitudinal type MOSFET is turned on, surface electrode 109 is being grounded and backplate 112 is being applied just Voltage in the state of, the state of conducting is turned into by applying positive voltage to driving gate electrode 108a.Thus, driving The periphery of gate electrode 108a is employed, the part connected with groove 106 in p-type base 103 forms inversion layer, as Raceway groove and electric current is flowed through between source drain.
(3) when making FWD carry out diode action, positive voltage is applied to surface electrode 109 and backplate 12 is connect Ground, and the state that will apply to stop and turn into cut-off to the voltage of each gate electrode 108a, 108b.Thus, in p-type base Inversion layer is not formed in 103, therefore is formed in the FWD between source drain carries out diode action.
So, in the semiconductor device for constituting as in the present embodiment, longitudinal type MOSFET can be switched to conducting Or cut-off state or FWD is carried out diode action.Also, by using the semiconductor device of such construction, carry out for The reduction for realizing return loss simultaneously and the control of the reduction for recovering loss.
On the control method, illustrated using the circuit example of the semiconductor device 100 using present embodiment.Figure 36 It is the circuit diagram of of the inverter circuit for representing the semiconductor device 100 for using present embodiment.Figure 37 is to represent inversion The timing diagram of the action of the semiconductor device 100 in device circuit.In Figure 37 ,+V1 and+V2 both can be identical voltage, The different voltage of performance can be corresponded to.Additionally, at XXXVIIA, (i.e. in MOS2 before MOS1 will be turned on again Before recovery action will being carried out), turn on FWD2.At XXXVIIB, MOS1's turns on the cut-off of FWD2 as needed again Can also overlap (overlap).Figure 38 A~Figure 38 F are the action specification figures of inverter circuit and represent that semiconductor now is filled The sectional view of the state in 100 is put, it is corresponding with state (1)~(4) in Figure 37.Here, in Figure 38 C and Figure 38 D, represent logical The diode action that carrier injection brings is crossed, in Figure 38 E and Figure 38 F, the formation by inversion layer is represented, is easily carried out The extraction of electronics, hole (hole) disappear.
The semiconductor device 100 for constituting as in the present embodiment is for example connected in series two like that as shown in figure 36, For being used in the half-bridge circuit for driving inductive load 120.Also, two semiconductor devices 100 are separately positioned on by switching In longitudinal type MOSFET on or off, the sense of current that is supplied to inductive load 120 from dc source 121 of switching, by This drives inductive load 120.In the following description, on being arranged in two semiconductor devices 100 for constituting half-bridge circuit Longitudinal type MOSFET, FWD in the semiconductor device 100 of side (high side) are referred to as MOS1, FWD1, will be arranged on downside (low Side longitudinal type MOSFET, FWD2 in semiconductor device 100) is referred to as MOS2, FWD2, and MOS1 is switched from the state of conducting Illustrate to end and as a example by control method when switching to conducting state again.In addition, in Figure 38 A~Figure 38 F State in semiconductor device 100, the semiconductor device 100 to downside is shown.
First, as the state (1) in Figure 37, be the driving gate electrode 108a of MOS1 is applied positive voltage (+ V1 driving gate electrode 108a and the diode gate electrode 108b of each FWD1, FWD2), to MOS2 does not apply grid electricity The state of pressure.Now, MOS1 conductings, based on the supply from power supply 121, with the path pair shown in the arrow of Figure 38 A~Figure 38 F Inductive load 120 flows through electric current.Also, due to p-type body layer 103a and n in MOS2-The PN junction formed between type drift layer 102 It is counter voltage state, so as shown in Figure 38 A~Figure 38 F, being formed in above-mentioned PN junction between depletion layer, source drain Electric current be cut off.
Then, as the state (2) in Figure 37, stop to the driving of the MOS1 applying of the positive voltage of gate electrode 108a And end MOS1.Now, due to be allowed in the inductive load 20 before the electric current that flows through flow continuously through, so with Figure 38 A~ The path shown in arrow in Figure 38 F, induced-current is flowed through by the path of FWD2.Therefore, based on by flowing through induced electricity The potential difference at the two ends of the brought inductive load 120 of stream, FWD2 conductings, in the semiconductor device 100 of downside, is passed through The diode action that carrier injection brings, as the state that there is electronics and hole.
Accordingly, as the state (3) in Figure 37, after MOS1 is turned on by after the stipulated time, and after Figure 37 in state (4) and will make again MOS1 turn on before, keep make MOS1, MOS2 end in the state of, it is right The diode of FWD2 applies positive voltage (+V2) with gate electrode 108b.Then, the electronics in p-type base 103 is attracted to The diode of the FWD2 periphery of gate electrode 108b, in the side of groove 106 with diode gate electrode 108b pairs The position answered forms inversion layer.Therefore, by inversion layer, electronics is drawn into surface electrode 109.Additionally, hole also with electronics It is combined and can easily disappears.Thus, it is possible to loss when reducing the injection efficiency of the carrier to FWD2, reduction recovery.
As described above, the semiconductor device 100 of present embodiment forms vertical for driving using the groove 6 of same depth Diode gate electrode 108b of the driving of type MOSFET with gate electrode 108a and for forming inversion layer in FWD sides.And And, on diode gate electrode 108b, formed in the region of p-type body layer 103a is formed with, it is configured to configure diode N is not up to the groove 106b of gate electrode 108b-The construction of type drift layer 102.
Using the semiconductor device 100 of such construction, before will being again switched to conducting after MOS1 cut-offs, lead to Cross and is applied by positive voltage and inversion layer is formed for diode gate electrode 108b, so that the injection efficiency reduction of carrier. Thus, even if not needing the trench-gate of different depth, it is also possible to while realizing the reduction of return loss and recovering the drop of loss It is low.
Additionally, the semiconductor device 100 of such construction substantially can be by general by longitudinal type with conventional The same manufacture method of the semiconductor device of MOSFET and FWD single chips is manufactured, but due to making groove 106a, 106b be phase Same depth, it is possible to them are formed with same operation.It is thus possible to enough realize the manufacturing process of semiconductor device 100 Simplification.
In addition, here, the voltage that will be applied with gate electrode 108a to the driving of MOS1 is as+V1, by the two of FWD2 The voltage that pole pipe gate electrode 108b applies is illustrated as+V2, but these V1, V2 both can be identical voltage The different voltage of the performance of longitudinal type MOSFET or FWD can also be corresponded to.Additionally, as shown in figure 37, making MOS1 again Overlapped during ending during conducting and by FWD2, as long as but be arranged as required on it just can be with, it is also possible to do not overlap.
(the 18th implementation method)
18th implementation method of the invention is illustrated.The semiconductor device of present embodiment is to the 17th implementation method Using obtained by superjunction construction, being likewise, so only pair different with the 17th implementation method from the 17th implementation method on other Part illustrate.
Figure 39 be about present embodiment formation have longitudinal type MOSFET and FWD semiconductor device sectional view.As being somebody's turn to do Shown in figure, to n-Type drift layer 102 forms p-type row 130, constitutes by n-In type drift layer 102 by p-type row 130 every portion The superjunction that the N-shaped row 131 and p-type row 130 for dividing bring is constructed.P-type row 130 and N-shaped row 131 are with paper vertical direction as length Direction and be extended, strip is turned into by being alternately arranged.Make the forming position of p-type row 130 and p-type body layer 103a mono- Cause.
So, it is also possible to which semiconductor device 100 is constructed using superjunction.Constructed by using such superjunction, can obtained To desired pressure-resistant and further reduce conducting resistance.
In addition, in the case that the such superjunction of explanation is constructed in using present embodiment, if in diode grid electricity The p-type row 130 formed below of pole 108b, then can make diode gate electrode 108b not with n-The phase of type drift layer 102 The construction for connecing.Therefore, in the case where being constructed using superjunction, even if there is no p-type body layer 103a, by diode grid electricity Pole 108b applies positive voltage and forms inversion layer, and the injection efficiency of carrier can also declined.Thus, with above-mentioned each embodiment party Formula is same, even if not needing the trench-gate of different depth, it is also possible to while realizing the reduction of return loss and recovering loss Reduce.
(the 19th implementation method)
19th implementation method of the invention is illustrated.The semiconductor device 100 of present embodiment is also real to the 17th Apply mode using obtained by superjunction construction, with the 17th implementation method be on other likewise, so only pair with the 17th embodiment party The different part of formula illustrates.
Figure 40 be about present embodiment formation have longitudinal type MOSFET and FWD semiconductor device 100 sectional view.Such as Shown in the figure, present embodiment also possesses the superjunction formed by N-shaped row 131 and p-type row 130 and constructs.But, p-type row 131 are not made Forming position it is consistent with the forming position of p-type body layer 103a, and make its with forming position and grid that p-type body layer 103a is consistent The forming position of the gate electrode 108 of the both sides adjoining of electrode 108 is consistent.
In the case of the semiconductor device 100 of such construction, in gate electrode 108 with p-type body layer 103a and p-type The consistent gate electrode 108 of the forming position of row 130 is diode gate electrode 108, is formed in and do not formed p-type body layer 103a And the gate electrode 108 of the position of p-type row 130 is driving gate electrode 108a.Also, the formation in semiconductor device 100 There is the part of diode gate electrode 108b as FWD functions, the part for being formed with driving gate electrode 108a is made It is longitudinal type MOSFET functions.
So, it is also possible to which diode is corresponded into p-type body layer 103a and the both sides of p-type row 130 and shape with gate electrode 108b Into.In this case, the formation ratio of driving gate electrode 108a and diode gate electrode 108b is not 1：1, But it is the value that can arbitrarily set on the formation ratio, so not having special problem.
(the 20th implementation method)
20th implementation method of the invention is illustrated.The semiconductor device 100 of present embodiment is that instead of the 17th The longitudinal type MOSFET that is illustrated in implementation method and possess the structure of longitudinal type IGBT, with the 17th implementation method be same on other , so only pair part different from the 17th implementation method illustrates.
Figure 41 be about present embodiment formation have longitudinal type IGBT and FWD semiconductor device 100 sectional view.As being somebody's turn to do Shown in figure, in the present embodiment, instead of the n illustrated in the 17th implementation method+Type substrate 101 and in n-Type drift layer 102 Rear side possess p equivalent to collector region+Type impurity layer (the 2nd conductive-type semiconductor layer) 141 and equivalent to cathodic region The n in domain+Type impurity layer (the 1st conductive-type semiconductor layer) 142.The n of the semiconductor device 100 of the present embodiment for so constituting+Type Extrinsic region 104 plays a part of as emitter region, to be connected in parallel the construction of longitudinal type IGBT and FWD.
So, if semiconductor device 100 to be made the construction for possessing longitudinal type IGBT and FWD, it is also possible to by with p-type The corresponding positions of body layer 103a formed diode gate electrode 108b, make groove 106b not with n-What type drift layer 102 connected Construction, obtains the effect same with the 17th implementation method.
(other embodiment)
Additionally, in the respective embodiments described above, so that the 1st conductivity type is N-shaped, the n-channel type that the 2nd conductivity type is p-type It is illustrated as a example by longitudinal type MOSFET or longitudinal type IGBT, but for making the p-channel type of the conductivity type transoid of each inscape Longitudinal type MOSFET or longitudinal type IGBT also can be using the present invention.
Additionally, the detailed construction of the semiconductor device 100 for illustrating in the respective embodiments described above, can suitably set Meter change.For example, as being illustrated in above-mentioned 17th implementation method, being used with gate pads 111a and diode using by driving Gate pads 111b is arranged in 1 construction in corner of chip.But, such layout is only to represent simple one Example, for example as shown in figure 42 above layout it is such, it would however also be possible to employ by driving gate pads 111a and diode grid Pole pad 111b is arranged respectively at the such layout in diagonal position of chip.
And then, it is also possible to threshold value ratio when making to form inversion layer by diode gate electrode 108b is by driving grid electricity Threshold value during pole 108a formation inversion layers is low.If so, can then be held with the vicinity of gate electrode 108b using diode Change places to form many inversion layers, it is possible to easily carrying out the extraction of carrier.Additionally, on for each gate electrode The gate driving circuit side of 108 applied voltages, also due to the applied voltage to diode gate electrode 108b can be reduced, institute So that circuit burden can be mitigated.
It is disclosed above including following form.
According to the first technical scheme of the disclosure, semiconductor device has the thyristor that insulated gate is constructed and continues Stream diode.Thyristor is made up of following part：The drift layer of the 1st conductivity type；The base of the 2nd conductivity type, configuration On the drift layer of above-mentioned 1st conductivity type；The extrinsic region of component side the 1st of the 1st conductivity type, top layer of the configuration in above-mentioned base Portion, is configured to across the base from above-mentioned drift leafing, and higher than above-mentioned drift layer impurity concentration；Component side gate electrode, every Gate insulating film and be configured at the above-mentioned base being clipped between above-mentioned 1st extrinsic region and above-mentioned drift layer；1st conductivity type or 2nd extrinsic region of 2 conductivity types, contacts with above-mentioned drift layer, higher than the drift layer impurity concentration, discretely matches somebody with somebody with above-mentioned base Put；The electrode of component side the 1st, electrically connects with the extrinsic region of said elements side the 1st and above-mentioned base；The electrode of component side the 2nd, it is and above-mentioned 2nd extrinsic region is electrically connected.Thyristor, it is in above-mentioned base, positioned at across above-mentioned gate insulating film and with it is upper State the raceway groove of formation transoid in the part of gate electrode opposition side.Thyristor is by the raceway groove in said elements side the Electric current is flowed through between 1 electrode and the electrode of said elements side the 2nd.Fly-wheel diode is made up of following part：1st conductive layer；2nd Conductive layer, configures on above-mentioned 1st conductive layer；The electrode of diode side the 1st, is connected to above-mentioned 2nd conductive layer side；Two poles The electrode of tube side the 2nd, is connected to above-mentioned 1st conductive layer side.Fly-wheel diode is provided by above-mentioned 1st conductive layer and the above-mentioned 2nd The PN junction that conductive layer is formed.Fly-wheel diode, between the electrode of above-mentioned diode side the 1st and the electrode of above-mentioned diode side the 2nd Flow through electric current.Above-mentioned thyristor is connected in parallel with above-mentioned fly-wheel diode.Above-mentioned fly-wheel diode also has：1st The extrinsic region of diode side the 1st of conductivity type, configures the skin section in above-mentioned 2nd conductive layer, more miscellaneous than above-mentioned 1st conductive layer Matter concentration is high；Diode side gate electrode, is configured at across gate insulating film and is clipped in the 1st extrinsic region with the above-mentioned 1st conduction Above-mentioned 2nd conductive layer between type layer.Above-mentioned diode side gate electrode has the 1st gate electrode.1st gate electrode is provided Excess carriers inject suppressor grid.When grid voltage is applied to the diode side gate electrode, the 1st gate electrode is above-mentioned Raceway groove is formed in a part for 2nd conductive layer.The part configuration of above-mentioned 2nd conductive layer is miscellaneous in above-mentioned diode side the 1st Matter region and from the extrinsic region of above-mentioned diode side the 1st towards between the assigned position of the midway of above-mentioned 1st conductive layer.
Above-mentioned semiconductor device possesses the 1st gate electrode, when apply grid voltage when, by it is in the 2nd conductive layer, It is located at and the 1st conductive layer of the 1st extrinsic region opposition side from the 1st extrinsic region side to direction across the 2nd conductive layer Half-way forms raceway groove, can make excess carriers injection suppressor grid.Thus, when from making FWD carry out diode action Timing to the exchange-column shift for turning on thyristor when, injection excess carriers and reducing can be suppressed and be present in the Excess carriers in 2 conductive layers, can reduce recovery loss.Further, since by only applying grid to the 1st gate electrode Voltage and form inversion layer, any voltage do not applied to the 2nd gate electrode and can realize recover loss reduction, even if so The grid voltage for applying to be come by interference fringe to the 2nd gate electrode, is not easy to exceed the threshold value for opening thyristor.Cause And, the semiconductor device from the construction opened for being not susceptible to interference fringe can be made.
Instead scheme, above-mentioned thyristor and above-mentioned fly-wheel diode can be only fitted in 1 chip.On It is above-mentioned 1st conductive layer to state drift layer.Above-mentioned base is above-mentioned 2nd conductive layer.The electrode of component side the 1st is diode side 1 electrode；The electrode of component side the 2nd is the electrode of diode side the 2nd.The extrinsic region of component side the 1st is the extrinsic region of diode side the 1st. Component side gate electrode is diode side gate electrode.
And then, Ke Yishi, above-mentioned 1st gate electrode is across above-mentioned gate insulating film from the extrinsic region of said elements side the 1st It is configured to the assigned position of the midway of above-mentioned base.It is such to be configured to be realized by double gated architecture.
Instead scheme, said elements side gate electrode can have the 2nd gate electrode.2nd gate electrode is across upper State gate insulating film and be configured to above-mentioned drift layer from the assigned position of the midway of above-mentioned base.It is above-mentioned when grid voltage is applied to During component side gate electrode, above-mentioned 1st gate electrode and above-mentioned 2nd gate electrode are used as thyristor driving grid Function.Thyristor driving grid formed in above-mentioned base by the extrinsic region of said elements side the 1st with it is upper State the raceway groove of drift layer connection.
And then, semiconductor device can also have from the above-mentioned base of extrinsic region insertion of said elements side the 1st and reach State the groove of drift layer.Above-mentioned 1st gate electrode and above-mentioned 2nd gate electrode are matched somebody with somebody in the way of clipping dielectric film between them Put in above-mentioned groove, there is provided bigrid type trench gate is constructed.There is above-mentioned thyristor trench gate to construct.
And then, above-mentioned 2nd extrinsic region can be the Semiconductor substrate of the 1st conductivity type.Above-mentioned drift layer configuration is above-mentioned In Semiconductor substrate.The part of side positioned at above-mentioned groove of the above-mentioned thyristor in above-mentioned base forms ditch Road.Above-mentioned thyristor is the longitudinal type MOSFET that electric current is flowed through along the vertical direction of above-mentioned Semiconductor substrate.
Instead scheme, above-mentioned 2nd extrinsic region can be the Semiconductor substrate also containing the 2nd conductivity type part.On Drift layer is stated to configure in above-mentioned Semiconductor substrate.Above-mentioned thyristor in above-mentioned base positioned at above-mentioned groove The part of side forms raceway groove.Above-mentioned thyristor is to flow through the vertical of electric current along the vertical direction of above-mentioned Semiconductor substrate Type IGBT.
Instead scheme, above-mentioned base can be only fitted to the skin section of above-mentioned drift layer.The impurity range of said elements side the 1st Skin section of the configuration of territory in the base.Above-mentioned 2nd extrinsic region has the 1st conductivity type.Above-mentioned 2nd extrinsic region configuration is above-mentioned The skin section of drift layer, and separated with above-mentioned base.Above-mentioned groove sets along the direction extension parallel with the surface of above-mentioned drift layer Put.Above-mentioned groove reaches above-mentioned drift layer from the above-mentioned above-mentioned base of 1st extrinsic region insertion.Above-mentioned thyristor is upper The part for stating the side positioned at above-mentioned groove in base forms raceway groove.Above-mentioned thyristor is edge and above-mentioned drift layer The parallel horizontal type MOSFET for flowing transversely through electric current in surface.
Instead scheme, above-mentioned base can be only fitted to the skin section of above-mentioned drift layer.The impurity range of said elements side the 1st Skin section of the configuration of territory in the base.Above-mentioned 2nd extrinsic region also includes the 2nd conductivity type part.Above-mentioned 2nd extrinsic region configuration In the skin section of above-mentioned drift layer, separated with above-mentioned base.Above-mentioned groove prolongs along the direction parallel with the surface of above-mentioned drift layer Stretch setting.Above-mentioned groove reaches above-mentioned drift layer from the above-mentioned above-mentioned base of 1st extrinsic region insertion.Above-mentioned thyristor The part of the side positioned at above-mentioned groove in above-mentioned base forms raceway groove.Above-mentioned thyristor is edge and above-mentioned drift Move the parallel traverse type IGBT for flowing transversely through electric current in the surface of layer.
Instead scheme, above-mentioned 2nd extrinsic region can be the Semiconductor substrate of the 1st conductivity type.Above-mentioned drift layer is matched somebody with somebody Put in above-mentioned Semiconductor substrate.In above-mentioned base between the extrinsic region of said elements side the 1st and above-mentioned drift layer Part surface on, be configured with above-mentioned 1st gate electrode and above-mentioned 2nd gate electrode across above-mentioned gate insulating film.It is above-mentioned Thyristor, in the surface portion of above-mentioned base, along the horizontal shape parallel with the in-plane of above-mentioned Semiconductor substrate Into raceway groove.Above-mentioned thyristor is the longitudinal type of the plane that electric current is flowed through along the vertical direction of above-mentioned Semiconductor substrate MOSFET。
Instead scheme, above-mentioned 2nd extrinsic region can be the also Semiconductor substrate including the 2nd conductivity type part.On Drift layer is stated to configure in above-mentioned Semiconductor substrate.In above-mentioned base positioned at above-mentioned 1st extrinsic region and above-mentioned drift layer Between part surface on, be configured with above-mentioned 1st gate electrode and above-mentioned 2nd gate electrode across above-mentioned gate insulating film. Above-mentioned thyristor, on the surface of above-mentioned base, along the horizontal shape parallel with the in-plane of above-mentioned Semiconductor substrate Into raceway groove.Above-mentioned thyristor is the longitudinal type of the plane that electric current is flowed through along the vertical direction of above-mentioned Semiconductor substrate IGBT。
Instead scheme, above-mentioned base can be only fitted to the skin section of above-mentioned drift layer.The impurity range of said elements side the 1st Skin section of the configuration of territory in the base.Above-mentioned 2nd extrinsic region has the 1st conductivity type.Above-mentioned 2nd extrinsic region configuration is above-mentioned The skin section of drift layer, separates with above-mentioned base.In above-mentioned base positioned at above-mentioned 1st extrinsic region and above-mentioned drift layer it Between part surface on, be configured with above-mentioned 1st gate electrode and above-mentioned 2nd gate electrode across above-mentioned gate insulating film.On Thyristor is stated, in the surface element of the above-mentioned base opposed with above-mentioned 1st gate electrode and above-mentioned 2nd gate electrode Point, horizontal it is upwardly formed raceway groove parallel with the surface of above-mentioned drift layer.Above-mentioned thyristor is edge and above-mentioned drift Flow through the horizontal type MOSFET of the plane of electric current in the parallel direction in surface of layer.
Instead scheme, above-mentioned base can also configure the skin section in above-mentioned drift layer.The impurity of said elements side the 1st Region configures the skin section in the base.Above-mentioned 2nd extrinsic region has the 1st conductivity type.Above-mentioned 2nd extrinsic region configuration is upper The skin section of drift layer is stated, is separated with above-mentioned base.In above-mentioned base positioned at above-mentioned 1st extrinsic region and above-mentioned drift layer Between part surface on, be configured with above-mentioned 1st gate electrode and above-mentioned 2nd gate electrode across above-mentioned gate insulating film. Above-mentioned thyristor, on the surface of the above-mentioned base opposed with above-mentioned 1st gate electrode and above-mentioned 2nd gate electrode, Horizontal raceway groove is upwardly formed parallel with the surface of above-mentioned drift layer.Above-mentioned thyristor along with above-mentioned drift layer Flow through the traverse type IGBT of the plane of electric current in the parallel direction in surface.
Instead scheme, said elements side gate electrode can have the 2nd gate electrode.Above-mentioned 1st gate electrode with 2nd gate electrode is separated.Above-mentioned 2nd gate electrode is configured to above-mentioned across above-mentioned gate insulating film from above-mentioned 1st extrinsic region Drift layer.When grid voltage is applied into said elements side gate electrode, above-mentioned 2nd gate electrode is used as semiconductor switch unit Part drives and uses grid function.Thyristor driving grid is formed above-mentioned 1st extrinsic region to above-mentioned base The raceway groove being connected with above-mentioned drift layer.
And then, semiconductor device can also have：1st groove, from said elements side the 1st, extrinsic region reaches above-mentioned base Area；And the 2nd groove, reach above-mentioned drift layer from the above-mentioned base of extrinsic region insertion of said elements side the 1st.Above-mentioned 1st grid In above-mentioned 1st groove, the 2nd gate electrode is configured in 2nd groove different from the 1st groove electrode configuration, there is provided trench gate Construction.There is above-mentioned thyristor trench gate to construct.
Instead scheme, above-mentioned 2nd extrinsic region can be the Semiconductor substrate of the 1st conductivity type.Above-mentioned drift layer is matched somebody with somebody Put in above-mentioned Semiconductor substrate.Above-mentioned 1st groove is configured to the predetermined bits of the midway of above-mentioned base from above-mentioned 1st extrinsic region Put.Above-mentioned 2nd groove reaches above-mentioned drift layer from the above-mentioned above-mentioned base of 1st extrinsic region insertion.Above-mentioned thyristor The part of the side positioned at above-mentioned 2nd groove in above-mentioned base forms raceway groove.Above-mentioned thyristor is along above-mentioned The vertical direction of Semiconductor substrate flows through the longitudinal type MOSFET of electric current.
Instead scheme, above-mentioned 2nd extrinsic region can be the Semiconductor substrate containing the 2nd conductivity type part.It is above-mentioned Drift layer is configured in above-mentioned Semiconductor substrate.Above-mentioned 1st groove is configured to the midway of above-mentioned base from above-mentioned 1st extrinsic region Assigned position.Above-mentioned 2nd groove reaches above-mentioned drift layer from the above-mentioned above-mentioned base of 1st extrinsic region insertion.Above-mentioned semiconductor The part of side positioned at above-mentioned 2nd groove of the switch element in above-mentioned base forms raceway groove.Above-mentioned thyristor It is the longitudinal type IGBT that electric current is flowed through along the vertical direction of above-mentioned Semiconductor substrate.
Instead scheme, above-mentioned base can be only fitted to the skin section of above-mentioned drift layer.The impurity range of said elements side the 1st Skin section of the configuration of territory in the base.Above-mentioned 2nd extrinsic region has the 1st conductivity type.Above-mentioned 2nd extrinsic region configuration is above-mentioned The skin section of drift layer, discretely configures with above-mentioned base.Above-mentioned 1st groove is along the direction parallel with the surface of above-mentioned drift layer It is extended.Above-mentioned 1st groove is configured to the assigned position of the midway of above-mentioned base from above-mentioned 1st extrinsic region.Above-mentioned 2nd ditch Groove is extended along the direction parallel with the surface of above-mentioned drift layer.Above-mentioned 2nd groove is above-mentioned from above-mentioned 1st extrinsic region insertion Base reaches above-mentioned drift layer.The portion of side positioned at above-mentioned 2nd groove of the above-mentioned thyristor in above-mentioned base Divide and form raceway groove.Above-mentioned thyristor is along the horizontal type that flows transversely through electric current parallel with the surface of above-mentioned drift layer MOSFET。
Instead scheme, above-mentioned base can be only fitted to the skin section of above-mentioned drift layer.The impurity range of said elements side the 1st Skin section of the configuration of territory in the base.Above-mentioned 2nd extrinsic region has the 2nd conductive area.Above-mentioned 2nd extrinsic region configuration exists The skin section of above-mentioned drift layer, discretely configures with above-mentioned base.Above-mentioned 1st groove is along parallel with the surface of above-mentioned drift layer Direction is extended.Above-mentioned 1st groove is configured to the assigned position of the midway of above-mentioned base from above-mentioned 1st extrinsic region.It is above-mentioned 2nd groove is extended along the direction parallel with the surface of above-mentioned drift layer.Above-mentioned 2nd groove is passed through from above-mentioned 1st extrinsic region Lead to above-mentioned base and reach above-mentioned drift layer.Above-mentioned thyristor in above-mentioned base positioned at above-mentioned 2nd groove The part of side forms raceway groove.Above-mentioned thyristor is to flow transversely through electric current along parallel with the surface of above-mentioned drift layer Traverse type IGBT.
Instead scheme, above-mentioned 2nd extrinsic region can be the Semiconductor substrate of the 1st conductivity type.Above-mentioned drift layer is matched somebody with somebody Put in above-mentioned Semiconductor substrate.In above-mentioned base between the extrinsic region of said elements side the 1st and above-mentioned drift layer Part surface on, be configured with above-mentioned 1st gate electrode and the 2nd gate electrode across above-mentioned gate insulating film.It is above-mentioned partly to lead Body switch element, on the surface of the above-mentioned base opposed with above-mentioned 2nd gate electrode, along the plane side with above-mentioned Semiconductor substrate Raceway groove is transversely formed to parallel.Above-mentioned thyristor is to flow through electric current along the vertical direction of above-mentioned Semiconductor substrate The longitudinal type MOSFET of plane.
Instead scheme, above-mentioned 2nd extrinsic region can be the Semiconductor substrate containing the 2nd conductivity type part.It is above-mentioned Drift layer is configured in above-mentioned Semiconductor substrate.In above-mentioned base positioned at above-mentioned 1st extrinsic region and above-mentioned drift layer it Between part surface on, be configured with above-mentioned 1st gate electrode and above-mentioned 2nd gate electrode across above-mentioned gate insulating film.On State thyristor, on the surface of the above-mentioned base opposed with above-mentioned 2nd gate electrode, along and above-mentioned Semiconductor substrate In-plane it is parallel be transversely formed raceway groove.Above-mentioned thyristor is flowed through along the vertical direction of above-mentioned Semiconductor substrate The longitudinal type IGBT of the plane of electric current.
As an alternative, above-mentioned base can be only fitted to the skin section of above-mentioned drift layer.The impurity range of said elements side the 1st Skin section of the configuration of territory in the base.Above-mentioned 2nd extrinsic region has the 1st conductivity type.Above-mentioned 2nd extrinsic region configuration is above-mentioned The skin section of drift layer is discretely configured with above-mentioned base.In above-mentioned base positioned at above-mentioned 1st extrinsic region and above-mentioned drift On the surface of the different piece moved between layer, above-mentioned 1st gate electrode and above-mentioned 2nd grid are configured with across above-mentioned gate insulating film Pole electrode.Above-mentioned thyristor, on the surface of the above-mentioned base opposed with above-mentioned 2nd gate electrode, along and above-mentioned drift Move layer surface it is parallel be transversely formed raceway groove.Above-mentioned thyristor is along the horizontal stroke parallel with the surface of above-mentioned drift layer To the horizontal type MOSFET of the plane for flowing through electric current.
Instead scheme, skin section of the above-mentioned base configuration in above-mentioned drift layer.Above-mentioned 1st extrinsic region configuration is at this The skin section of base.Above-mentioned 2nd extrinsic region has the 2nd conductive area.Above-mentioned 2nd extrinsic region configuration is in above-mentioned drift layer Skin section, discretely configured with above-mentioned base.In above-mentioned base positioned at above-mentioned 1st extrinsic region and above-mentioned drift layer it Between part surface on different positions, be configured with above-mentioned 1st gate electrode and the above-mentioned 2nd across above-mentioned gate insulating film Gate electrode.Above-mentioned thyristor, on the surface of the above-mentioned base opposed with above-mentioned 2nd gate electrode, along with it is above-mentioned The surface of drift layer it is parallel be transversely formed raceway groove.Above-mentioned thyristor is along parallel with the surface of above-mentioned drift layer Flow transversely through the traverse type IGBT of the plane of electric current.
Instead scheme, semiconductor device can also have the groove of depth identical the 1st and the 2nd groove.Above-mentioned 2nd is miscellaneous Matter region is the Semiconductor substrate of the 1st conductivity type.Above-mentioned drift layer configuration is in above-mentioned Semiconductor substrate.Above-mentioned 1st groove and 2nd groove reaches above-mentioned drift layer from the above-mentioned base of extrinsic region insertion of said elements side the 1st respectively.Said elements side grid electricity Has the 2nd gate electrode.In the 1st groove, the 2nd gate electrode is configured with the 1st groove not for above-mentioned 1st gate electrode configuration In the 2nd same groove.The part of side positioned at above-mentioned 2nd groove of the above-mentioned thyristor in above-mentioned base is formed Raceway groove.Above-mentioned thyristor is the longitudinal type MOSFET that electric current is flowed through along the vertical direction of above-mentioned Semiconductor substrate.Configuration Above-mentioned gate insulating film in above-mentioned 1st groove has the part 1 and the 2nd more shallow than centre position than centre position depth Point.Centre position is deeper and more shallow than the top of above-mentioned drift layer than the top of above-mentioned base.Above-mentioned part 1 is than above-mentioned 2nd Divide thickness thick.
Instead scheme, semiconductor device can also have the groove of depth identical the 1st and the 2nd groove.Above-mentioned 2nd is miscellaneous Matter region is the Semiconductor substrate of the 1st conductivity type.Above-mentioned drift layer configuration is in above-mentioned Semiconductor substrate.1st groove and the 2nd ditch Groove reaches above-mentioned drift layer from the above-mentioned base of extrinsic region insertion of said elements side the 1st respectively.Said elements side gate electrode tool There is the 2nd gate electrode.In the 1st groove, the 2nd gate electrode is configured different from the 1st groove for above-mentioned 1st gate electrode configuration In 2nd groove.The part of side positioned at above-mentioned 2nd groove of the above-mentioned thyristor in above-mentioned base forms ditch Road.Above-mentioned thyristor is the longitudinal type MOSFET that electric current is flowed through along the vertical direction of above-mentioned Semiconductor substrate.Positioned at upper Stating the above-mentioned base of the side of the 1st groove has 1st region and than centre position deeper 2nd region more shallow than centre position.In Between position it is deeper than the top of above-mentioned base and more shallow than the top of above-mentioned drift layer.Above-mentioned 2nd region is more miscellaneous than above-mentioned 1st region Matter concentration is high.
Instead scheme, or, the configuration of above-mentioned fly-wheel diode in the 1st chip, above-mentioned semiconductor switch unit Part is configured in 2nd chip different from the 1st chip.
Instead scheme, or, above-mentioned 1st gate electrode is across above-mentioned gate insulating film from above-mentioned diode side 1st extrinsic region is configured to the assigned position of the midway of above-mentioned 2nd conductive area.
Instead scheme, said elements side gate electrode can have the 2nd gate electrode and the 3rd gate electrode.It is above-mentioned 2nd gate electrode is configured to the rule of the midway of above-mentioned base across above-mentioned gate insulating film from the extrinsic region of said elements side the 1st Positioning is put.3rd gate electrode is configured to above-mentioned drift layer across above-mentioned gate insulating film from the extrinsic region of said elements side the 1st The assigned position of midway.When grid voltage is applied into said elements side gate electrode, above-mentioned 3rd gate electrode is used as partly leading Body switch element drives and uses grid function.Thyristor driving grid is formed above-mentioned in above-mentioned base The raceway groove that 1 extrinsic region is connected with above-mentioned drift layer.
Instead scheme, above-mentioned 1st chip can also have the 1st groove.1st groove is miscellaneous from above-mentioned diode side the 1st Matter region reaches above-mentioned 2nd conductive layer.Above-mentioned 1st gate electrode configuration is in the 1st groove.Above-mentioned 2nd chip can also have There are the 2nd groove and the 3rd groove.2nd groove reaches above-mentioned base from the extrinsic region of said elements side the 1st.3rd groove is from above-mentioned unit The above-mentioned base of extrinsic region insertion of part side the 1st reaches above-mentioned drift layer.2nd gate electrode is configured in the 2nd groove, the 3rd grid Electrode configuration is in the 3rd groove, there is provided trench gate is constructed.There is above-mentioned thyristor trench gate to construct.
Instead scheme, above-mentioned 2nd extrinsic region can be the Semiconductor substrate of the 1st conductivity type.Above-mentioned drift layer is matched somebody with somebody Put in above-mentioned Semiconductor substrate.Above-mentioned 1st groove is configured to above-mentioned 2nd conductivity type from the extrinsic region of above-mentioned diode side the 1st The assigned position of the midway of layer.Above-mentioned 2nd groove is configured to the rule of the midway of above-mentioned base from the extrinsic region of said elements side the 1st Positioning is put.Above-mentioned 3rd groove reaches above-mentioned drift layer from the above-mentioned above-mentioned base of 1st extrinsic region insertion.Above-mentioned semiconductor switch The part of side positioned at above-mentioned 3rd groove of the element in above-mentioned base forms raceway groove.Above-mentioned thyristor is edge The vertical direction of above-mentioned Semiconductor substrate flows through the longitudinal type MOSFET of electric current.
Instead scheme, above-mentioned 2nd extrinsic region can be the Semiconductor substrate containing the 2nd conductivity type part.It is above-mentioned Drift layer is configured in above-mentioned Semiconductor substrate.Above-mentioned 2nd groove is configured to above-mentioned base from the extrinsic region of said elements side the 1st Midway assigned position.Above-mentioned 3rd groove reaches above-mentioned drift from the above-mentioned base of extrinsic region insertion of said elements side the 1st Layer.The part of side positioned at above-mentioned 3rd groove of the above-mentioned thyristor in above-mentioned base forms raceway groove.Above-mentioned half Conductor switch element is the longitudinal type IGBT that electric current is flowed through along the vertical direction of above-mentioned Semiconductor substrate.
Instead scheme, above-mentioned base can be only fitted to the skin section of above-mentioned drift layer.The impurity range of said elements side the 1st Skin section of the configuration of territory in the base.Above-mentioned 2nd extrinsic region has the 1st conductivity type.Above-mentioned 2nd extrinsic region configuration is above-mentioned The skin section of drift layer, discretely configures with above-mentioned base.Above-mentioned 2nd groove is along the direction parallel with the surface of above-mentioned drift layer It is extended, the assigned position of the midway of above-mentioned base is configured to from the extrinsic region of said elements side the 1st.Above-mentioned 3rd groove edge The direction parallel with the surface of above-mentioned drift layer is extended, and is reached from the above-mentioned base of extrinsic region insertion of said elements side the 1st Above-mentioned drift layer.The part of side positioned at above-mentioned 3rd groove of the above-mentioned thyristor in above-mentioned base forms ditch Road.Above-mentioned thyristor is along the horizontal type MOSFET that flows transversely through electric current parallel with the surface of above-mentioned drift layer.
Instead scheme, above-mentioned base can be only fitted to the skin section of above-mentioned drift layer.The impurity range of said elements side the 1st Skin section of the configuration of territory in the base.Above-mentioned 2nd extrinsic region has the 2nd conductivity type part.Above-mentioned 2nd extrinsic region configuration exists The skin section of above-mentioned drift layer, discretely configures with above-mentioned base.Above-mentioned 2nd groove is along parallel with the surface of above-mentioned drift layer Direction is extended, and the assigned position of the midway of above-mentioned base is configured to from the extrinsic region of said elements side the 1st.Above-mentioned 3rd ditch Groove is extended along the direction parallel with the surface of above-mentioned drift layer, from the above-mentioned base of extrinsic region insertion of said elements side the 1st Reach above-mentioned drift layer.The part shape of side positioned at above-mentioned 3rd groove of the above-mentioned thyristor in above-mentioned base Into raceway groove.Above-mentioned thyristor is along the traverse type IGBT that flows transversely through electric current parallel with the surface of above-mentioned drift layer.
Instead scheme, above-mentioned 2nd extrinsic region can be the Semiconductor substrate of the 1st conductivity type.Above-mentioned drift layer is matched somebody with somebody Put in above-mentioned Semiconductor substrate.In above-mentioned base between the extrinsic region of said elements side the 1st and above-mentioned drift layer Part surface on, be configured with above-mentioned 2nd gate electrode and the 3rd gate electrode across above-mentioned gate insulating film.It is above-mentioned partly to lead Body switch element on the surface of the above-mentioned base opposed with above-mentioned 3rd gate electrode, along the plane side with above-mentioned Semiconductor substrate Raceway groove is transversely formed to parallel.Above-mentioned thyristor is to flow through electric current along the vertical direction of above-mentioned Semiconductor substrate The longitudinal type MOSFET of plane.
Instead scheme, above-mentioned 2nd extrinsic region can be the Semiconductor substrate containing the 2nd conductivity type part.It is above-mentioned Drift layer is configured in above-mentioned Semiconductor substrate.In above-mentioned base positioned at the extrinsic region of said elements side the 1st and above-mentioned drift On the surface of the part moved between layer, above-mentioned 2nd gate electrode and the 3rd gate electrode are configured with across above-mentioned gate insulating film. Above-mentioned thyristor, on the surface of the above-mentioned base opposed with above-mentioned 3rd gate electrode, along and above-mentioned Semiconductor substrate In-plane it is parallel be transversely formed raceway groove.Above-mentioned thyristor is along the vertical direction stream of above-mentioned Semiconductor substrate The longitudinal type IGBT of the plane of overcurrent.
Instead scheme, above-mentioned base can be only fitted to the skin section of above-mentioned drift layer.The impurity range of said elements side the 1st Skin section of the configuration of territory in the base.Above-mentioned 2nd extrinsic region has the 1st conductivity type.Above-mentioned 2nd extrinsic region configuration is above-mentioned The skin section of drift layer, discretely configures with above-mentioned base.In above-mentioned base positioned at the extrinsic region of said elements side the 1st with Diverse location on the surface of the part between above-mentioned drift layer, above-mentioned 2nd grid electricity is configured with across above-mentioned gate insulating film Pole and above-mentioned 3rd gate electrode.Above-mentioned thyristor, in the table of the above-mentioned base opposed with above-mentioned 3rd gate electrode Face, raceway groove is transversely formed along parallel with the surface of above-mentioned drift layer.Above-mentioned thyristor is edge and above-mentioned drift layer The parallel plane for flowing transversely through electric current in surface horizontal type MOSFET.
Instead scheme, above-mentioned base can be only fitted to the skin section of above-mentioned drift layer.The impurity range of said elements side the 1st Skin section of the configuration of territory in the base.Above-mentioned 2nd extrinsic region has the 2nd conductive area.Above-mentioned 2nd extrinsic region configuration exists The skin section of above-mentioned drift layer, discretely configures with above-mentioned base.In above-mentioned base positioned at the impurity range of said elements side the 1st Diverse location on the surface of the part between domain and above-mentioned drift layer, above-mentioned 2nd grid are configured with across above-mentioned gate insulating film Pole electrode and above-mentioned 3rd gate electrode.Above-mentioned thyristor, in the above-mentioned base opposed with above-mentioned 3rd gate electrode Surface, be transversely formed raceway groove along parallel with the surface of above-mentioned drift layer.Above-mentioned thyristor is edge and above-mentioned drift Move the traverse type IGBT of the parallel plane for flowing transversely through electric current in surface of layer.
Instead scheme, above-mentioned 1st chip can also have the 1st groove.1st groove is miscellaneous from above-mentioned diode side the 1st Insertion above-mentioned 2nd conductive layer in matter region reaches above-mentioned 1st conductive layer.Above-mentioned 1st gate electrode configuration is in above-mentioned 1st groove It is interior.Configuring above-mentioned gate insulating film in above-mentioned 1st groove has the part 1 deeper than centre position and more shallow than centre position Part 2.Centre position is deeper and more shallow than the top of above-mentioned 1st conductive layer than the top of above-mentioned 2nd conductive layer.On State part 1 thicker than above-mentioned part 2 thickness.
Instead scheme, above-mentioned 1st chip can also have the 1st groove.1st groove is miscellaneous from above-mentioned diode side the 1st Insertion above-mentioned 2nd conductive layer in matter region reaches above-mentioned 1st conductive layer.Above-mentioned 1st gate electrode configuration is in above-mentioned 1st groove It is interior.Above-mentioned 2nd conductive layer positioned at the side of above-mentioned 1st groove has 1st region more shallow than centre position and compares interposition Put the 2nd deep region.Centre position is deeper and more shallow than the top of above-mentioned 1st conductive layer than the top of the 2nd conductive layer. Above-mentioned 2nd region is higher than above-mentioned 1st region impurity concentration.
Instead scheme, said elements side gate electrode can have the 2nd gate electrode.2nd gate electrode is across upper State gate insulating film and be configured to above-mentioned drift layer from the assigned position of the midway of above-mentioned base.Above-mentioned 1st gate electrode and above-mentioned 2nd gate electrode is made up of the material of different work functions.Difference based on work function, the grid applied to above-mentioned 1st gate electrode Voltage may be applied to above-mentioned 2nd gate electrode.
According to the second technical scheme of the disclosure, in the control method of the semiconductor device described in above-mentioned first technical scheme In, from making above-mentioned fly-wheel diode carry out the state of diode action to cutting the state of above-mentioned thyristor conducting Change；In above-mentioned switching, before above-mentioned thyristor is turned on, grid voltage is applied to above-mentioned 1st gate electrode, The part opposed with above-mentioned 1st gate electrode across above-mentioned gate insulating film in above-mentioned 2nd conductive layer forms inversion layer.
The control method of above-mentioned semiconductor device, from making FWD carry out the timing of diode action to making semiconductor switch During the exchange-column shift of element conductive, can suppress to inject the superfluous load that excess carriers and reducing are present in the 2nd conductive layer Stream, can reduce recovery loss.Further, since forming inversion layer, right by only applying grid voltage to the 1st gate electrode 2nd gate electrode does not apply any voltage so as to realize recovering the reduction of loss, even if so applying to the 2nd gate electrode The grid voltage come by interference fringe, is not easy to exceed the threshold value for turning on thyristor.Thus, it is possible to make be difficult hair The raw semiconductor device from the construction opened come by interference fringe.
According to the 3rd technical scheme of the disclosure, semiconductor device possesses：1st conductive-type semiconductor layer；1st conductivity type Drift layer, configures on above-mentioned 1st conductive-type semiconductor layer, lower than above-mentioned 1st conductive-type semiconductor layer impurity concentration；2nd The base of conductivity type, forms on the contrary on above-mentioned drift layer and with above-mentioned 1st conductive-type semiconductor layer；1st conductivity type Extrinsic region, is formed on above-mentioned base, higher than above-mentioned drift layer concentration；2nd conductive-type impurity layer, is formed in than above-mentioned base The position of Qu Shen, with base contact；Groove, forms from the surface of above-mentioned base, and groove is extended along its length, and above-mentioned 1 conductive type impurity region and the configuration of above-mentioned base are in the both sides of groove；Gate insulating film, is formed in the surface of above-mentioned groove；Grid Pole electrode, in above-mentioned groove, is formed by above-mentioned gate insulating film；Surface electrode, with above-mentioned 1st conductive type impurity region and Above-mentioned base electrical connection；Backplate, be formed in above-mentioned 1st conductive-type semiconductor layer as with above-mentioned drift layer opposition side Face rear side.When to above-mentioned gate electrode applied voltage, on the surface positioned at side, the above-mentioned base of above-mentioned groove Portion forms inversion layer.Via above-mentioned 1st conductive type impurity region, inversion layer and above-mentioned drift layer, above-mentioned surface electrode and on State and flow through electric current between backplate, there is provided the vertical semiconductor switch element of transoid.Above-mentioned base and above-mentioned drift layer it Between PN junction is provided, there is provided carry out the fly-wheel diode of diode action.Thyristor and fly-wheel diode configuration are at 1 In chip.Groove has the 1st groove and the 2nd groove.1st groove is than above-mentioned base depth and reaches above-mentioned drift layer.2nd groove Above-mentioned 2nd conductive-type impurity layer is reached with the 1st groove identical depth, and than the bottom of above-mentioned 2nd conductive-type impurity layer It is shallow.Above-mentioned gate electrode has the driving for being used for driving above-mentioned vertical semiconductor switch element with gate electrode and in shape The diode gate electrode of inversion layer is formed in above-mentioned base into the position for having above-mentioned fly-wheel diode.Drive with grid electricity Pole is configured in the 1st groove.Diode gate electrode is configured at the 2nd groove.
In above-mentioned semiconductor device, formed using the 1st of same depth the, the 2nd groove and be used for driving vertical semiconductor to open Close the driving gate electrode and the diode gate electrode for forming inversion layer in FWD sides of element.Also, on two poles Effective gate electrode, is formed on the region of the 2nd conductive-type impurity layer, and made the of configuration diode gate electrode 2 grooves are not up to the construction of drift layer.If using the semiconductor device of such construction, under making the injection efficiency of carrier Drop.Thus, even if not needing the trench-gate of different depth, it is also possible to while realizing the reduction of return loss and recovering loss Reduce.
Instead scheme, above-mentioned 2nd conductive-type impurity layer can be formed in the 2nd conductivity type of the bottom of above-mentioned base Body layer.
Instead scheme, the length direction of above-mentioned driving gate electrode can be with above-mentioned diode gate electrode Length direction is parallel.Above-mentioned driving gate electrode and above-mentioned diode gate electrode are configured to the formation ratio with regulation Strip.Formation ratio on the driving gate electrode 8a in the case of this and diode gate electrode 8b can be arbitrarily Setting.
Instead scheme, semiconductor device can also have：Driving gate wirings, with above-mentioned driving gate electrode Connection；Diode gate wirings, are connected with above-mentioned diode with gate electrode.Above-mentioned driving gate wirings are by from above-mentioned drive Draw the one end for employing the above-mentioned length direction in gate electrode.Above-mentioned diode gate wirings are by from above-mentioned diode grid The other end of the above-mentioned length direction in the electrode of pole is drawn.If so, then possessing vertical semiconductor switch element, FWD The periphery of unit area, can not make and driving gate wirings 10a overlaps with diode gate wirings 10b both sides Layout, can easily carry out distribution layout.
Instead scheme, Ke Yishi during with to above-mentioned driving with gate electrode applied voltage, forms the situation of inversion layer Under threshold value compare, during to above-mentioned diode with gate electrode applied voltage, formed inversion layer in the case of threshold value it is lower.Such as Fruit so, then easily can form more inversion layer, it is possible to easily using the vicinity of diode gate electrode Carry out carrier extraction.Additionally, on for the gate driving circuit side to each gate electrode applied voltage, also due to can subtract The small applied voltage to diode gate electrode and can reduce circuit burden.
Instead scheme, above-mentioned vertical semiconductor switch element can be longitudinal type MOSFET.Above-mentioned 1st conductive-type impurity Region is source region.Above-mentioned surface electrode is source electrode.Above-mentioned backplate is drain electrode.
Instead scheme, semiconductor device can also have the 2nd conductive-type semiconductor layer, configure in above-mentioned drift layer Simultaneously.One side of the above-mentioned 1st conductive-type semiconductor layer configuration in above-mentioned drift layer.Above-mentioned vertical semiconductor switch element is longitudinal type IGBT.Above-mentioned 1st conductive type impurity region is emitter region.Above-mentioned 1st conductive-type semiconductor layer is cathode zone.Above-mentioned 2 conductive-type semiconductor layers are collector regions.Above-mentioned surface electrode is emitter electrode.Above-mentioned backplate is colelctor electrode electricity Pole.
According to the 4th technical scheme of the disclosure, the semiconductor device of above-mentioned 3rd technical scheme is being connected in series two It is individual and connect the control method of device obtained from inductive load at two contact points of above-mentioned semiconductor device, will The above-mentioned vertical semiconductor switch element possessed in the above-mentioned semiconductor device of upside is configured at is switched to from cut-off state leads Logical state, and the above-mentioned fly-wheel diode that will possess in the above-mentioned semiconductor device of downside is configured at is from turn-on action state Switch to blocking action state；The above-mentioned vertical semiconductor switch element possessed in the above-mentioned semiconductor device by above-mentioned upside Before switching to conducting state from cut-off state, the above-mentioned diode to possessing in the above-mentioned semiconductor device of above-mentioned downside is used Gate electrode applies grid voltage, is pointed to configure upper at the side of above-mentioned 2nd groove of above-mentioned diode gate electrode State base and form inversion layer.
According to the control method of such device, decline the injection efficiency of carrier.Thus, even if not needing different depths The trench-gate of degree, it is also possible to while realizing the reduction of return loss and recovering the reduction of loss.
The present invention is that with reference to being described, but the present invention is interpreted as being not limited to the implementation with preferred embodiment Example and construction.The present invention also includes the deformation in various modifications example and equivalency range.Also, it is understood that appropriate various groups Conjunction and form or other combinations in them only including a kind of key element, including more or less key element or form are also included In scope of the invention or technical scope.

Claims (10)

1. a kind of semiconductor device, it is characterised in that
Thyristor and fly-wheel diode with insulated gate construction；
Thyristor is made up of following part：
The drift layer (2,50) of the 1st conductivity type；
The base (3,51) of the 2nd conductivity type, configures on the drift layer (2,50) of above-mentioned 1st conductivity type；
The extrinsic region of the component side the 1st (4,52) of the 1st conductivity type, configures the skin section in above-mentioned base (3,51), across the base Area (3,51) and discretely configured with above-mentioned drift layer (2,50), it is and higher than above-mentioned drift layer (2,50) impurity concentration；
Component side gate electrode (8,56), is configured at across gate insulating film (7,55) and is clipped in above-mentioned 1st extrinsic region (4,52) With the above-mentioned base (3,51) between above-mentioned drift layer (2,50)；
2nd extrinsic region (1,57) of the 1st conductivity type or the 2nd conductivity type, contacts, than the drift layer with above-mentioned drift layer (2,50) (2,50) impurity concentration is high, is discretely configured with above-mentioned base (3,51)；
The electrode of component side the 1st (9,58), electrically connects with the extrinsic region of said elements side the 1st (4,52) and above-mentioned base (3,51)； And
The electrode of component side the 2nd (10,59), electrically connects with above-mentioned 2nd extrinsic region (1,57)；
Thyristor, it is in above-mentioned base (3,51), positioned at across above-mentioned gate insulating film (7,55) and with it is above-mentioned The raceway groove of transoid is formed in the part of component side gate electrode (8,56) opposite side；
Thyristor, by the raceway groove in the electrode of said elements side the 1st (9,58) and the electrode of said elements side the 2nd Electric current is flowed through between (10,59)；
Fly-wheel diode is made up of following part：
1st conductive layer (2,50,60)；
2nd conductive layer (3,51,61), configures on above-mentioned 1st conductive layer (2,50,60)；
The electrode of diode side the 1st (9,58,62), is connected to above-mentioned 2nd conductive layer (3,51,61) side；And
The electrode of diode side the 2nd (10,59,63), is connected to above-mentioned 1st conductive layer (2,50,60) side；
Fly-wheel diode provides what is formed by above-mentioned 1st conductive layer (2,50,60) and above-mentioned 2nd conductive layer (3,51,61) PN junction；
Fly-wheel diode, in the electrode of above-mentioned diode side the 1st (9,58,62) and the electrode of above-mentioned diode side the 2nd (10,59,63) Between flow through electric current；
Above-mentioned thyristor is connected in parallel with above-mentioned fly-wheel diode；
Above-mentioned fly-wheel diode also has：
The extrinsic region of the diode side the 1st (4,52,64) of the 1st conductivity type, configures in above-mentioned 2nd conductive layer (3,51,61) Skin section is higher than above-mentioned 1st conductive layer (2,50,60) impurity concentration；And
Diode side gate electrode (8,56,67), is configured at across gate insulating film (7,55,66) and is clipped in the 1st extrinsic region Above-mentioned 2nd conductive layer (3,51,61) between (4,52,64) and above-mentioned 1st conductive layer (2,50,60)；
Above-mentioned diode side gate electrode (8,56,67) is with the 1st gate electrode (8a, 8c, 8e, 8g, 56a, 56c, 67)；
1st gate electrode (8a, 8c, 8e, 8g, 56a, 56c, 67) provides excess carriers injection suppressor grid；
When to the diode side gate electrode (8,56,67) apply grid voltage when, the 1st gate electrode (8a, 8c, 8e, 8g, 56a, 56c, 67) in a part for above-mentioned 2nd conductive layer (3,51,61) form raceway groove；
Above-mentioned 2nd conductive layer (3,51,61) a part configuration exist, the extrinsic region of above-mentioned diode side the 1st (4,52,64) with From the extrinsic region of above-mentioned diode side the 1st (4,52,64) towards the predetermined bits of the midway of above-mentioned 1st conductive layer (2,50,60) Between putting；
Above-mentioned thyristor and the configuration of above-mentioned fly-wheel diode are in 1 chip；
Above-mentioned drift layer (2,50) is above-mentioned 1st conductive layer (2,50,60)；
Above-mentioned base (3,51) is above-mentioned 2nd conductive layer (3,51,61)；
The electrode of component side the 1st (9,58) is the electrode of diode side the 1st (9,58,62)；
The electrode of component side the 2nd (10,59) is the electrode of diode side the 2nd (10,59,63)；
The extrinsic region of component side the 1st (4,52) is the extrinsic region of diode side the 1st (4,52,64)；
Component side gate electrode (8,56) is diode side gate electrode (8,56,67)；
Above-mentioned 1st gate electrode (8a, 8c, 56a, 56c) is across above-mentioned gate insulating film (7,55) from the impurity of said elements side the 1st Region (4,52) is configured to the assigned position of the midway of above-mentioned base (3,51)；
Said elements side gate electrode (8,56) is with the 2nd gate electrode (8d, 56d)；
Above-mentioned 1st gate electrode (8c, 56c) separates with the 2nd gate electrode (8d, 56d)；
Above-mentioned 2nd gate electrode (8d, 56d) is matched somebody with somebody across above-mentioned gate insulating film (7,55) from above-mentioned 1st extrinsic region (4,52) Put above-mentioned drift layer (2,50)；
When grid voltage is applied into said elements side gate electrode (8,56), the conduct of above-mentioned 2nd gate electrode (8d, 56d) Thyristor drives and uses grid function；
Thyristor driving grid to above-mentioned base (3,51) formed by above-mentioned 1st extrinsic region (4,52) with it is above-mentioned The raceway groove of drift layer (2,50) connection,
The semiconductor device also has：
1st groove (6,54), above-mentioned base (3,51) is reached from the extrinsic region of said elements side the 1st (4,52)；And
2nd groove (6,54), above-mentioned drift is reached from said elements side the 1st extrinsic region (4,52) the above-mentioned base of insertion (3,51) Layer (2,50)；
In above-mentioned 1st groove (6,54), the 2nd gate electrode (8d, 56d) is configured for above-mentioned 1st gate electrode (8c, 56c) configuration In 2nd groove (6,54) different from the 1st groove (6,54), there is provided trench gate is constructed；
There is above-mentioned thyristor trench gate to construct,
Above-mentioned 1st groove (6) is configured to the assigned position of the midway of above-mentioned base (3) from above-mentioned 1st extrinsic region (4),
Above-mentioned 2nd groove (6) reaches above-mentioned drift layer (2) from the above-mentioned base of above-mentioned 1st extrinsic region (4) insertion (3),
Above-mentioned 1st gate electrode and above-mentioned 2nd gate electrode, can be independent by independent grid wiring and external electrical connections The voltage that ground control is applied in respectively.
2. semiconductor device as claimed in claim 1, it is characterised in that
Above-mentioned 2nd extrinsic region is the Semiconductor substrate (1) of the 1st conductivity type；
Above-mentioned drift layer (2) configuration is in above-mentioned Semiconductor substrate (1)；
Above-mentioned thyristor forms ditch in above-mentioned base (3) in the part of above-mentioned 2nd groove (6) side Road；
Above-mentioned thyristor is the longitudinal type MOSFET that electric current is flowed through along the vertical direction of above-mentioned Semiconductor substrate (1).
3. semiconductor device as claimed in claim 1, it is characterised in that
Above-mentioned 2nd extrinsic region (1) is the Semiconductor substrate (1) containing the 2nd conductivity type part (1b)；
Above-mentioned drift layer (2) configuration is in above-mentioned Semiconductor substrate (1)；
Above-mentioned thyristor forms ditch in above-mentioned base (3) in the part of above-mentioned 2nd groove (6) side Road；
Above-mentioned thyristor is the longitudinal type IGBT that electric current is flowed through along the vertical direction of above-mentioned Semiconductor substrate (1).
4. semiconductor device as claimed in claim 1, it is characterised in that
Skin section of above-mentioned base (51) configuration in above-mentioned drift layer (50)；
Skin section of extrinsic region (52) configuration of said elements side the 1st in the base (51)；
Above-mentioned 2nd extrinsic region (57) is with the 1st conductivity type；
Above-mentioned 2nd extrinsic region (57) configuration is discretely configured in the skin section of above-mentioned drift layer (50) with above-mentioned base (51)；
Above-mentioned 1st groove (54) is extended along the direction parallel with the surface of above-mentioned drift layer (50)；
Above-mentioned 1st groove (54) is configured to the assigned position of the midway of above-mentioned base (51) from above-mentioned 1st extrinsic region (52)；
Above-mentioned 2nd groove (54) is extended along the direction parallel with the surface of above-mentioned drift layer (50)；
Above-mentioned 2nd groove (54) reaches above-mentioned drift layer (50) from the above-mentioned base of above-mentioned 1st extrinsic region (52) insertion (51)；
Above-mentioned thyristor forms ditch in above-mentioned base (51) in the part of above-mentioned 2nd groove (54) side Road；
Above-mentioned thyristor is along the horizontal type that flows transversely through electric current parallel with the surface of above-mentioned drift layer (50) MOSFET。
5. semiconductor device as claimed in claim 1, it is characterised in that
Skin section of above-mentioned base (51) configuration in above-mentioned drift layer (50)；
Skin section of extrinsic region (52) configuration of said elements side the 1st in the base (51)；
Above-mentioned 2nd extrinsic region (57) is with the 2nd conductive area (57b)；
Above-mentioned 2nd extrinsic region (57) configuration is discretely configured in the skin section of above-mentioned drift layer (50) with above-mentioned base (51)；
Above-mentioned 1st groove (54) is extended along the direction parallel with the surface of above-mentioned drift layer (50)；
Above-mentioned 1st groove (54) is configured to the assigned position of the midway of above-mentioned base (51) from above-mentioned 1st extrinsic region (52)；
Above-mentioned 2nd groove (54) is extended along the direction parallel with the surface of above-mentioned drift layer (50)；
Above-mentioned 2nd groove (54) reaches above-mentioned drift layer (50) from the above-mentioned base of above-mentioned 1st extrinsic region (52) insertion (51)；
Above-mentioned thyristor forms ditch in above-mentioned base (51) in the part of above-mentioned 2nd groove (54) side Road；
Above-mentioned thyristor is along the traverse type IGBT that flows transversely through electric current parallel with the surface of above-mentioned drift layer (50).
6. semiconductor device as claimed in claim 1, it is characterised in that
Above-mentioned 2nd extrinsic region (1) is the Semiconductor substrate (1) of the 1st conductivity type；
Above-mentioned drift layer (2) configuration is in above-mentioned Semiconductor substrate (1)；
The part between the extrinsic region (4) of said elements side the 1st and above-mentioned drift layer (2) in above-mentioned base (3) On surface, above-mentioned 1st gate electrode (8c) and the 2nd gate electrode (8d) are configured with across above-mentioned gate insulating film (7)；
Above-mentioned thyristor, on the surface of the above-mentioned base (3) opposed with above-mentioned 2nd gate electrode (8d), along with it is upper State Semiconductor substrate (1) in-plane it is parallel be transversely formed raceway groove；
Above-mentioned thyristor is the longitudinal type of the plane that electric current is flowed through along the vertical direction of above-mentioned Semiconductor substrate (1) MOSFET。
7. semiconductor device as claimed in claim 1, it is characterised in that
Above-mentioned 2nd extrinsic region (1) is the Semiconductor substrate (1) containing the 2nd conductivity type part (1b)；
Above-mentioned drift layer (2) configuration is in above-mentioned Semiconductor substrate (1)；
On the surface of the part between above-mentioned 1st extrinsic region (4) and above-mentioned drift layer (2) in above-mentioned base (3), Above-mentioned 1st gate electrode (8c) and above-mentioned 2nd gate electrode (8d) are configured with across above-mentioned gate insulating film (7)；
Above-mentioned thyristor, on the surface of the above-mentioned base (3) opposed with above-mentioned 2nd gate electrode (8d), along with it is upper State Semiconductor substrate (1) in-plane it is parallel be transversely formed raceway groove；
Above-mentioned thyristor is the longitudinal type of the plane that electric current is flowed through along the vertical direction of above-mentioned Semiconductor substrate (1) IGBT。
8. semiconductor device as claimed in claim 1, it is characterised in that
Skin section of above-mentioned base (51) configuration in above-mentioned drift layer (50)；
Skin section of extrinsic region (52) configuration of said elements side the 1st in the base (51)；
Above-mentioned 2nd extrinsic region (57) is with the 1st conductivity type；
Above-mentioned 2nd extrinsic region (57) configuration is discretely configured in the skin section of above-mentioned drift layer (50) with above-mentioned base (51)；
The different piece between above-mentioned 1st extrinsic region (52) and above-mentioned drift layer (50) in above-mentioned base (51) On surface, above-mentioned 1st gate electrode (56c) and above-mentioned 2nd gate electrode are configured with across above-mentioned gate insulating film (55) (56d)；
Above-mentioned thyristor, on the surface of the above-mentioned base (51) opposed with above-mentioned 2nd gate electrode (56d), along with The surface of above-mentioned drift layer (50) it is parallel be transversely formed raceway groove；
Above-mentioned thyristor is along the plane that flows transversely through electric current parallel with the surface of above-mentioned drift layer (50) Horizontal type MOSFET.
9. semiconductor device as claimed in claim 1, it is characterised in that
Skin section of above-mentioned base (51) configuration in above-mentioned drift layer (50)；
Skin section of above-mentioned 1st extrinsic region (52) configuration in the base (51)；
Above-mentioned 2nd extrinsic region (57) is with the 2nd conductive area (57b)；
Above-mentioned 2nd extrinsic region (57) configuration is discretely configured in the skin section of above-mentioned drift layer (50) with above-mentioned base (51)；
The surface of the part between above-mentioned 1st extrinsic region (52) and above-mentioned drift layer (50) in above-mentioned base (51) On different positions, be configured with above-mentioned 1st gate electrode (56c) and above-mentioned 2nd grid across above-mentioned gate insulating film (55) Electrode (56d)；
Above-mentioned thyristor, on the surface of the above-mentioned base (51) opposed with above-mentioned 2nd gate electrode (56d), along with The surface of above-mentioned drift layer (50) it is parallel be transversely formed raceway groove；
Above-mentioned thyristor is along the plane that flows transversely through electric current parallel with the surface of above-mentioned drift layer (50) Traverse type IGBT.
10. a kind of control method of semiconductor device, controls the semiconductor device any one of claim 1~9, and it is special Levy and be,
From making above-mentioned fly-wheel diode carry out the state of diode action to cutting the state of above-mentioned thyristor conducting Change；
In above-mentioned switching, before above-mentioned thyristor is turned on, to above-mentioned 1st gate electrode (8a, 8c, 8e, 8g, 56a, 56c, 67) apply grid voltage, in above-mentioned 2nd conductive layer (3,51,61) across above-mentioned gate insulating film (7,55,66) and form inversion layer in the part opposed with above-mentioned 1st gate electrode (8a, 8c, 8e, 8g, 56a, 56c, 67) (12)。
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