CN104157592A - Technology for increasing capacity of silicon-based heterojunction solar cells - Google Patents
Technology for increasing capacity of silicon-based heterojunction solar cells Download PDFInfo
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- CN104157592A CN104157592A CN201310172714.6A CN201310172714A CN104157592A CN 104157592 A CN104157592 A CN 104157592A CN 201310172714 A CN201310172714 A CN 201310172714A CN 104157592 A CN104157592 A CN 104157592A
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 199
- 239000010703 silicon Substances 0.000 title claims abstract description 199
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 198
- 238000000034 method Methods 0.000 claims abstract description 109
- 238000004519 manufacturing process Methods 0.000 claims abstract description 54
- 238000000151 deposition Methods 0.000 claims abstract description 44
- 239000000126 substance Substances 0.000 claims abstract description 33
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 16
- 230000008021 deposition Effects 0.000 claims abstract description 16
- 238000004140 cleaning Methods 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 162
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 131
- 239000012528 membrane Substances 0.000 claims description 38
- 239000007789 gas Substances 0.000 claims description 32
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 24
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 24
- 239000007792 gaseous phase Substances 0.000 claims description 24
- 238000002360 preparation method Methods 0.000 claims description 17
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 16
- 238000012545 processing Methods 0.000 claims description 15
- 230000005540 biological transmission Effects 0.000 claims description 13
- 229910052786 argon Inorganic materials 0.000 claims description 12
- 239000001257 hydrogen Substances 0.000 claims description 12
- 229910052739 hydrogen Inorganic materials 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 230000000630 rising effect Effects 0.000 claims description 7
- 239000010409 thin film Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 238000012546 transfer Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 239000013081 microcrystal Substances 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000004062 sedimentation Methods 0.000 claims description 3
- 238000000427 thin-film deposition Methods 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 2
- 238000010438 heat treatment Methods 0.000 abstract description 21
- 235000012431 wafers Nutrition 0.000 abstract 8
- 210000004027 cell Anatomy 0.000 description 32
- 150000002431 hydrogen Chemical class 0.000 description 9
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 238000013459 approach Methods 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004050 hot filament vapor deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
-
- H01L21/2053—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67103—Apparatus for thermal treatment mainly by conduction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67109—Apparatus for thermal treatment mainly by convection
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Photovoltaic Devices (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
The invention relates to a technology for increasing the capacity of silicon-based heterojunction solar cells. The technology comprises the steps that a production device, which comprises a wafer inlet chamber and a deposition chamber, of the silicon-based heterojunction solar cells is provided, and the deposition chamber is internally provided with a heater which implements heat treatment on silicon wafers; the surfaces of the silicon wafers are cleaned and dried in a wet chemical cleaning method; the silicon wafers are transmitted to the wafer inlet chamber, and vacuumizing is carried out; the silicon wafers are transmitted from the wafer inlet chamber to the deposition chamber, the internal of the deposition chamber includes a vacuum environment, and the preset temperature of the heater is greater than the technical temperature for preparing silicon-based films; and when the surface temperature of the silicon wafers is increased to the technical temperature of the silicon-based films due to heating, the silicon-based films are prepared in a chemical vapor deposition method in the deposition chamber. The technology can improve the equipment capacity and reduce the production cost while ensuring the quality of films.
Description
Technical field
The present invention relates to silicon based hetero-junction area of solar cell and field of semiconductor manufacture, relate in particular to a kind of technique that can increase silicon based hetero-junction solar cell production capacity.
Technical background
At present common prepare one side or two-sided silicon based hetero-junction solar cell all need to be on silicon chip depositing silicon system or carbon-based thin film, such as amorphous silicon membrane, microcrystalline silicon film, Nano thin film, silicon oxide film, carborundum films, silicon nitride film etc.These film preparation processes all comprise following two steps: first in a vacuum silicon chip is heated to technological temperature (130-350 DEG C), then under technological temperature condition, deposits very thin rete (2-20nm) at silicon chip surface.People adopt the heating process completing in two ways under this vacuum condition conventionally at present: a kind of mode is the direct heating in deposit cavity chamber, being set in advance as technological temperature by the temperature of heater heats, its advantage is without obvious cross pollution and without additional configuration heating in vacuum chamber again, can save like this equipment cost, but the process time of the method film forming is long, production capacity is not high; Another kind of mode is except deposit cavity, to increase by a preheating cavity again, first silicon chip is heated to approach technological temperature in preheating cavity, and then chip transmission is heated to deposit cavity, its advantage is that the process time of film forming is shorter, but improved equipment cost owing to increasing preheating cavity, and silicon chip often passes in and out the outer risk that can increase cross pollution of cavity body.
On the other hand, no matter be that one side or two-sided silicon based hetero-junction solar cell all need to deposit dissimilar amorphous silicon membrane on silicon chip surface, i.e. intrinsic amorphous silicon, P type amorphous silicon, N-type amorphous silicon.Due to the physical structure difference of all types of amorphous silicon membranes, therefore need to silicon chip be heated to different technological temperatures under vacuum environment and carry out film forming, to this, the method that people adopt is conventionally in different deposit cavities, to provide different process conditions to prepare required amorphous silicon membrane.This just makes the production equipment of amorphous silicon membrane must configure multiple deposit cavities, simultaneously more because of needs frequent transmission silicon chip between different deposit cavities, and causes the rising of cost and the increase of transmitting procedure die crack risk.
In current industrial actual production, people, in order to improve production capacity, can adopt the method that increases preheating cavity to heat mostly, in order further to reduce equipment cost and to save the transmission time, conventionally can and enter sheet chamber by preheating cavity and unite two into one simultaneously.But, often be exposed in atmosphere owing to entering sheet chamber, therefore heating can make to exist the materials such as some residual oxygen, steam and these materials easily to react at silicon chip surface in the time of high temperature in chamber herein, affects the passivation effect of heterojunction boundary, thereby has influence on the efficiency of solar cell.On the other hand, when entering sheet chamber and being connected with atmosphere, heat also can be constantly delivered in sheet chamber by outside, affects its temperature environment, causes heating environment unstable, affects the production yield of product and heater block is easily damaged.
Summary of the invention
In order to address the above problem, the invention provides a kind of technique that can increase silicon based hetero-junction solar cell production capacity, make silicon chip directly heating in deposit cavity, by the heter temperature in deposit cavity is set in advance as to the method higher than required deposit film technological temperature, realize ensureing to save the processing time of silicon chip in deposit cavity under the prerequisite that film-forming process is stable and film quality is good, reached the object that improves equipment capacity, reduces production costs.
For this reason, the invention provides a kind of technique that increases silicon based hetero-junction solar cell production capacity, this technique, for the preparation of the silica-base film in described silicon based hetero-junction solar cell, is characterized in that: this technique comprises the steps:
The first step, provides the production equipment of silicon based hetero-junction solar cell, and it comprises into sheet chamber and deposit cavity, is provided with the heater that silicon chip is heat-treated in described deposit cavity;
Second step, adopts wet-chemical cleaning mode that described silicon chip surface is cleaned and is dried;
The 3rd step, by described chip transmission to described in enter in sheet chamber, and vacuumize processing;
The 4th step, then by described silicon chip from described enter sheet chamber transfer to described deposit cavity, be vacuum environment in this deposit cavity, the temperature of described heater is set in advance as higher than the technological temperature of preparing described silica-base film;
The 5th step in the time that the surface temperature of described silicon chip is heated to the technological temperature of described silica-base film, utilizes chemical gaseous phase depositing process to prepare described silica-base film in described deposit cavity.
Alternatively, described silica-base film is the one in amorphous silicon, microcrystal silicon, carborundum, silicon nitride, silicon oxynitride, silica, polysilicon membrane, germanium-silicon film.
Alternatively, described amorphous silicon membrane is one or more in intrinsic amorphous silicon film, P type amorphous silicon membrane or N-type amorphous silicon membrane.
Alternatively, when described heter temperature is set in advance as while equaling described silica-base film technological temperature, the time that described silicon chip surface temperature is heated to described silica-base film technological temperature with the scope of utilizing chemical gaseous phase depositing process to prepare the ratio of the time of described silica-base film is: 4/1-12/1.
Alternatively, in the time period in the 5th step after described silicon chip is transferred in described deposit cavity and before carrying out chemical vapour deposition (CVD), in described deposit cavity, pass into a kind of gas or several gas in hydrogen, nitrogen, argon gas.
In addition, the present invention also provides a kind of technique that increases silicon based hetero-junction solar cell production capacity, this technique, for the preparation of intrinsic amorphous silicon film and doped amorphous silicon film in described silicon based hetero-junction solar cell, is characterized in that: this technique comprises the steps:
The first step, provides the production equipment of silicon based hetero-junction solar cell, and it comprises into sheet chamber and deposit cavity, is provided with the heater that silicon chip is heat-treated in described deposit cavity;
Second step, adopts wet-chemical cleaning mode that described silicon chip surface is cleaned and is dried;
The 3rd step, by described chip transmission to described in enter in sheet chamber, and vacuumize processing;
The 4th step, then by described silicon chip from described enter sheet chamber transfer to described deposit cavity, be vacuum environment in this deposit cavity, the temperature of described heater is set in advance as higher than the technological temperature of preparing described doped amorphous silicon film;
The 5th step in the time that the surface temperature of described silicon chip is heated to the technological temperature of described intrinsic amorphous silicon film, utilizes chemical gaseous phase depositing process to prepare described intrinsic amorphous silicon film in described deposit cavity;
The 6th step, completes after described intrinsic amorphous silicon thin film deposition, stops this chemical vapour deposition reaction, waits for that described silicon temperature continues to be increased to the technological temperature of described doped amorphous silicon film;
The 7th step, in the time that surface deposition has the silicon temperature of intrinsic amorphous silicon film to reach the technological temperature of described doped amorphous silicon film, in described deposit cavity, recycle chemical gaseous phase depositing process and continue the described doped amorphous silicon film of preparation on the surface of described intrinsic amorphous silicon film.
Alternatively, described doped amorphous silicon film is the one in P type amorphous silicon membrane or N-type amorphous silicon membrane.
Alternatively, the time that silicon chip surface temperature described in the 5th step is heated to described intrinsic amorphous silicon thin-film technique temperature is the time that in the 4/1-12/1, seven step, surface deposition has the silicon temperature of described intrinsic amorphous silicon film to be heated to technological temperature in described doped amorphous silicon film to be with the scope of utilizing chemical gaseous phase depositing process to prepare the ratio of the time of described doped amorphous silicon film with the scope of utilizing chemical gaseous phase depositing process to prepare the ratio of the time of described intrinsic amorphous silicon film: 4/1-12/1.
Alternatively, utilizing chemical gaseous phase depositing process to prepare in the sedimentation time of described silica-base film, described intrinsic amorphous silicon film, described doped amorphous silicon film, the rising scope of described silicon chip surface temperature is all less than 10 DEG C.
Alternatively, the technological temperature of described doped amorphous silicon film is than the high 200-100 DEG C of the technological temperature of described intrinsic amorphous silicon film.
Alternatively, in time period after described silicon chip is transferred in described deposit cavity and before described silicon chip surface temperature reaches the technological temperature of described intrinsic amorphous silicon film, pass into a kind of gas or several gas in the hydrogen, nitrogen, argon gas of good heat conductivity.
Alternatively, in the time period in the 5th step after described silicon chip is transferred in described deposit cavity and before carrying out chemical vapour deposition (CVD), to a kind of gas or several gas that pass in described deposit cavity in the hydrogen, nitrogen, argon gas of good heat conductivity.
Alternatively, in the 6th step waiting for that described silicon temperature continued to be increased in the time period of described doped amorphous silicon film technological temperature, to one or more the gas passing in described deposit cavity in hydrogen, nitrogen, argon gas.
Alternatively, described silicon chip is the one in n type single crystal silicon, p type single crystal silicon, N-type polysilicon, P type polysilicon.
Alternatively, described silica-base film, described intrinsic amorphous silicon film and described doped amorphous silicon film thickness range are 2-20nm.
Alternatively, described technique both can, for the preparation of lateral silicon base heterojunction solar cell, also can be prepared two-sided silicon based hetero-junction solar cell.
Alternatively, the production equipment of described silicon based hetero-junction solar cell is PECVD equipment, and described chemical gaseous phase depositing process is PECVD method.
Alternatively, described PECVD device power supply (DPS) is radio-frequency power supply, and its rf frequency scope is 13.56-100MHz.
Compared with the prior art, the present invention has following technique effect:
1) the present invention adopts silicon chip direct-fired method in deposit cavity, heat by the heter temperature in deposit cavity being set in advance as higher than the technological temperature of the required film of deposition, can avoid additional configuration heating in vacuum chamber more on the one hand, thereby save equipment cost; On the other hand, owing to having the temperature difference between heater and technological temperature, can make silicon chip within the shorter time, reach technological temperature, and owing to treating deposit film very thin thickness, only need the very short time to complete so deposit this film, at this moment, in section, silicon chip surface temperature rising difference will be less than 10 DEG C, substantially do not affect film-forming process and quality of forming film, therefore, technique provided by the invention can, ensureing to save the processing time of silicon chip in deposit cavity under the good prerequisite of film quality, improve the production capacity of equipment.
2) for the situation that need to deposit dissimilar film on same silicon chip, the present invention has adopted the method for preparing multiple film in same deposit cavity, by the temperature of heater being set in advance as higher than the high technology temperature in dissimilar film to be prepared, make all to have temperature difference between heater and various different process temperature, no matter thereby make silicon chip be heated to which kind of technological temperature, all can reach with speed faster, play and save the silicon chip processing time in deposit cavity, improve the object of equipment capacity, on the other hand, because the method does not need silicon chip frequent transmission between different deposit cavities, therefore also can reduce the cross pollution between cracked risk and vacuum environment and the atmosphere of transmitting procedure silicon chip.
3) in possibility, when silicon temperature in deposit cavity not yet reaches before technological temperature, in this deposit cavity, pass into the gas that heat-conductive characteristic is good, for example, one or more gases in hydrogen, nitrogen, argon gas, can accelerate the heat transmission in deposit cavity, further shorten the heating-up time of silicon chip, improve equipment capacity.
Brief description of the drawings
Fig. 1 is the structural representation of silicon based hetero-junction solar cell;
Fig. 2 is silicon chip surface heating-up temperature temporal evolution curve in vacuum;
Fig. 3 is the schematic flow sheet that increases silicon based hetero-junction solar cell production capacity technique in first embodiment of the invention.
Fig. 4 is the new temperature variation curve of silicon chip surface in old technology in long-pending chamber;
Fig. 5 is the schematic flow sheet that increases silicon based hetero-junction solar cell production capacity technique in second embodiment of the invention.
Fig. 6 is the time variation diagram of the interior deposition intrinsic amorphous silicon membrane of same deposit cavity and doped amorphous silicon film
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implemented but the present invention can also adopt other to be different from additive method described here, therefore the present invention is not subject to the restriction of following public specific embodiment.
Figure 1 shows that the structure of two-sided silicon based hetero-junction solar cell, preparing this battery need be at the emission layer (a-SiH (p) or μ c-SiH (p)) of intrinsic amorphous silicon film (a-SiH (i)), P type amorphous silicon or microcrystal silicon and the back surface field layer (a-SiH (n) or μ c-SiH (n)) of N-type amorphous silicon or microcrystal silicon of N-type surface of crystalline silicon deposition very thin (2-20nm), correspondingly, the sedimentation time of these films is also inevitable very short.
Figure 2 shows that silicon chip surface temperature is with the Changing Pattern of heating time, this curve is the hydrogen that passes into 500sccm flow in vacuum deposit chamber, maintains 0.5mbar air pressure and heter temperature and is set under 200 DEG C of conditions and tests gained.Can find out, the variation of silicon chip surface temperature has feature first quick and back slow, especially when silicon chip surface temperature is more approaching while presetting 200 DEG C of temperature, the temperature-rise period of silicon chip is just slower, in traditional handicraft because the design temperature of heater is technological temperature,, in the time that silicon temperature more approaches technological temperature, silicon chip heats up just slower, makes it have to wait for that the longer time just can reach corresponding temperature standard in deposit cavity.
Comprehensive above can find out, for the way that in traditional handicraft, heter temperature is set in advance as to described silica-base film technological temperature, will inevitably make the time far more than silicon chip surface deposit film silicon chip heating time.The time that common silicon chip surface temperature is heated to technological temperature with the scope of utilizing chemical gaseous phase depositing process to prepare the ratio of the time of silica-base film is: 4/1-12/1.So, the silicon chip long Main Bottleneck that just becomes the raising of limiting device production capacity heating time.In order to address this problem, the invention provides a kind of technique that increases silicon based hetero-junction solar cell production capacity, below with reference to accompanying drawing, this is described in detail.
the first embodiment:
The invention provides a kind of technique that increases silicon based hetero-junction solar cell production capacity, this technique is for the preparation of the silica-base film in described silicon based hetero-junction solar cell, and Fig. 3 shows the schematic flow sheet of the first embodiment, and this technique comprises the steps:
Step S1, provides the production equipment of silicon based hetero-junction solar cell, and it comprises into sheet chamber and deposit cavity, is provided with the heater that silicon chip is heat-treated in described deposit cavity;
Step S2, adopts wet-chemical cleaning mode that described silicon chip surface is cleaned and is dried;
Step S3, by described chip transmission to described in enter in sheet chamber, and vacuumize processing;
Step S4, then by described silicon chip from described enter sheet chamber transfer to described deposit cavity, be vacuum environment in this deposit cavity, the temperature of described heater is set in advance as higher than the technological temperature of preparing described silica-base film;
Step S5 in the time that the surface temperature of described silicon chip is heated to the technological temperature of described silica-base film, utilizes chemical gaseous phase depositing process to prepare described silica-base film in described deposit cavity.
Below each step is elaborated:
For step S1, the production equipment of described silicon based hetero-junction solar cell can strengthen chemical vapor depsotition equipment, hot-filament chemical vapor deposition equipment (HWCVD) etc. for chemical vapour deposition (CVD) (PECVD) equipment, surface wave plasma that plasma strengthens.
Alternatively, the production equipment of described silicon based hetero-junction solar cell is radio frequency PECVD equipment, and its rf frequency is 13.56-100MHz.
Alternatively, described silicon chip can be the one in n type single crystal silicon, p type single crystal silicon, N-type polysilicon, P type polysilicon.
The production equipment of described silicon based hetero-junction solar cell comprises into sheet chamber and deposit cavity, described deposit cavity is vacuum environment, its number is at least one, in described deposit cavity, be provided with the heater that silicon chip is heat-treated, the mode of heating of described heater can be resistance heating, infrared heating, induction heating etc.
Preferably, adopt resistance heating mode to heat.
For step S2, described wet-chemical cleaning mode comprises that employing acid solution or aqueous slkali clean described silicon chip, described acid solution can be a kind of or its combination in HNO3, HF, HCL, described aqueous slkali can be a kind of or its combination in NaOH, KOH, the compressed air that described drying means can adopt heating or not heat, nitrogen, one or several gases in argon gas are dried.
For step S3, after entering in sheet chamber described in described silicon chip is transferred to, to described enter sheet chamber vacuumize, air pressure is at least down to below 1mbar.
For step S4, described silica-base film can be the films such as amorphous silicon membrane, microcrystalline silicon film, Nano thin film, silicon oxide film, silicon oxynitride film, carborundum films, silicon nitride film.
Preferably, described for amorphous silicon membrane can be the one in intrinsic amorphous silicon film, P type amorphous silicon membrane or N-type amorphous silicon membrane.
Described deposit cavity is vacuum environment, and the temperature of described heater is set in advance as to the technological temperature higher than described silica-base film, and particularly, the technological temperature of described silica-base film is 150-320 DEG C.Particularly, the temperature of described heater is set in advance as 180 DEG C-350 DEG C.
Preferably, the technological temperature of described silica-base film is 150 DEG C, and described heter temperature is set in advance as 200 DEG C.
Alternatively, the thickness range of described silica-base film is 2-20nm.
Alternatively, if heter temperature is set in advance as and equals described silica-base film technological temperature, silicon chip surface temperature is heated to the time of this technological temperature and with the scope of utilizing chemical gaseous phase depositing process to prepare the ratio of the time of this film is: 4/1-12/1.
For step S5, in the time that the described silicon chip surface temperature of heating reaches the technological temperature of described silica-base film, in described deposit cavity, utilize chemical gaseous phase depositing process to prepare described silica-base film.
Alternatively, in the time period after described silicon chip is transferred in described deposit cavity and before carrying out chemical vapour deposition (CVD), to a kind of gas or several gas that pass in described deposit cavity in the hydrogen, nitrogen, argon gas of good heat conductivity
Particularly, in the present embodiment, the initial temperature of described silicon chip in deposit cavity is 25 DEG C of room temperatures, and the technological temperature of described silica-base film is 150 DEG C, described silica-base film is intrinsic amorphous silicon film, the new technology respectively the present invention being disclosed and the production capacity of traditional handicraft is compared to explanation below.
Figure 4 shows that the temperature variation curve of silicon chip surface in the interior new old technology of deposit cavity, what solid line represented is novel process of the present invention, the temperature of its heater is set in advance as 200 DEG C, higher than the technological temperature for the treatment of 150 DEG C of deposit films, dotted line represents traditional handicraft, and its heter temperature is set in advance as 150 DEG C of technological temperatures that equal to treat deposit film.Can find out, in traditional handicraft, because the temperature that presets of heater is technological temperature, and prior figures 2 shows that silicon chip surface temperature rising rule is: more approach heater design temperature and heat up slower, so silicon chip surface can only be longer time t3(approximately 500 seconds) reach technological temperature, and after PECVD overlay film process in, because the thickness for the treatment of depositing silicon base film only has nanometer scale, so the heavy film time t4-t3 of this PECVD is approximately 60 seconds, described like this silicon chip has to consume the 560-600 time of second in deposit cavity, the overlong time that described silicon chip surface temperature is heated to technological temperature becomes limiting device and has the bottleneck of higher production capacity.
In the disclosed novel process of the present invention, the temperature of heater is set in advance as to 200 DEG C, exceed 50 DEG C than its 150 DEG C pending technological temperature, due to the temperature difference existing between this heater and silicon chip, make silicon chip surface reach technological temperature in shorter time t1 (approximately 60 seconds), then in PECVD overlay film process, because the needed time t2-t1 of silica-base film of depositing nano magnitude is also about 60 seconds, the time span that both consume is substantially suitable, therefore the time that silicon chip is heated to technological temperature no longer becomes the bottleneck of limiting device production capacity, the total processing time of described silicon chip in deposit cavity can foreshorten to 120-150 second, thereby in the present invention, the processing time length of silicon chip in deposit cavity can be only traditional handicraft time 1/4-1/5 used, correspondingly, the production capacity of equipment has just improved 4-5 doubly.
It is pointed out that, owing to existing uniform temperature poor between described heater and described silicon chip, so silicon chip surface carries out in the process of overlay film, described silicon chip surface temperature not keeps constant, and can continue to increase.But on the other hand, owing to treating that very thin thickness, the overlay film time of deposit film are very short, so within the approximately 60 second time of PECVD overlay film, described silicon chip surface temperature rising difference is less than 10 DEG C, the amplitude of this increase can not affect film-forming process and the quality of forming film of PECVD substantially, therefore novel process provided by the present invention can ensure under the prerequisite of compound film quality and coating technique, make silicon chip reach technological temperature within the shorter time, thereby save the processing time of silicon chip in deposit cavity, improved the production capacity of equipment.In addition, in the present embodiment, because heating process is carried out in deposit cavity, just without additional configuration heating in vacuum chamber again, thereby also can save equipment cost.
the second embodiment:
For the industrial situation that need to deposit in silicon based hetero-junction solar cell surface dissimilar Multi-layer amorphous silicon thin film, for example on silicon chip, deposit intrinsic amorphous silicon film, P type amorphous silicon membrane, N-type amorphous silicon membrane, the present invention also provides a kind of technique that increases silicon based hetero-junction solar cell production capacity, this technique is for the preparation of intrinsic amorphous silicon film and doped amorphous silicon film in described silicon based hetero-junction solar cell, and Fig. 5 is the schematic flow sheet that increases silicon based hetero-junction solar cell production capacity technique in second embodiment of the invention.This technique comprises the steps:
Step S1, provides the production equipment of silicon based hetero-junction solar cell, and it comprises into sheet chamber and deposit cavity, is provided with the heater that silicon chip is heat-treated in described deposit cavity;
Step S2, adopts wet-chemical cleaning mode that described silicon chip surface is cleaned and is dried;
Step S3, by described chip transmission to described in enter in sheet chamber, and vacuumize processing;
Step S4, then by described silicon chip from described enter sheet chamber transfer to described deposit cavity, be vacuum environment in this deposit cavity, the temperature of described heater is set in advance as higher than the technological temperature of preparing described doped amorphous silicon film;
Step S5 in the time that the surface temperature of described silicon chip is heated to the technological temperature of described intrinsic amorphous silicon film, utilizes chemical gaseous phase depositing process to prepare described intrinsic amorphous silicon film in described deposit cavity;
Step S6, completes after described intrinsic amorphous silicon thin film deposition, stops this chemical vapour deposition reaction, waits for that described silicon temperature continues to be increased to the technological temperature of described doped amorphous silicon film;
Step S7, in the time that surface deposition has the silicon temperature of intrinsic amorphous silicon film to reach the technological temperature of described doped amorphous silicon film, in described deposit cavity, recycle chemical gaseous phase depositing process and continue the described doped amorphous silicon film of preparation on the surface of described intrinsic amorphous silicon film.
Step S1, S2, S3 in step S1, S2, S3 and the first embodiment in the present embodiment are similar, and its main distinction is step S4-S7, below will be elaborated to this:
In the present embodiment, described doped amorphous silicon film can be P type amorphous silicon membrane or N-type amorphous silicon membrane.Preferably, described doped amorphous silicon film is P type amorphous silicon membrane.
Alternatively, the thickness range of described intrinsic amorphous silicon film and described doped amorphous silicon film is 2-20nm.
Alternatively, silicon chip surface temperature described in step S5 is heated to the time of described intrinsic amorphous silicon thin-film technique temperature and with the scope of utilizing chemical gaseous phase depositing process to prepare the ratio of the time of described intrinsic amorphous silicon film is: 4/1-12/1.
Alternatively, the time that in step S7, surface deposition has the silicon temperature of described intrinsic amorphous silicon film to be heated to the thin middle membrane process temperature of described doped amorphous silicon with the scope of utilizing chemical gaseous phase depositing process to prepare the ratio of the time of described doped amorphous silicon film is: 4/1-12/1.
Alternatively, the technological temperature of described doping type amorphous silicon membrane is conventionally than the high 20-100 DEG C of the technological temperature of intrinsic amorphous silicon film.
Alternatively, the technological temperature scope of described intrinsic amorphous silicon film is 130-280 DEG C, and the technological temperature scope of described P type amorphous silicon membrane or described N-type amorphous silicon membrane is 150-320 DEG C.
Described deposit cavity is vacuum environment, and the temperature of described heater is set in advance as the technological temperature higher than described doped amorphous silicon base film, and particularly, the temperature range that described heater sets in advance is 180-350 DEG C
Preferably, the technological temperature of intrinsic amorphous silicon film is 140 DEG C, and the technological temperature of P type amorphous silicon membrane is 180 DEG C, and the temperature of heater is set in advance as 220 DEG C.Figure 6 shows that the time variation diagram of the interior deposition intrinsic amorphous silicon membrane of same deposit cavity and doped amorphous silicon film, find out accordingly, be transferred to while starting to heat from 25 DEG C of room temperatures in described deposit cavity at silicon chip, the temperature of described silicon chip can first elapsed time t1(approximately 60 seconds) rise to 140 DEG C of the technological temperatures of intrinsic amorphous silicon film, and start the depositing operation of intrinsic amorphous silicon film, through t2-t1(approximately 60 seconds) time complete the preparation of described intrinsic amorphous silicon layer film.Complete after the preparation of described intrinsic amorphous silicon film, stop this PECVD process, wait for that described silicon temperature continues to raise until reach 180 DEG C of the technological temperatures of described P type amorphous silicon membrane, the time span of described wait is t5-t2 (approximately 200 seconds), and then start at described intrinsic amorphous silicon surface preparation P type amorphous silicon membrane, this preparation time is t6-t5(approximately 200 seconds).Finally, the total processing time of described silicon chip in deposit cavity is altogether 520 seconds.And in traditional handicraft, need deposition intrinsic amorphous silicon membrane and P type amorphous silicon membrane in two deposit cavities respectively, now the total processing time of described silicon chip in deposit cavity approximately needs 1000 seconds.New old technology is compared and can be found out, all there is temperature difference by utilizing between heater and various different process temperature in new technology provided by the invention, no matter make silicon chip be heated to which kind of technological temperature, all can reach with speed faster, play the object of saving the silicon chip processing time in deposit cavity, improving equipment capacity, on the other hand, because the method does not need silicon chip frequent transmission between different deposit cavities, therefore also can reduce the cross pollution between cracked risk and vacuum environment and the atmosphere of transmitting procedure silicon chip.
In addition, with reason same in embodiment, owing to existing uniform temperature poor between described heater and described silicon chip, so silicon chip surface carries out in the process of overlay film, described silicon chip surface temperature can continue to increase.Again owing to treating that very thin thickness, the overlay film time of deposit film are very short, so in the PECVD of intrinsic amorphous silicon and doped amorphous silicon film method preparation process, described silicon chip surface temperature rising difference is all less than 10 DEG C, the amplitude of this increase can not affect film-forming process and the quality of forming film of PECVD substantially, and therefore novel process provided by the present invention can also ensure compound film quality and coating technique in improving equipment capacity.
Alternatively, in step S5 in the 5th step in the time period after described silicon chip is transferred in described deposit cavity and before carrying out chemical vapour deposition (CVD), to a kind of gas or several gas that pass in described deposit cavity in the hydrogen, nitrogen, argon gas of good heat conductivity.
Alternatively, in step S6 waiting for that described silicon temperature continued to be increased in the time period of described doped amorphous silicon film technological temperature, to one or more the gas passing in described deposit cavity in the hydrogen, nitrogen, argon gas of good heat conductivity.
In possibility, when silicon temperature in deposit cavity not yet reaches before technological temperature, in this deposit cavity, pass into the gas that heat-conductive characteristic is good, for example, one or more gases in hydrogen, nitrogen, argon gas, can accelerate the heat transmission in deposit cavity, further shorten the heating-up time of silicon chip, improve equipment capacity.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes and amendment, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (16)
1. increase a technique for silicon based hetero-junction solar cell production capacity, this technique, for the preparation of the silica-base film in described silicon based hetero-junction solar cell, is characterized in that: this technique comprises the steps:
The first step, provides the production equipment of silicon based hetero-junction solar cell, and it comprises into sheet chamber and deposit cavity, is provided with the heater that silicon chip is heat-treated in described deposit cavity;
Second step, adopts wet-chemical cleaning mode that described silicon chip surface is cleaned and is dried;
The 3rd step, by described chip transmission to described in enter in sheet chamber, and vacuumize processing;
The 4th step, then by described silicon chip from described enter sheet chamber transfer to described deposit cavity, be vacuum environment in this deposit cavity, the temperature of described heater is set in advance as higher than the technological temperature of preparing described silica-base film;
The 5th step in the time that the surface temperature of described silicon chip is heated to the technological temperature of described silica-base film, utilizes chemical gaseous phase depositing process to prepare described silica-base film in described deposit cavity.
2. a kind of technique that increases silicon based hetero-junction solar cell production capacity according to claim 1, is characterized in that: described silica-base film is one or more in amorphous silicon, microcrystal silicon, carborundum, silicon oxynitride, silicon nitride, silica, polysilicon membrane, germanium-silicon film.
3. a kind of technique that increases silicon based hetero-junction solar cell production capacity according to claim 2, is characterized in that: described amorphous silicon membrane is the one in intrinsic amorphous silicon film, P type amorphous silicon membrane or N-type amorphous silicon membrane.
4. a kind of technique that increases silicon based hetero-junction solar cell production capacity according to claim 1, it is characterized in that: when described heter temperature is set in advance as while equaling described silica-base film technological temperature, the time that described silicon chip surface temperature is heated to described silica-base film technological temperature with the scope of utilizing chemical gaseous phase depositing process to prepare the ratio of the time of described silica-base film is: 4/1-12/1.
5. increase a technique for silicon based hetero-junction solar cell production capacity, this technique, for the preparation of intrinsic amorphous silicon film and doped amorphous silicon film in described silicon based hetero-junction solar cell, is characterized in that: this technique comprises the steps:
The first step, provides the production equipment of silicon based hetero-junction solar cell, and it comprises into sheet chamber and deposit cavity, is provided with the heater that silicon chip is heat-treated in described deposit cavity;
Second step, adopts wet-chemical cleaning mode that described silicon chip surface is cleaned and is dried;
The 3rd step, by described chip transmission to described in enter in sheet chamber, and vacuumize processing;
The 4th step, then by described silicon chip from described enter sheet chamber transfer to described deposit cavity, be vacuum environment in this deposit cavity, the temperature of described heater is set in advance as higher than the technological temperature of preparing described doped amorphous silicon film;
The 5th step in the time that the surface temperature of described silicon chip is heated to the technological temperature of described intrinsic amorphous silicon film, utilizes chemical gaseous phase depositing process to prepare described intrinsic amorphous silicon film in described deposit cavity;
The 6th step, completes after described intrinsic amorphous silicon thin film deposition, stops this chemical vapour deposition reaction, waits for that described silicon temperature continues to be increased to the technological temperature of described doped amorphous silicon film;
The 7th step, in the time that surface deposition has the silicon temperature of intrinsic amorphous silicon film to reach the technological temperature of described doped amorphous silicon film, in described deposit cavity, recycle chemical gaseous phase depositing process and continue the described doped amorphous silicon film of preparation on the surface of described intrinsic amorphous silicon film.
6. a kind of technique that increases silicon based hetero-junction solar cell production capacity according to claim 4, is characterized in that: described doped amorphous silicon film is the one in P type amorphous silicon membrane or N-type amorphous silicon membrane.
7. a kind of technique that increases silicon based hetero-junction solar cell production capacity according to claim 5, it is characterized in that: the time that silicon chip surface temperature described in the 5th step is heated to described intrinsic amorphous silicon thin-film technique temperature is the time that in the 4/1-12/1, seven step, surface deposition has the silicon temperature of described intrinsic amorphous silicon film to be heated to the thin middle membrane process temperature of described doped amorphous silicon to be with the scope of utilizing chemical gaseous phase depositing process to prepare the ratio of the time of described doped amorphous silicon film with the scope of utilizing chemical gaseous phase depositing process to prepare the ratio of the time of described intrinsic amorphous silicon film: 4/1-12/1.
8. according to a kind of technique that increases silicon based hetero-junction solar cell production capacity described in claim 1 or 5, it is characterized in that: utilizing chemical gaseous phase depositing process to prepare in the sedimentation time of described silica-base film, described intrinsic amorphous silicon film, described doped amorphous silicon film, the rising scope of described silicon chip surface temperature is all less than 10 DEG C.
9. a kind of technique that increases silicon based hetero-junction solar cell production capacity according to claim 5, is characterized in that: the technological temperature of described doped amorphous silicon film is than the high 20-100 DEG C of the technological temperature of described intrinsic amorphous silicon film.
10. a kind of technique that increases silicon based hetero-junction solar cell production capacity according to claim 1 or 5, it is characterized in that: in the time period in the 5th step after described silicon chip is transferred in described deposit cavity and before carrying out chemical vapour deposition (CVD), in described deposit cavity, pass into a kind of gas or several gas in hydrogen, nitrogen, argon gas.
11. a kind of techniques that increase silicon based hetero-junction solar cell production capacity according to claim 5, it is characterized in that: in the 6th step waiting for that described silicon temperature continued to be increased in the time period of described doped amorphous silicon film technological temperature, to one or more the gas passing in described deposit cavity in hydrogen, nitrogen, argon gas.
12. a kind of techniques that increase silicon based hetero-junction solar cell production capacity according to claim 1 or 5, is characterized in that: described silicon chip is the one in n type single crystal silicon, p type single crystal silicon, N-type polysilicon, P type polysilicon.
13. a kind of techniques that increase silicon based hetero-junction solar cell production capacity according to claim 1 or 5, is characterized in that: described silica-base film, described intrinsic amorphous silicon film and described doped amorphous silicon film thickness range are 2-20nm.
14. a kind of techniques that increase silicon based hetero-junction solar cell production capacity according to claim 1 or 5, is characterized in that: described technique both can, for the preparation of lateral silicon base heterojunction solar cell, also can be prepared two-sided silicon based hetero-junction solar cell.
15. a kind of techniques that increase silicon based hetero-junction solar cell production capacity according to claim 1 or 5, is characterized in that: the production equipment of described silicon based hetero-junction solar cell is PECVD equipment, described chemical gaseous phase depositing process is PECVD method.
16. a kind of techniques that increase silicon based hetero-junction solar cell production capacity according to claim 15, is characterized in that: described PECVD device power supply (DPS) is radio-frequency power supply, its rf frequency scope is 13.56-100MHz.
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