CN104157580B - Embedding chip interconnection packaging method and structure based on anode oxidation technology - Google Patents
Embedding chip interconnection packaging method and structure based on anode oxidation technology Download PDFInfo
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Abstract
The present invention relates to a kind of embedding chip interconnection packaging method based on anode oxidation technology and structure.Select the aluminium flake of low cost as the embedding substrate of chip, dual sided porous type pellumina is prepared with anode oxidation technology；Protected using straight-flanked ring aluminium chamber, and porous alumina film selective corrosion characteristic, obtain the cavity body structure of embedding chip, complete chip coplanar embedding；The technique such as photoetching and thin film metal layer wiring is filled by front dielectric layer, embedding chip interconnection is completed.Positioning precision of the present invention is high, and embedding chamber size is good with chip matching, effectively solves inexpensive, the coplanar embedding problem of high accuracy of different chip sizes；And can well solve the problems, such as chip cooling using the design of back aluminium through post；Dielectric layer with low-k may act as surface protection film, interlayer dielectric, the Woelm Alumina deep trench filler of chip, enables in particular to solve the problems, such as aluminium base surface planarisation, improves substrate bending or warpage, meet thin-film technique.
Description
Technical field
The invention belongs to technical field of semiconductor encapsulation, more particularly, to a kind of embedding core based on anode oxidation technology
Piece interconnecting method.
Background technology
Embedding chip interconnection technique, be during chip is embedded into substrate or dielectric layer after, then unification carry out metal line, will
The welding zone of chip is connected naturally with wiring metal.Interconnection between this chip welding zone and substrate welding zone belongs to of metal line
Point, interconnect without the vestige of any " welding ".Embedding chip interconnection also can further improve Electronic Assemblies density and electronics is produced
The reliability of product, is a kind of effective form for further realizing three-dimension packaging, and it can eliminate traditional chip and substrate metal
All kinds of pads of welding zone, and the manufacturing process of device does not need solder, has with solder and backflow and directly or indirectly closes
A large amount of defects of system will disappear, so as to improve the reliability of electronic product.
The main of embedding chip interconnection mode has two kinds, can be used on organic substrate, ceramic substrate, silicon substrate, Metal Substrate
On plate.One kind is medium burial method on substrate, chip can be carried out by techniques such as medium photoetching, dry etchings it is embedding, it is embedding
Laggard row metalization wiring, the method is higher to dielectric property requirement, relatively infrequently；Another kind is fluting burial method, is by core
Directly in embedding substrate cavity, the method can increase the directly contact area of substrate and chip to piece, make substantial amounts of chip heat fast
Speed is distributed by substrate, it is ensured that the operating temperature of chip and whole package assembling is in appropriate scope；Also, substrate is directly buried
The environment that mode provides a high intensity, high-isolation to chip is put, is conducive to protecting chip.This kind of fluting buried inter side
Formula is relatively conventional.
Silicon substrate has thermal conductivity [84W/ (mK)] high, and the advantage good with chip CTE matching degree, turns into
The preferred material of buried inter mode of slotting.But there is also some problems.On the one hand it is to carry out embedding chip cavity processing
When, frequently with dry etching or wet corrosion technique, dry etching positioning precision processing cost high but high turns into high-volume
Production and processing, a big obstacle of integra-tion application.And the inverted trapezoidal structure that silicon substrate wet etching is then easily formed, inclination angle is
50 °~60 °, corrosion process control accuracy is poor, causes chip positioning precision relatively low；The mechanical strength of another aspect Si materials is low,
After embedding chip can be because of deposited metal and dielectric layer when interconnecting, larger bending and warpage issues are produced, influence product reliability
Property.Therefore need a kind of new method badly at present, solve the above problems and reduce processing cost.
The content of the invention
To solve problems of the prior art, a kind of embedding core based on anode oxidation technology of proposition of the invention
Piece interconnection packaging method and structure, technical scheme are as follows：
A kind of embedding chip interconnection packaging method based on anode oxidation technology, at least comprises the following steps：
S1：Anodic oxidation pre-treatment step, the aluminium base (101) is placed in carries out anodic oxygen in anodic oxidation electrolyte
Change pretreatment, surface is formed one layer of pellumina (102), to increase substrate surface adhesive force；
S2：Photoresist mask fabrication step against corrosion, the aluminium base (101) after being processed through S1 is divided into tow sides,
The front surface embedding as chip is made, reverse side is used as the surface for making radiation aluminium through post.Photoetching is carried out to described front
Glue spin coating, front baking, exposure, development, the rear operation dried, straight-flanked ring photoresist mask (103,104) is formed in the front；To institute
The reverse side stated carries out the same operation of photoresist, and aluminium through post photoresist mask (105) is formed in the reverse side；
S3：Two-sided anodization step, the aluminium base (101) after being processed through S2 is placed in anodic oxidation electrolyte
Anodic oxidation is carried out, anodic oxidation part makes porous alumina layer (107,108), and non-oxidized portion front forms straight-flanked ring
Aluminium cavity (106), reverse side forms aluminium through post (109), and described porous alumina layer (107,108) thickness is more than chip thickness；
S4：Metal mask making step, removal described straight-flanked ring photoresist mask (103,104) and aluminium through post photoresist
Mask (105), the aluminium base (101) is placed in aluminum oxide corrosive liquid and erodes pellumina (102) and partially porous type
Alumina layer (107,108), porous alumina layer (107,108) corrosion to front straight-flanked ring aluminium cavity (106) and
Reverse side aluminium through post (109) is highly consistent；
Front sputtering layer of metal layer mask (110) on the aluminium base (101), reverse side sputtering layer of metal layer
(111) photoresist figure, then on the metal mask layer (110) is formed by photoresist gluing, front baking, exposure, development, rear baking
Shape mask (112), in the reverse side spin coating photoresist of the aluminium base (101), solidifying to form photoresist diaphragm one (113) is used for
Described metal level (111) is prevented to be corroded；
S5：The embedding cavity making step of selective corrosion, using corresponding selective corrosion liquid respectively sequentially to metal level
Mask (110), porous alumina layer (107) carry out wet etching, and the embedding chamber of chip is formed in straight-flanked ring aluminium chamber (106)
(114,115)；
S6：Die bonding layer making step, removal described photoetching offset plate figure mask (112) and photoresist diaphragm one
(113), in the reverse side spin coating photoresist of the aluminium base (101), photoresist diaphragm two (116) is solidify to form for preventing
The metal level (111) stated is corroded, and positive metal mask layer (110) is fallen using selective corrosion corrosion；
Layer of metal is sputtered in the front, plating thickeies, and carry out photoresist spin coating, front baking, exposure, development, rear baking
Operation, form embedding cavity photoresist mask (119,120), wet etching is carried out using selective corrosion liquid, remove embedding
Cavity photoresist mask (119,120), forms chip tack coat (117,118)；
S7：The embedding step of chip, removal photoresist diaphragm two (116), with conducting resinl by chip one (121) and chip two
(122) it is embedded in the embedding chamber of the chip (114,115), is bonded in solidify afterwards on die bonding layer (117,118), chip electricity
Pole court exposes outside；
S8：Dielectric layer fill making step, described front is carried out with photosensitive medium spin coating, standing, front baking, exposure,
Development, it is rear dry, form dielectric layer (123) and Filled Dielectrics porous alumina layer (126), expose electrode dielectric through hole (124,
125), it is placed in vacuum drying oven and is solidified；
S9：Chip electrode metal level making step, front sputtering layer of metal, two-sided on positive dielectric layer (123)
Plating thickeies, and reverse side forms plating thickening layer (129).Front carries out photoresist lithography operations, and reverse side spin coating photoresist solidifies shape
Into photoresist diaphragm three (130), for preventing described plating thickening layer (129) to be corroded, front uses selective corrosion
Liquid carries out wet etching, then front, reverse side removal photoresist, forms chip electrode metal level (127,128), so far completes embedding
The making of chip interconnection packaging method.
Further,
Anodic oxidation electrolyte described in step S1, S3 is the acid class electrolyte such as sulfuric acid, phosphoric acid, chromic acid or oxalic acid；
10~20V of decomposition voltage in step S1；
(103, the 104) internal diameter of straight-flanked ring photoresist mask described in step S2 is set according to chip size, internal diameter
The difference of external diameter is set in 0.4~1mm scopes, and aluminium through post photoresist mask (105) is with diameter greater than or equal to 0.2mm；
Layer (107, the 108) thickness of porous alumina described in step S3 is bigger than chip thickness 10~20 μm, decomposition voltage
50~70V；
Metal mask layer (110) described in step S4 and metal level (111) are TiW/Cu film layers, and thickness isTiW and thickness beCu；
Corresponding selective corrosion liquid is described in step S5, S6：The corrosive liquid of TiW is H2O2, Cu corrosive liquids proportioning (volume
Than) it is HCl:H2O2:H2O=1:3:10, while corrosive liquid proportioning (volume ratio) of Cu and Ni layers of corrosion is HNO3：H2O=1:
1, Au corrosive liquid proportioning (mass ratio) is I2：KI:H2O=3:20:100；Al corrosive liquids proportioning (volume ratio) are HNO3:
H3PO4:CH3COOH:H2O=1:16:1:2；Woelm Alumina corrosive liquid proportioning (mass fraction) is 6% phosphoric acid and 1.8% chromium
The mixed liquor of acid；
Die bonding layer (117,118) and chip electrode metal level (126,127), its sputtered film described in step S6, S7, S9
System is TiW/Cu film layers, and electrodeposited coating is Cu/Ni/Au metal levels.
Solidification described in step S7 is specially and keeps 100 DEG C of 60~80min of temperature-curable time；
Dielectric layer time of repose described in step S8 is no less than 1 hour；
The embedding cake core interconnection package structure of aluminium base manufactured by methods described, including at least aluminium base (101), chip
(121,122), dielectric layer (123), chip electrode metal level (126,127)；The chip (121,122) is embedded in the aluminium base
In plate (101), the filling of groove front of the aluminium base (101) has stated dielectric layer (123), the chip electrode metal level (127,
128) it is connected on the aluminium base (101) positive dielectric layer (123).
Further, aluminium base (101) front is additionally provided with Filled Dielectrics porous alumina layer (126), straight-flanked ring
Aluminium cavity (106), die bonding layer (117,118), reverse side are additionally provided with porous alumina layer (108) and aluminium through post (109).
Further, the dielectric layer (123) is PI or BCB, and dielectric layer (123) thickness is 10~15 μm, described
Chip electrode metal level (127,128) thickness is 3~5 μm.
Further, it is set to electroplate thickening layer under the porous alumina layer (108) of aluminium base (101) reverse side
(129)。
Further, in described die bonding layer and chip electrode metal level (126,127), its sputtered layer is thickness
DegreeTiW and thicknessCu；Plating film layer is the Cu that thickness is 3~5 μm, and thickness is 5
~8 μm of Ni, thickness is 0.5~1.2 μm of Au.
The present invention has the advantages that：
Embedding chip interconnection packaging method and structure based on anode oxidation technology of the present invention, using aluminum
As substrate substrate, there are thermal conductivity [more than 150W/ (mK)] high, low cost, that Woelm Alumina thermal coefficient of expansion is adjustable etc. is excellent
Point.Based on anode oxidation technology, protected using straight-flanked ring metallic aluminium chamber, and porous alumina film selective corrosion spy
Property, it is high to make positioning precision, and embedding chamber size and the more preferable chip embedding structure of chip matching, effectively solves different
The coplanar embedding problem of low-cost and high-precision of chip size, improves the precision of chip positioning；And can be fine using aluminium through post
Ground solves the problems, such as chip cooling；By the use of the liquid or gum polymers of low-k as dielectric layer, the table of chip is may act as
Surface protective film, interlayer dielectric, Woelm Alumina deep trench filler, are particularly advantageous in aluminium base surface planarisation, improve
Substrate bending or the problem of warpage, meet thin-film technique, improve chip interconnection, the reliability of interlayer interconnection.
The embedding chip interconnection methodologies that the present invention is taken, by existing process technology, slightly optimization is promoted, you can realized
Multilayer wiring interconnection structure, and the work(of module can be realized with upside-down mounting welding core or surface component on multilayer interconnection structure
Energyization.
Brief description of the drawings
Fig. 1-Figure 12 is embedding chip interconnection packaging method implementation steps and counter structure based on anode oxidation technology；
Figure 13 is the wafer top view of front straight-flanked ring aluminium cavity after the two-sided anodic oxidation of aluminium base；
Figure 14 is the wafer top view of reverse side aluminium through post after the two-sided anodic oxidation of aluminium base；
Figure 15 is the embedding chip interconnection packaging method implementation steps flow chart based on anode oxidation technology.
It is denoted as in figure：
101：Metal aluminium substrate；102：Pellumina；103、104：Straight-flanked ring photoresist mask；105：Aluminium through post photoresist
Mask；106：Straight-flanked ring aluminium cavity；107、108：Porous alumina layer；109：Aluminium through post；110：Metal mask layer；111：Gold
Category layer；112：Photoetching offset plate figure mask；113：Photoresist diaphragm one；114：115：The embedding chamber of chip；116：Photoresist is protected
Film two；117、118：Die bonding layer；119、120：Embedding cavity photoresist mask；121：Chip one；122：Chip two；123：
Dielectric layer；124、125：Dielectric layer through hole；126:Filled Dielectrics porous alumina layer；127、128：Chip electrode metal level；
129：Metal thickening layer；130：Photoresist diaphragm three.
Specific embodiment
The present invention is described in detail in the way of specific embodiment below in conjunction with the accompanying drawings.Following examples will be helpful to
Those skilled in the art further understands the present invention, but the invention is not limited in any way.It should be pointed out that to ability
For the those of ordinary skill in domain, without departing from the inventive concept of the premise, various modifications and improvements can be made.These
Belong to protection scope of the present invention.
Embedding chip interconnection packaging method based on anode oxidation technology of the invention is buried with silicon substrate of the prior art
Put the processing method that chip interconnection is required for using photoetching.In the process of current silica-based embedded chip interconnection, will relate to
And multiple photo-etching technological process, although the purpose requirement of each photoetching and process conditions difference, but its technical process is base
This identical.Photoetching process typically (will afterwards dry), corrode and remove photoresist by spin coating, front baking, exposure, development, post bake
Seven steps：
1st, gluing：Gluing is exactly in SIO2Or other film substrate surfaces, it is coated with one layer of adhesion well, thickness is appropriate, thick
Thin uniform photoresist film.Before gluing preferably after oxidation or evaporation gluing immediately, the now drying of substrate surface cleaning, photoresist
Adhesiveness it is preferable.Gluing typically uses rotary process, and its principle is, using the centrifugal force produced when rotating, will to drop in many of substrate
Remaining glue gets rid of, and under photoresist surface tension and rotary centrifugal force collective effect, is extended to glued membrane in uniform thickness.Glued membrane is thick
Degree can be adjusted by the concentration of rotating speed and glue.The thickness of gluing is appropriate, uniform film thickness, and adhesion is good.Glued membrane is too thin, then pin
Kong Duo, resistance to corrosion is poor；Glued membrane is too thick, then resolution ratio is low.In general, distinguishable line width is about 5~8 times of thickness.
2nd, front baking：Front baking is exactly at a certain temperature, the solvent in glued membrane is lentamente evaporated, and does glued membrane
It is dry, and increase its adhesiveness and wearability.The temperature and time of front baking difference, one with the species of glue and the difference of thickness
As determined by testing.The temperature and time of front baking must be appropriate.Temperature is too high to cause the heat cross-linking of resist,
Counterdie is left during development, or sensitizer distillation volatilization declines luminous sensitivity；Pre-bake temperature is too low or the time is too short, then resist
Organic solvent in erosion agent can not fully volatilize, and the solvent molecule of residual can hinder light interlinkage reaction, so as to cause pinhold density
Increase, floating glue or figure deformation etc..Meanwhile, can't be shock heating during front baking, in order to avoid causing surface blisters, produce pin hole even floating
Glue.General front baking is toasted 10-15 minutes in 80 DEG C of thermostatic drying chambers；Can also be toasted in substrate back with thermal station, make glue
The drying of film from the inside to surface, to obtain good front baking effect.
3rd, expose：Exposure is exactly that the substrate to scribbling photoresist carries out selective light chemical reaction, makes the light of exposed portion
Dissolubility of the photoresist in developer solution changes, it is developed after the figure corresponding with mask plate is obtained on photoresist film.
In production, ultraviolet light exposure exposure method is generally all used, its basic step is positioning alignment and exposes.Positioning alignment is to make mask
The accurate fit of figure on the figure and substrate of version, therefore it is required that litho machine has good alignment device, i.e., with the micro- of precision
Mediation hold-down mechanism, particularly ensures that accurate fit is not subjected to displacement when compressing.Additionally, litho machine should also have suitable light
Learn observing system, it is desirable to have a depth of field larger, while there is microscope high-resolution enough again.The selection of light exposure is decided by
The spatial distribution of the absorption spectrum of photoresist, proportioning, thickness and light source.The determination of optimum exposure, it is also contemplated that the light of substrate
Reflection characteristic.In actual production, light exposure is often controlled with the time for exposure, and determine during optimum exposure by testing
Between.
4th, develop：Development be exposure after substrate be placed in appropriate solvent, the photoresist film that should will be removed is molten except dry
Only, obtaining the protection figure of resist film required during corrosion.
5th, post bake (drying afterwards)：Post bake dries after being called, and is that the silicon chip after development is bakeed at a certain temperature, removes aobvious
Glued membrane is absorbed during shadow developer solution and the moisture content of residual, improve the adhesiveness of glued membrane and silicon chip, strengthen the resistance to corrosion of cornea.
The temperature and time of post bake is appropriate.Post bake is not enough, then resist glued membrane does not dry, film and substrate poor adhesion, during corrosion
Easy floating glue；Post bake temperature is too high, then resist glued membrane can warpage or peeling because of thermal expansion, can equally be produced during corrosion undercutting or
Floating glue.When temperature is higher, polymer will be decomposed, and influence adhesiveness and resistance to corrosion.Additionally, preferably with slow intensification during post bake
With the baking process of natural cooling.The thick film etching more long for etching time, can again carry out a post bake after half is corroded,
To improve the resistance to corrosion of glued membrane.
6th, corrode：Corrosion is exactly with appropriate corrosive agent, the SiO to not being photo-etched glued membrane covering2Or other films are carried out
Corrosion, to obtain complete, clear, accurate litho pattern, reaches the purpose of selectivity diffusion or metal line.Photoetching process pair
The requirement of corrosive agent is：Only the material for needing to remove is corroded, and resist glued membrane is not corroded or etching extent very little.Together
When, also require that corrosion factor is sufficiently large.The definition of corrosion factor is the ratio between lateral encroaching amount of corrosion depth and a side.It is rotten
The erosion factor is bigger, represents that lateral encroaching amount is smaller.Furthermore it is required that etch pattern neat in edge, clear；Corrosive liquid small toxicity,
It is easy to use.
For the corrosion of aluminium, the corrosive liquid commonly used at present has phosphoric acid and potassium permanganate corrosive liquid.It is to utilize it for phosphoric acid
Water-soluble aluminium acid phosphate can be generated with reactive aluminum, to reach the purpose of corrosion, its reaction equation is：2Al+6H3PO4=2Al
(H2PO4)3+3H2.Be can be seen that from reaction equation, react fierce during corrosion, had bubble and constantly emerge, it is uniform that influence is corroded
Property.Therefore, a small amount of absolute ethyl alcohol can be added in corrosive liquid or in corrosion using ultrasonic vibration, to remove the gas of reaction generation
Bubble.
7th, remove photoresist：No longer need photoresist to make protective layer after corrosion is completed, can be removed.The method removed photoresist
Often have that wet method is removed photoresist and dry method is removed photoresist two classes：
A () wet method is removed photoresist
1. organic solvent removes photoresist：Photoresist is removed using organic solvent；
2. inorganic solvent：By using some inorganic solvents, the carbon in this organic matter of photoresist is oxidized to two
Carbonoxide, and then and be removed；
B () dry method is removed photoresist：Photoresist is divested using plasma.
Plating is exactly the process for plating other metal or alloy of last layer thin layer on some metal surfaces using electrolysis principle,
Playing prevents metal from aoxidizing, and improves the effect such as wearability, electric conductivity, corrosion resistance, and the metallization of substrate is typically using plating Cu/
Ni/Au electrodeposition of metals, electrodeposition of metals Cu/Ni/Au membrane systems thickness need to meet certain limit, and general Cu is adhesion layer, thickness
It it is 3~5 μm, Ni can stop the diffusion of Cu and Au as barrier layer, and thickness is 5~8 μm, and Au is main conductor layer, with excellent
Solderability, electric conductivity, corrosion resistance and inoxidizability, thickness are 0.5~1.2 μm.
It is as Figure 1-Figure 11 embedding chip interconnection packaging method implementation steps based on anode oxidation technology and right
Answer structure chart 14 for method and step flow chart, the corresponding operating process of Fig. 1-Figure 11 is as follows：
S101：Anodic oxidation pre-treatment step, the aluminium base (101) is placed in carries out anode in anodic oxidation electrolyte
Oxidation pre-treatment, makes surface form one layer of pellumina (102), to increase substrate surface adhesive force, structure as shown in Figure 1.
Compared with the current silicon substrate for using, the present invention uses aluminum as substrate, there is thermal conductivity high, low cost, many
The advantages of porous aluminum oxide thermal coefficient of expansion is adjustable.
Aluminium base (101) material typically selects fine aluminium Al1060 materials, and thermal conductivity is 217W/ (mK).By the aluminium of 0.3mm
Substrate (101) carries out surface polishing to aluminum with method chemically or mechanically, then cleans to remove table with acetone, ethanol solution
Face greasy dirt and impurity, are placed in the phosphoric acid as anodic oxidation electrolyte and are pre-oxidized, and obtain one layer of pellumina (102),
The pellumina can increase substrate surface adhesive force.Wherein, the usable anodic oxidation electrolyte of the present invention is not limited to this implementation
The phosphoric acid of example, can also be using the acidic electrolysis bath such as sulfuric acid, chromic acid or oxalic acid, and decomposition voltage of the invention and electrolysis time are not yet
It is limited to the present embodiment, decomposition voltage setting range is 10~20V, and electrolysis time setting range is 5~20min.
S102：Photoresist mask fabrication step against corrosion, the aluminium base (101) after being processed through S101 is divided into positive and negative two
Face, the front surface embedding as chip is made, reverse side is used as the surface for making radiation aluminium through post.Light is carried out to described front
Photoresist spin coating, front baking, exposure, development, the rear operation dried, straight-flanked ring photoresist mask (103,104) is formed in the front；It is right
Described reverse side carries out the same operation of photoresist, forms aluminium through post photoresist mask (105) in the reverse side, as shown in Figure 2
Structure；
Wherein, straight-flanked ring photoresist mask (103,104) identifies the position of presetting straight-flanked ring aluminium cavity (106) manufactured
And shape, the location and shape of the presetting aluminium through post (109) to be manufactured of aluminium through post photoresist mask (105) mark.Straight-flanked ring
Aluminium cavity (106) the correspondence embedding chamber of chip (114,115), for embedding chip (121,122)；Aluminium through post (109) can be used for aluminium
Substrate radiates.Straight-flanked ring photoresist mask (103,104) inside diameter ranges) internal diameter set according to chip size, internal diameter
The difference of external diameter is set in 0.4~1mm scopes, and aluminium through post photoresist mask (105) is with diameter greater than or equal to 0.2mm.
S103：Two-sided anodization step, the aluminium base (101) after being processed through S102 is placed in anodic oxidation electrolysis
Anodic oxidation is carried out in liquid, anodic oxidation part makes porous alumina layer (107,108), and non-oxidized portion front forms square
Shape ring aluminium cavity (106), reverse side forms aluminium through post (109), and described porous alumina layer (107,108) thickness is thick more than chip
Degree, forms structure as shown in Figure 3, and positive and negative wafer top view now is shown in Figure 13 and Figure 14.
S104：Metal mask making step, described straight-flanked ring photoresist mask (103,104) of removal and aluminium through post photoetching
Glue mask (105), the aluminium base (101) is placed in aluminum oxide corrosive liquid and erodes pellumina (102) and partially porous
Type alumina layer (107,108), porous alumina layer (107,108) corrosion to front straight-flanked ring aluminium cavity (106)
It is highly consistent with reverse side aluminium through post (109), form structure as shown in Figure 4.The present embodiment step 104 etching time is set as
20min, but the invention is not restricted to the present embodiment, the time is set in 10~30min scopes.
Front sputtering layer of metal layer mask (110) on the aluminium base (101), reverse side sputtering layer of metal layer
(111) structure as shown in Figure 5, is formed.Again on the metal mask layer (110) by photoresist gluing, front baking, exposure,
Development, rear baking form photoetching offset plate figure mask (112), in the reverse side spin coating photoresist of the aluminium base (101), solidify to form light
Photoresist diaphragm one (113) forms structure as shown in Figure 6 for preventing described metal level (111) to be corroded.
Photoresist diaphragm one (113) can also use anticorrosion adhesive tape in the present embodiment, and protection reverse side metal level (111) exists
It is not corroded during corrosion front, and is also convenient for tearing when removal is needed.Metal mask layer (110) and metal level (111) are
TiW/Cu film layers, thickness isTiW and thickness beCu；
S105：The embedding cavity making step of selective corrosion, using corresponding selective corrosion liquid respectively sequentially to metal
Layer mask (110), porous alumina layer (107) carry out wet etching, and the embedding chamber of chip is formed in straight-flanked ring aluminium chamber (106)
(114,115), structure as shown in Figure 7.
Wherein, corresponding selective corrosion liquid is respectively described in the present embodiment：The corrosive liquid of TiW is H2O2, Cu corrosive liquids
Proportioning (volume ratio) is HCl:H2O2:H2O=1:3:10, while corrosive liquid proportioning (volume ratio) of Cu and Ni layers of corrosion is HNO3：
H2O=1:1, Au corrosive liquid proportioning (mass ratio) is I2：KI:H2O=3:20:100；Al corrosive liquids match (volume ratio)
HNO3:H3PO4:CH3COOH:H2O=1:16:1:2；Woelm Alumina corrosive liquid proportioning (mass fraction) is 6% phosphoric acid and 1.8%
The mixed liquor of chromic acid；The corrosive liquid that pellumina (102), porous alumina layer (107,108) are used is identical.The embedding chamber of chip
The size of (114,115) coordinates with required embedding chip, because the embedding chamber cavity wall inclination angle that aluminium base wet etching goes out is general
More than 80 °, there is preferable matching degree with chip form.When chip is embedding, than that can obtain more accurate fixed using silicon substrate
Position.
S106：Die bonding layer making step, removal described photoetching offset plate figure mask (112) and photoresist diaphragm one
(113), in the reverse side spin coating photoresist of the aluminium base (101), photoresist diaphragm two (116) is solidify to form for preventing
The metal level (111) stated is corroded, and positive metal mask layer (110) is fallen using selective corrosion corrosion.
Layer of metal is sputtered in the front, plating thickeies, and carry out photoresist spin coating, front baking, exposure, development, rear baking
Operation, form embedding cavity photoresist mask (119,120), after carrying out wet etching using selective corrosion liquid, formed such as
Structure shown in Fig. 8.Embedding cavity photoresist mask (119,120) is removed, chip tack coat (117,118) is formed.
Step S106 chips adhesive linkage (117,118) the sputtering membrane system is TiW/Cu film layers, sputters thicknessTiW and thicknessCu；Described die bonding layer (117,118) electrodeposited coating is Cu/Ni/
Au metal levels, plating Cu thicknesses of layers is 3~5 μm, and electroplated Ni thicknesses of layers is 5~8 μm, plating Au thicknesses of layers is 0.5~
1.2μm。
S107：The embedding step of chip, removal photoresist diaphragm two (116), with conducting resinl by chip one (121) and chip
Two (122) are embedded in the embedding chamber of the chip (114,115), are bonded in solidify afterwards, chip on die bonding layer (117,118)
Electrode court exposes outside, structure as shown in Figure 9；
Solidification described in step S107 is specially and keeps 100 DEG C of 60~80min of temperature-curable time.
S108：Dielectric layer fills making step, and spin coating, standing, front baking, exposure are carried out to described front with photosensitive medium
Light, development, rear baking, form dielectric layer (123) and Filled Dielectrics porous alumina layer (126), expose electrode dielectric through hole
(124,125), are placed in vacuum drying oven and are solidified, structure as shown in Figure 10.
Dielectric layer (123) is made with low-k in front, may act as surface protection film, the layer insulation of chip
Film, Woelm Alumina deep trench filler, enable in particular to solve asking for aluminium base surface planarisation, the bending of improvement substrate or warpage
Topic, meets thin-film technique.Using photosensitive materials such as PI or BCB, dielectric layer (123) thickness is 10~15 μ to dielectric layer (123)
M, dielectric layer time of repose is no less than 1 hour, and the mobility of medium itself can be leaned on to improve flatness, it is ensured that substrate surface is put down
Smoothization.
S109：Chip electrode metal level making step, front sputtering layer of metal, double on positive dielectric layer (123)
Face plating thickeies, and reverse side forms plating thickening layer (129).Front carries out photoresist lithography operations, reverse side spin coating photoresist, solidification
Photoresist diaphragm three (130) is formed, for preventing described plating thickening layer (129) to be corroded, front is rotten using selectivity
Erosion liquid carries out wet etching, and front, reverse side removal photoresist form chip electrode metal level (127,128), so far complete embedding
The making step of chip interconnection package, structure as shown in figure 11.
In the chip electrode metal level (127,128) described in step S109, sputtering membrane system is TiW/Cu film layers, and sputtering is thick
DegreeTiW and thicknessCu；The chip electrode metal level (127,128) is Cu/Ni/
Au metal levels, plating Cu thicknesses of layers is 3~5 μm, and electroplated Ni thicknesses of layers is 5~8 μm, plating Au thicknesses of layers is 0.5~
1.2μm。
Specific embodiment of the invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, those skilled in the art can within the scope of the claims make various deformations or amendments, should all belong to
Protection content of the invention.
Claims (7)
1. a kind of embedding chip interconnection packaging method based on anode oxidation technology, it is characterised in that at least including following step
Suddenly：
S1：Anodic oxidation pre-treatment step, aluminium base (101) is placed in anodic oxidation electrolyte to carry out anodic oxidation and locates in advance
Reason, makes surface form one layer of pellumina (102), to increase substrate surface adhesive force；
S2：Photoresist mask fabrication step against corrosion, the aluminium base (101) after being processed through S1 is divided into tow sides, front
The surface embedding as chip is made, reverse side is used as the surface for making radiation aluminium through post；Photoresist rotation is carried out to described front
Painting, front baking, exposure, development, the rear operation dried, straight-flanked ring photoresist mask (103,104) is formed in the front；To described
Reverse side carries out the same operation of photoresist, and aluminium through post photoresist mask (105) is formed in the reverse side；
S3：Two-sided anodization step, the aluminium base (101) after being processed through S2 is placed in anodic oxidation electrolyte and carries out
Anodic oxidation, anodic oxidation part makes porous alumina layer (107,108), and non-oxidized portion front forms straight-flanked ring aluminium chamber
Body (106), reverse side forms aluminium through post (109), and described porous alumina layer (107,108) thickness is more than chip thickness；
S4：Metal mask making step, removal described straight-flanked ring photoresist mask (103,104) and aluminium through post photoresist mask
(105), the aluminium base (101) is placed in aluminum oxide corrosive liquid and erodes pellumina (102) and the oxidation of partially porous type
Aluminium lamination (107,108), porous alumina layer (107,108) corrosion to front straight-flanked ring aluminium cavity (106) and reverse side
Aluminium through post (109) is highly consistent；
Front sputtering layer of metal layer mask (110) on the aluminium base (101), reverse side sputtering layer of metal layer (111), then
Photoetching offset plate figure mask is formed by photoresist gluing, front baking, exposure, development, rear baking on the metal mask layer (110)
(112), in the reverse side spin coating photoresist of the aluminium base (101), photoresist diaphragm one (113) is solidify to form for preventing
The metal level (111) stated is corroded；
S5：The embedding cavity making step of selective corrosion, using corresponding selective corrosion liquid respectively sequentially to metal mask layer
(110), porous alumina layer (107) carries out wet etching, formed in the straight-flanked ring aluminium chamber (106) the embedding chamber of chip (114,
115)；
S6：Die bonding layer making step, removal described photoetching offset plate figure mask (112) and photoresist diaphragm one (113),
In the reverse side spin coating photoresist of the aluminium base (101), photoresist diaphragm two (116) is solidify to form for preventing described gold
Category layer (111) is corroded, and positive metal mask layer (110) is fallen using selective corrosion corrosion；
Layer of metal is sputtered in the front, plating thickeies, and carry out photoresist spin coating, front baking, exposure, development, the rear behaviour for drying
Make, form embedding cavity photoresist mask (119,120), wet etching is carried out using selective corrosion liquid, remove embedding cavity
Photoresist mask (119,120), forms chip tack coat (117,118)；
S7：The embedding step of chip, removal photoresist diaphragm two (116), with conducting resinl by chip one (121) and chip two
(122) it is embedded in the embedding chamber of the chip (114,115), is bonded in solidify afterwards on die bonding layer (117,118), chip electricity
Pole court exposes outside；
S8：Dielectric layer fill making step, described front is carried out with photosensitive medium spin coating, standing, front baking, exposure, development,
After dry, form dielectric layer (123) and Filled Dielectrics porous alumina layer (126), expose electrode dielectric through hole (124,125),
It is placed in vacuum drying oven and is solidified；
S9：Chip electrode metal level making step, front sputtering layer of metal, two-sided plating on positive dielectric layer (123)
Thicken, reverse side forms plating thickening layer (129)；Front carries out photoresist lithography operations, and reverse side spin coating photoresist solidify to form light
Photoresist diaphragm three (130), for preventing described plating thickening layer (129) to be corroded, front is entered using selective corrosion liquid
Row wet etching, then front, reverse side removal photoresist, form chip electrode metal level (127,128), so far complete embedding chip
The making step of interconnection package.
2. the method for claim 1, it is characterised in that：
Anodic oxidation electrolyte described in step S1, S3 is sulfuric acid or phosphoric acid or chromic acid or oxalic acid；
10~20V of decomposition voltage in step S1；
(103, the 104) internal diameter of straight-flanked ring photoresist mask described in step S2 is set according to chip size, internal diameter external diameter
Difference be set in 0.4~1mm scopes, aluminium through post photoresist mask (105) is with diameter greater than or equal to 0.2mm；
Layer (107, the 108) thickness of porous alumina described in step S3 is bigger than chip thickness 10~20 μm, and decomposition voltage 50~
70V；
Metal mask layer (110) described in step S4 and metal level (111) are TiW/Cu film layers, and thickness is's
TiW and thickness areCu；
Corresponding selective corrosion liquid is described in step S5, S6：The corrosive liquid of TiW is H2O2, Cu corrosive liquids volume ratio proportioning be
HCl:H2O2:H2O=1:3:10, while the volume ratio proportioning of the corrosive liquid of Cu and Ni layers of corrosion is HNO3：H2O=1:1, Au
The mass ratio proportioning of corrosive liquid is I2：KI:H2O=3:20:100；The volume ratio proportioning of Al corrosive liquids is HNO3:H3PO4:
CH3COOH:H2O=1:16:1:2；The mass fraction proportioning of Woelm Alumina corrosive liquid is the mixing of 6% phosphoric acid and 1.8% chromic acid
Liquid；
Die bonding layer (117,118) and chip electrode metal level (126,127) are sputtered film system described in step S6, S7, S9
TiW/Cu film layers, or electrodeposited coating Cu/Ni/Au metal levels；
Solidification described in step S7 is specially and keeps 100 DEG C of 60~80min of temperature-curable time；
Dielectric layer time of repose described in step S8 is no less than 1 hour.
3. the embedding cake core interconnection package structure of aluminium base manufactured by claim 1 methods described, it is characterised in that comprise at least
Aluminium base (101), chip (121,122), dielectric layer (123), chip electrode metal level (126,127)；The chip (121,
122) it is embedded in the aluminium base (101), the filling of groove front of the aluminium base (101) has stated dielectric layer (123), the core
Plate electrode metal level (127,128) is connected on the aluminium base (101) positive dielectric layer (123).
4. structure as claimed in claim 3, it is characterised in that it is many that aluminium base (101) front is additionally provided with Filled Dielectrics
Porous aluminum oxide layer (126), straight-flanked ring aluminium cavity (106), die bonding layer (117,118), reverse side is additionally provided with Woelm Alumina
Layer (108) and aluminium through post (109).
5. structure as claimed in claim 3, it is characterised in that the dielectric layer (123) is PI or BCB, the dielectric layer
(123) thickness is 10~15 μm, and chip electrode metal level (127, the 128) thickness is 3~5 μm.
6. structure as claimed in claim 4, it is characterised in that the porous alumina layer (108) of aluminium base (101) reverse side
Under be set to plating thickening layer (129).
7. the structure as described in claim 4 or 5, it is characterised in that described die bonding layer and chip electrode metal level
(126,127) are the TiW/Cu film layers of sputtered layer, and the wherein thickness of TiW is The thickness of Cu isOr the Cu/Ni/Au metal levels of electrodeposited coating are, the wherein thickness of Cu is 3~5 μm, and the thickness of Ni is 5
~8 μm, the thickness of Au is 0.5~1.2 μm.
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