CN104157580A - Embedded chip interconnecting and packaging method based on aluminum anodizing technology and structure - Google Patents
Embedded chip interconnecting and packaging method based on aluminum anodizing technology and structure Download PDFInfo
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- CN104157580A CN104157580A CN201410395319.9A CN201410395319A CN104157580A CN 104157580 A CN104157580 A CN 104157580A CN 201410395319 A CN201410395319 A CN 201410395319A CN 104157580 A CN104157580 A CN 104157580A
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- 229910052782 aluminium Inorganic materials 0.000 title claims abstract description 100
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 title claims abstract description 100
- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000005516 engineering process Methods 0.000 title claims abstract description 21
- 238000004806 packaging method and process Methods 0.000 title abstract description 4
- 238000007743 anodising Methods 0.000 title abstract 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 75
- 239000002184 metal Substances 0.000 claims abstract description 75
- 238000005260 corrosion Methods 0.000 claims abstract description 54
- 230000007797 corrosion Effects 0.000 claims abstract description 54
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000001259 photo etching Methods 0.000 claims abstract description 14
- 230000005855 radiation Effects 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 99
- 239000004411 aluminium Substances 0.000 claims description 88
- 230000003647 oxidation Effects 0.000 claims description 40
- 238000007254 oxidation reaction Methods 0.000 claims description 40
- 239000007788 liquid Substances 0.000 claims description 39
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 19
- 238000004528 spin coating Methods 0.000 claims description 19
- 238000011161 development Methods 0.000 claims description 16
- 230000008719 thickening Effects 0.000 claims description 15
- 239000003792 electrolyte Substances 0.000 claims description 12
- 238000001039 wet etching Methods 0.000 claims description 11
- 238000012856 packing Methods 0.000 claims description 10
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 claims description 9
- 238000004026 adhesive bonding Methods 0.000 claims description 9
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000007747 plating Methods 0.000 claims description 7
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- KRVSOGSZCMJSLX-UHFFFAOYSA-L chromic acid Substances O[Cr](O)(=O)=O KRVSOGSZCMJSLX-UHFFFAOYSA-L 0.000 claims description 6
- 238000000354 decomposition reaction Methods 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 claims description 6
- AWJWCTOOIBYHON-UHFFFAOYSA-N furo[3,4-b]pyrazine-5,7-dione Chemical compound C1=CN=C2C(=O)OC(=O)C2=N1 AWJWCTOOIBYHON-UHFFFAOYSA-N 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical group O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 229910017604 nitric acid Inorganic materials 0.000 claims description 4
- 239000002253 acid Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 235000006408 oxalic acid Nutrition 0.000 claims description 3
- 238000002203 pretreatment Methods 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 96
- 239000000945 filler Substances 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 3
- 238000005452 bending Methods 0.000 abstract description 2
- 230000004907 flux Effects 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 18
- 239000012528 membrane Substances 0.000 description 12
- 230000008569 process Effects 0.000 description 10
- 235000011007 phosphoric acid Nutrition 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000003292 glue Substances 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000003466 welding Methods 0.000 description 5
- 238000005868 electrolysis reaction Methods 0.000 description 4
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- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 2
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 239000003518 caustics Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004070 electrodeposition Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 239000003049 inorganic solvent Substances 0.000 description 2
- 229910001867 inorganic solvent Inorganic materials 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 150000002739 metals Chemical group 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- 238000000862 absorption spectrum Methods 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- ILRRQNADMUWWFW-UHFFFAOYSA-K aluminium phosphate Chemical compound O1[Al]2OP1(=O)O2 ILRRQNADMUWWFW-UHFFFAOYSA-K 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
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- 229910052799 carbon Inorganic materials 0.000 description 1
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- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
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- 210000004087 cornea Anatomy 0.000 description 1
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- 230000008020 evaporation Effects 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000004021 metal welding Methods 0.000 description 1
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- 230000003287 optical effect Effects 0.000 description 1
- 239000012286 potassium permanganate Substances 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
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- 239000013557 residual solvent Substances 0.000 description 1
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- 230000035945 sensitivity Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- -1 thickness is 3~5 μ m Substances 0.000 description 1
- 230000001988 toxicity Effects 0.000 description 1
- 231100000419 toxicity Toxicity 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to an embedded chip interconnecting and packaging method based on an aluminum anodizing technology and a structure. The method comprises the steps of selecting a low-cost aluminum sheet as a chip embedded substrate, and making a double-face and porous alumina film by the aluminum anodizing technology; obtaining a cavity structure of an embedded chip by utilizing the aluminum chamber protection characteristic of a rectangular ring and the selective corrosion characteristic of the porous alumina film, and finishing the chip coplanar embedment; finishing the interconnection of the embedded chip by the technologies, such as a right side dielectric layer filling photoetching technology, a film metal layer wiring technology, etc. According to the present invention, the positioning precision is high, the size of an embedded cavity matches the chip very well, and the low-cost and coplanar embedment problem of the chips of different sizes is solved effectively. By designing the back side aluminum flux columns, the heat radiation problem of the chip can be solved very well. A dielectric layer having a low dielectric constant can be used as a surface protection film, an interlayer insulation film or a porous alumina depth groove filler of the chip, especially can solve the problems of flattening the surface of an aluminum substrate, improving the bending or warping of the substrate, and satisfies a film technology.
Description
Technical field
The invention belongs to semiconductor packaging field, especially relate to a kind of embedding chip interconnects method based on anode oxidation technology.
Background technology
Embedding chip interconnects technology, is after chip is embedded in substrate or dielectric layer, then unifies to carry out metal line, and the welding zone of chip is connected naturally with wiring metal.Interconnection between this chip welding zone and substrate welding zone belongs to a part for metal line, and interconnection is without the vestige of any " welding ".Embedding chip interconnects also can further improve the reliability of Electronic Assemblies density and electronic product, it is the effective form of one that further realizes three-dimension packaging, it can eliminate all kinds of pads of traditional chip and substrate metal welding zone, and the manufacture process of device does not need scolder, there are a large amount of defects of direct or indirect relation to disappear with scolder and backflow, thereby improve the reliability of electronic product.
Embedding chip interconnects mode mainly contain two kinds, all can be used on organic substrate, ceramic substrate, silicon substrate, metal substrate.One is the embedding method of medium on substrate, can carry out chip by techniques such as medium photoetching, dry etchings embedding, embedding laggard row metalization wiring, the method is had relatively high expectations to dielectric property, is of little use; Another kind is the embedding method of fluting, by in direct chip embedding substrate cavity, the direct contact surface that the method can increase substrate and chip amasss, and a large amount of chip heat is distributed by substrate fast, ensures that the working temperature of chip and whole package assembling is in suitable scope; And substrate direct embedding method provides the environment of a high strength, high-isolation to chip, be conducive to protect chip.This kind of fluting buried inter mode is comparatively common.
Silicon substrate has thermal conductivity high [84W/ (mK)], and the advantage good with chip matched coefficients of thermal expansion degree, becomes the preferred material of fluting buried inter mode.But also there are some problems.Be on the one hand to add man-hour carrying out embedding chip cavity, often adopt dry etching or wet corrosion technique, dry etching positioning precision is high, but high processing cost becomes a large obstacle of producing processing, integrated application in enormous quantities.The inverted trapezoidal structure that silicon substrate wet etching easily forms, inclination angle is 50 °～60 °, corrosion process control precision is poor, causes chip positioning precision lower; The mechanical strength of Si material is low on the other hand, when embedding chip interconnects, can, because of after deposited metal and dielectric layer, produce larger bending and warpage issues, affects product reliability.Therefore need at present a kind of new method badly, address the above problem and cut down finished cost.
Summary of the invention
For solving problems of the prior art, a kind of embedding chip interconnects method for packing and structure based on anode oxidation technology of proposition of the present invention, technical scheme of the present invention is as follows:
Based on an embedding chip interconnects method for packing for anode oxidation technology, at least comprise the following steps:
S1: anodic oxidation pre-treatment step, described aluminium base (101) is placed in to anodic oxidation electrolyte and carries out anodic oxidation preliminary treatment, make surface form one deck pellumina (102), to increase substrate surface adhesive force;
S2: photoresist mask fabrication step against corrosion, will be divided into tow sides through S1 described aluminium base after treatment (101), positive as making the embedding surface of chip, reverse side is as the surface that makes radiation aluminium through post.Described front is carried out to the operation of photoresist spin coating, front baking, exposure, development, rear baking, at the described positive straight-flanked ring photoresist mask (103,104) that forms; Described reverse side is carried out to the same operation of photoresist, form aluminium through post photoresist mask (105) at described reverse side;
S3: two-sided anodic oxidation step, to be placed in anodic oxidation electrolyte through S2 described aluminium base after treatment (101) and carry out anodic oxidation, anodic oxidation part is made porous alumina layer (107,108), the not positive straight-flanked ring aluminium cavity (106) that forms of oxidized portion, reverse side forms aluminium through post (109), and described porous alumina layer (107,108) thickness is greater than chip thickness;
S4: metal mask making step, remove described straight-flanked ring photoresist mask (103,104) and aluminium through post photoresist mask (105), described aluminium base (101) is placed in to aluminium oxide corrosive liquid and erodes pellumina (102) and partially porous type alumina layer (107,108), described porous alumina layer (107,108) corrosion is to highly consistent with front straight-flanked ring aluminium cavity (106) and reverse side aluminium through post (109);
At the upper positive sputter layer of metal layer mask (110) of described aluminium base (101), reverse side sputter layer of metal layer (111), upper by photoresist gluing, front baking, exposure, development, rear baking formation photoetching offset plate figure mask (112) at described metal mask layer (110) again, at the reverse side spin coating photoresist of described aluminium base (101), solidify to form photoresist diaphragm one (113) and be corroded for preventing described metal level (111);
S5: the embedding cavity making step of selective corrosion, adopt corresponding selective corrosion liquid sequentially metal mask layer (110), porous alumina layer (107) to be carried out to wet etching respectively, in straight-flanked ring aluminium chamber (106), form the embedding chamber of chip (114,115);
S6: die bonding layer making step, remove described photoetching offset plate figure mask (112) and photoresist diaphragm one (113), at the reverse side spin coating photoresist of described aluminium base (101), solidify to form photoresist diaphragm two (116) and be corroded for preventing described metal level (111), adopt selective corrosion corrosion to fall positive metal mask layer (110);
In described positive sputter layer of metal, electroplate thickening, and carry out the operation of photoresist spin coating, front baking, exposure, development, rear baking, form embedding cavity photoresist mask (119,120), adopt selective corrosion liquid to carry out wet etching, remove embedding cavity photoresist mask (119,120), form chip attach layer (117,118);
S7: the embedding step of chip, remove photoresist diaphragm two (116), chip one (121) and chip two (122) are embedded in to the embedding chamber (114 of described chip with conducting resinl, 115) in, be bonded in die bonding layer (117,118) upper rear solidifying, chip electrode is towards exposing outside;
S8: dielectric layer is filled making step, with photosensitive medium to described front carry out spin coating, leave standstill, front baking, exposure, development, rear baking, form dielectric layer (123) and Filled Dielectrics porous alumina layer (126), expose electrode dielectric layer through hole (124,125), being placed in vacuum furnace is cured;
S9: chip electrode metal level making step, in the upper positive sputter layer of metal of positive dielectric layer (123), two-sided plating thickening, reverse side forms electroplates thickening layer (129).Photoresist lithography operations is carried out in front; reverse side spin coating photoresist; solidify to form photoresist diaphragm three (130); for preventing that described plating thickening layer (129) is corroded; the positive selective corrosion liquid that adopts carries out wet etching, more positive, reverse side removal photoresist, forms chip electrode metal level (127; 128), so far complete the making of embedding chip interconnects method for packing.
Further,
Anodic oxidation electrolyte described in step S1, S3 is the acid class electrolyte such as sulfuric acid, phosphoric acid, chromic acid or oxalic acid;
Decomposition voltage 10～20V in step S1;
The photoresist of straight-flanked ring described in step S2 mask (103,104) internal diameter arranges according to chip size, and the difference of internal diameter external diameter is set in 0.4～1mm scope, and aluminium through post photoresist mask (105) diameter is more than or equal to 0.2mm;
Large 10～20 μ m of the layer of porous alumina described in step S3 (107,108) Thickness Ratio chip thickness, decomposition voltage 50～70V;
Metal mask layer described in step S4 (110) and metal level (111) are TiW/Cu rete, and thickness is
tiW and thickness be
cu;
Selective corrosion liquid corresponding described in step S5, S6 is: the corrosive liquid of TiW is H2O2, Cu corrosive liquid proportioning (volume ratio) is HCl:H2O2:H2O=1:3:10, the corrosive liquid proportioning (volume ratio) of simultaneously corroding Cu and Ni layer is HNO3:H2O=1:1, and the corrosive liquid proportioning (mass ratio) of Au is I2:KI:H2O=3:20:100; Al corrosive liquid proportioning (volume ratio) is HNO3:H3PO4:CH3COOH:H2O=1:16:1:2; Woelm Alumina corrosive liquid proportioning (mass fraction) is the mixed liquor of 6% phosphoric acid and 1.8% chromic acid;
Die bonding layer (117,118) and chip electrode metal level (126,127) described in step S6, S7, S9, its sputtered film system is TiW/Cu rete, and electrodeposited coating is Cu/Ni/Au metal level.
Described in step S7, solidify to be specially and keep 100 DEG C of temperature-curable time 60～80min;
Dielectric layer time of repose described in step S8 is no less than 1 hour;
The aluminium base embedded type chip interconnects encapsulating structure of being manufactured by described method, at least comprises aluminium base (101), chip (121,122), dielectric layer (123), chip electrode metal level (126,127); Described chip (121,122) be embedded in described aluminium base (101), the front of described aluminium base (101) is filled with described dielectric layer (123), described chip electrode metal level (127,128) is connected on the positive dielectric layer (123) of described aluminium base (101).
Further, described aluminium base (101) front is also provided with Filled Dielectrics porous alumina layer (126), straight-flanked ring aluminium cavity (106), die bonding layer (117,118), and reverse side is also provided with porous alumina layer (108) and aluminium through post (109).
Further, described dielectric layer (123) is PI or BCB, and described dielectric layer (123) thickness is 10～15 μ m, and described chip electrode metal level (127,128) thickness is 3～5 μ m.
Further, under the porous alumina layer (108) of described aluminium base (101) reverse side, be set to electroplate thickening layer (129).
Further, in described die bonding layer and chip electrode metal level (126,127), its sputtered layer is thickness
tiW and thickness
cu; Electroplate rete and be the Cu that thickness is 3～5 μ m, thickness is the Ni of 5～8 μ m, and thickness is the Au of 0.5～1.2 μ m.
The present invention has following beneficial effect:
Embedding chip interconnects method for packing and structure based on anode oxidation technology of the present invention, adopts aluminum as substrate substrate, the advantage such as have thermal conductivity high [being greater than 150W/ (mK)], cost is low, Woelm Alumina thermal coefficient of expansion is adjustable.Based on anode oxidation technology, utilize the protection of straight-flanked ring metallic aluminium chamber, and the characteristic of porous alumina film selective corrosion, positioning precision can be made high, and the better chip embedding structure of embedding chamber size and chip matching, efficient solution, never with the coplanar embedding problem of low-cost and high-precision of chip size, has improved the precision of chip positioning; And utilize aluminium through post can solve well chip cooling problem; Utilize the liquid state of low-k or gum polymers as dielectric layer; can serve as surface protection film, interlayer dielectric, the Woelm Alumina deep trench filler of chip; be particularly advantageous in aluminium base flattening surface, improved the problem of curved substrate or warpage; meet thin-film technique, improved the reliability of chip interconnects, inter-level interconnects.
The embedding chip interconnects method that the present invention takes, by existing technology, optimizes and promotes a little, can realize multilayer wiring interconnection structure, and can also upside-down mounting welding core on multilayer interconnect structure or surface element device, realizes the functionalization of module.
Brief description of the drawings
Fig. 1-Figure 12 is embedding chip interconnects method for packing implementation step and the counter structure based on anode oxidation technology;
Figure 13 is the wafer vertical view of front straight-flanked ring aluminium cavity after the two-sided anodic oxidation of aluminium base;
Figure 14 is the wafer vertical view of reverse side aluminium through post after the two-sided anodic oxidation of aluminium base;
Figure 15 is the embedding chip interconnects method for packing implementation step flow chart based on anode oxidation technology.
In figure, be denoted as:
101: at the bottom of metal aluminum based; 102: pellumina; 103,104: straight-flanked ring photoresist mask; 105: aluminium through post photoresist mask; 106: straight-flanked ring aluminium cavity; 107,108: porous alumina layer; 109: aluminium through post; 110: metal mask layer; 111: metal level; 112: photoetching offset plate figure mask; 113: photoresist diaphragm one; 114:115: the embedding chamber of chip; 116: photoresist diaphragm two; 117,118: die bonding layer; 119,120: embedding cavity photoresist mask; 121: chip one; 122: chip two; 123: dielectric layer; 124,125: dielectric layer through hole; 126: Filled Dielectrics porous alumina layer; 127,128: chip electrode metal level; 129: metal thickening layer; 130: photoresist diaphragm three.
Embodiment
Below in conjunction with accompanying drawing, in the mode of specific embodiment, the present invention is described in detail.Following examples will contribute to those skilled in the art further to understand the present invention, but not limit in any form the present invention.It should be pointed out that to those skilled in the art, without departing from the inventive concept of the premise, can also make some distortion and improvement.These all belong to protection scope of the present invention.
Embedding chip interconnects method for packing and silica-based embedded chip interconnects of the prior art based on anode oxidation technology of the present invention all needs to use the processing method of photoetching.In the course of processing of current silica-based embedded chip interconnects, all will relate to repeatedly photo-etching technological process, although the object of each photoetching requires and process conditions difference to some extent, its technical process is essentially identical.Photoetching process generally all will be passed through spin coating, front baking, and exposure, develops, and post bake (afterwards dry) such as corrodes and remove photoresist at seven steps:
1, gluing: gluing is exactly at SIO
2or other film substrate surfaces, coating one deck adheres to good, and thickness is suitable, the uniform photoresist film of thickness.Before gluing, be preferably in gluing immediately after oxidation or evaporation, now substrate surface is clean dry, and the adhesiveness of photoresist is better.Gluing generally adopts rotary process, and its principle is to utilize the centrifugal force producing while rotation, and the unnecessary glue that drops in substrate is got rid of, and under photoresist surface tension and rotary centrifugal force acting in conjunction, is extended to the glued membrane of even thickness.Film thickness can regulate by the concentration of rotating speed and glue.The thickness of gluing is wanted suitably, and uniform film thickness adheres to good.Glued membrane is too thin, and pin hole is many, and resistance to corrosion is poor; Glued membrane is too thick, and resolution is low.In the ordinary course of things, distinguishable live width is about 5～8 times of thickness.
2, front baking: front baking is exactly at a certain temperature, evaporates the solvent in glued membrane lentamente, makes glued membrane dry, and increases its adhesiveness and resistance to wear.With the kind of glue and the difference of thickness and to some extent difference of the temperature and time of front baking, generally comes to be determined by experiment.The temperature and time of front baking must be suitably.Excess Temperature can cause the heat cross-linking of resist, in the time developing, leaves counterdie, or sensitizer distillation volatilization declines luminous sensitivity; Pre-bake temperature is too low or the time is too short, and the organic solvent in resist can not fully volatilize, and residual solvent molecule can hinder the reaction of light interlinkage, thereby causes pinhold density to increase, floating glue or figure deformation etc.Meanwhile, can't be shock heating when front baking, in order to avoid cause surface blisters, produce the even floating glue of pin hole.General front baking is to toast 10-15 minute in 80 DEG C of thermostatic drying chambers; Also can toast at substrate back with hot platform, make being dried from the inside to surface of glued membrane, to obtain good front baking effect.
3, exposure: exposure is carried out selective light chemical reaction to the substrate that scribbles photoresist with exactlying, the dissolubility of the photoresist that makes exposed portion in developer solution changes, and after development, obtains the figure corresponding with mask plate on photoresist film.In production, conventionally all adopt ultraviolet light contact exposure method, its basic step is that location is aimed at and exposure.It is figure and the accurate fit of on-chip figure that makes mask plate that location is aimed at, and therefore requires mask aligner to have good alignment device, has accurate fine setting and hold-down mechanism, particularly in the time compressing, ensures that accurate fit is not subjected to displacement.In addition, mask aligner also should have suitable optical viewing system, and requiring has a depth of field larger, has again enough high-resolution microscopes simultaneously.The selection of exposure is decided by the absorption spectrum of photoresist, proportioning, the spectral distribution of thickness and light source.Determining of optimum exposure, also will consider the reflective character of substrate.In actual production, often control exposure with the time for exposure, and carry out by experiment to determine optimum exposure time.
4, development: development is that the substrate after exposure is placed in suitable solvent, the photoresist film that should remove is molten except clean, the protection figure of needed resist film while corrosion to obtain.
5, post bake (afterwards dry): post bake cries again rear baking, is at a certain temperature the silicon chip after developing to be cured, and removes developer solution that while development, glued membrane absorbs and residual moisture content, improves the adhesiveness of glued membrane and silicon chip, the resistance to corrosion of enhancing cornea.The temperature and time of post bake is wanted suitably.Post bake deficiency, resist glued membrane does not dry, film and substrate poor adhesion, easily floating glue when corrosion; Post bake excess Temperature, resist glued membrane can or peel off because of thermal expansion warpage, can produce equally undercutting or floating glue when corrosion.When temperature is higher, polymer will decompose, and affect adhesiveness and resistance to corrosion.In addition, preferably adopt slow intensification and the naturally cooling process of curing when post bake.The thick film etching of growing for etching time can be carried out post bake one time, to improve the resistance to corrosion of glued membrane after corrosion half again.
6, corrosion: corrosion is exactly with suitable corrosive agent, to the SiO not covered by photoresist film
2or other films corrode, complete to obtain, clear, litho pattern accurately, reaches the object of selectivity diffusion or metal line.Photoetching process to the requirement of corrosive agent is: a material of only needs being removed corrodes, and to resist glued membrane do not corrode or etching extent very little.Meanwhile, also require corrosion factor to want enough large.The definition of corrosion factor is corrosion depth and the ratio of the lateral encroaching amount of a side.Corrosion factor is larger, represents that lateral encroaching amount is less.In addition, also require etch pattern neat in edge, clear; Corrosive liquid toxicity is little, easy to use.
For the corrosion of aluminium, conventional corrosive liquid has phosphoric acid and potassium permanganate corrosive liquid at present.For phosphoric acid, be to utilize it and reactive aluminum can generate water-soluble acid aluminum phosphate, to reach the object of corrosion, its reaction equation is: 2Al+6H
3pO
4=2Al (H
2pO
4)
3+ 3H
2.From reaction equation, can find out, when corrosion, reaction fierceness, has bubble and constantly emerges, the uniformity of impact corrosion.For this reason, a small amount of absolute ethyl alcohol be can in corrosive liquid, add or ultrasonic vibration, the bubble generating to remove reaction in the time of corrosion, adopted.
7, remove photoresist: no longer needed photoresist to make protective layer completing after corrosion, can be removed.The method of removing photoresist often has wet method to remove photoresist and dry method two classes of removing photoresist:
(a) wet method is removed photoresist
1. organic solvent removes photoresist: utilize organic solvent to remove photoresist;
2. inorganic solvent: by using some inorganic solvents, the carbon in this photoresist organic substance is oxidized to carbon dioxide, and then and be removed;
(b) dry method is removed photoresist: utilize plasma that photoresist is divested.
Plating is exactly to utilize electrolysis principle on some metal surface, to plate the process of other metal or alloy of one deck thin layer, play and prevent burning, improve resistance to wear, conductivity, the effects such as corrosion resistance, the metallization of substrate generally adopts electroplates Cu/Ni/Au electrodeposition of metals, electrodeposition of metals Cu/Ni/Au film is that thickness need meet certain limit, general Cu is adhesion layer, thickness is 3～5 μ m, Ni is as barrier layer, can stop the diffusion of Cu and Au, thickness is 5～8 μ m, Au takes body layer as the leading factor, there is good solderability, conductivity, corrosion resistance and non-oxidizability, thickness is 0.5～1.2 μ m.
For embedding chip interconnects method for packing implementation step and counter structure Figure 14 based on anode oxidation technology are method step flow chart, the operating process that Fig. 1-Figure 11 is corresponding is as follows as Figure 1-Figure 11:
S101: anodic oxidation pre-treatment step, described aluminium base (101) is placed in to anodic oxidation electrolyte and carries out anodic oxidation preliminary treatment, make surface form one deck pellumina (102), to increase substrate surface adhesive force, structure as shown in Figure 1.
Compared with the silicon substrate of current employing, the present invention uses aluminum as substrate, has the advantages such as thermal conductivity is high, cost is low, Woelm Alumina thermal coefficient of expansion is adjustable.
Aluminium base (101) material is generally selected fine aluminium Al1060 material, and thermal conductivity is 217W/ (mK).The aluminium base of 0.3mm (101) is carried out to surface finish with chemistry or mechanical method to aluminum, clean to remove surface and oil contaminant and impurity with acetone, ethanolic solution again, be placed in as the phosphoric acid of anodic oxidation electrolyte and carry out pre-oxidation, obtain one deck pellumina (102), this pellumina can increase substrate surface adhesive force.Wherein, the spendable anodic oxidation electrolyte of the present invention is not limited to the phosphoric acid of the present embodiment, can also use the acidic electrolysis baths such as sulfuric acid, chromic acid or oxalic acid, decomposition voltage of the present invention and electrolysis time are also not limited to the present embodiment, decomposition voltage setting range is 10～20V, and electrolysis time setting range is 5～20min.
S102: photoresist mask fabrication step against corrosion, will be divided into tow sides through S101 described aluminium base after treatment (101), positive as making the embedding surface of chip, reverse side is as the surface that makes radiation aluminium through post.Described front is carried out to the operation of photoresist spin coating, front baking, exposure, development, rear baking, at the described positive straight-flanked ring photoresist mask (103,104) that forms; Described reverse side is carried out to the same operation of photoresist, form aluminium through post photoresist mask (105), structure as shown in Figure 2 at described reverse side;
Wherein, straight-flanked ring photoresist mask (103,104) mark presets position and the shape of the straight-flanked ring aluminium cavity (106) of manufacturing, and aluminium through post photoresist mask (105) mark presets position and the shape of the aluminium through post (109) that will manufacture.The embedding chamber of the corresponding chip of straight-flanked ring aluminium cavity (106) (114,115), for embedding chip (121,122); Aluminium through post (109) can be used for aluminium base heat radiation.Straight-flanked ring photoresist mask (103,104) inside diameter ranges for) internal diameter arranges according to chip size, the difference of internal diameter external diameter is set in 0.4～1mm scope, aluminium through post photoresist mask (105) diameter is more than or equal to 0.2mm.
S103: two-sided anodic oxidation step, to be placed in anodic oxidation electrolyte through S102 described aluminium base after treatment (101) and carry out anodic oxidation, anodic oxidation part is made porous alumina layer (107,108), the not positive straight-flanked ring aluminium cavity (106) that forms of oxidized portion, reverse side forms aluminium through post (109), described porous alumina layer (107,108) thickness is greater than chip thickness, form structure as shown in Figure 3, positive and negative wafer vertical view is now shown in Figure 13 and Figure 14.
S104: metal mask making step, remove described straight-flanked ring photoresist mask (103,104) and aluminium through post photoresist mask (105), described aluminium base (101) is placed in to aluminium oxide corrosive liquid and erodes pellumina (102) and partially porous type alumina layer (107,108), described porous alumina layer (107,108) corrosion, to highly consistent with front straight-flanked ring aluminium cavity (106) and reverse side aluminium through post (109), forms structure as shown in Figure 4.The present embodiment step 104 etching time is set as 20min, but the invention is not restricted to the present embodiment, and the time is set in 10～30min scope.
At the upper positive sputter layer of metal layer mask (110) of described aluminium base (101), reverse side sputter layer of metal layer (111), forms structure as shown in Figure 5.Upper by photoresist gluing, front baking, exposure, development, rear baking formation photoetching offset plate figure mask (112) at described metal mask layer (110) again; at the reverse side spin coating photoresist of described aluminium base (101); solidify to form photoresist diaphragm one (113) and be corroded for preventing described metal level (111), form structure as shown in Figure 6.
In the present embodiment, photoresist diaphragm one (113) also can adopt anticorrosion adhesive tape, and protection reverse side metal level (111) is not corroded in the time that corrosion is positive, and also conveniently tears in the time that needs are removed.Metal mask layer (110) and metal level (111) are TiW/Cu rete, and thickness is
tiW and thickness be
cu;
S105: the embedding cavity making step of selective corrosion, adopt corresponding selective corrosion liquid sequentially metal mask layer (110), porous alumina layer (107) to be carried out to wet etching respectively, in straight-flanked ring aluminium chamber (106), form the embedding chamber (114 of chip, 115), structure as shown in Figure 7.
Wherein, described in the present embodiment, corresponding selective corrosion liquid is respectively: the corrosive liquid of TiW is H
2o
2, Cu corrosive liquid proportioning (volume ratio) is HCl:H
2o
2: H
2o=1:3:10, the corrosive liquid proportioning (volume ratio) of simultaneously corroding Cu and Ni layer is HNO3:H2O=1:1, the corrosive liquid proportioning (mass ratio) of Au is I2:KI:H2O=3:20:100; Al corrosive liquid proportioning (volume ratio) HNO
3: H
3pO
4: CH
3cOOH:H
2o=1:16:1:2; Woelm Alumina corrosive liquid proportioning (mass fraction) is the mixed liquor of 6% phosphoric acid and 1.8% chromic acid; The corrosive liquid that pellumina (102), porous alumina layer (107,108) use is identical.The size in the embedding chamber of chip (114,115) coordinates with required embedding chip, and the Qiang Bi inclination angle, embedding chamber going out due to aluminium base wet etching is generally greater than 80 °, has good matching degree with chip form.In the time that chip is embedding, than using silicon substrate can obtain location more accurately.
S106: die bonding layer making step; remove described photoetching offset plate figure mask (112) and photoresist diaphragm one (113); at the reverse side spin coating photoresist of described aluminium base (101); solidify to form photoresist diaphragm two (116) and be corroded for preventing described metal level (111), adopt selective corrosion corrosion to fall positive metal mask layer (110).
In described positive sputter layer of metal, electroplate thickening, and carry out the operation of photoresist spin coating, front baking, exposure, development, rear baking, form embedding cavity photoresist mask (119,120), adopt selective corrosion liquid to carry out after wet etching, form structure as shown in Figure 8.Remove embedding cavity photoresist mask (119,120), form chip attach layer (117,118).
Described step S106 chips adhesive linkage (117,118) sputtered film is TiW/Cu rete, sputter thickness
tiW and thickness
cu; Described die bonding layer (117,118) electrodeposited coating is Cu/Ni/Au metal level, and electroplating Cu thicknesses of layers is 3～5 μ m, and electroplated Ni thicknesses of layers is 5～8 μ m, and electroplating Au thicknesses of layers is 0.5～1.2 μ m.
S107: the embedding step of chip, remove photoresist diaphragm two (116), chip one (121) and chip two (122) are embedded in to the embedding chamber (114 of described chip with conducting resinl, 115) in, be bonded in die bonding layer (117,118) upper rear solidifying, chip electrode court exposes outside, structure as shown in Figure 9;
Described in step S107, solidify to be specially and keep 100 DEG C of temperature-curable time 60～80min.
S108: dielectric layer is filled making step, with photosensitive medium to described front carry out spin coating, leave standstill, front baking, exposure, development, rear baking, form dielectric layer (123) and Filled Dielectrics porous alumina layer (126), expose electrode dielectric layer through hole (124,125), be placed in vacuum furnace and be cured, structure as shown in figure 10.
Make dielectric layer (123) in front and there is low-k; can serve as surface protection film, interlayer dielectric, the Woelm Alumina deep trench filler of chip; especially can solve aluminium base flattening surface, improve the problem of curved substrate or warpage, meet thin-film technique.Dielectric layer (123) adopts the photosensitive materials such as PI or BCB, described dielectric layer (123) thickness is 10～15 μ m, dielectric layer time of repose is no less than 1 hour, can lean on the mobility of medium self to improve evenness, ensures substrate surface planarization.
S109: chip electrode metal level making step, in the upper positive sputter layer of metal of positive dielectric layer (123), two-sided plating thickening, reverse side forms electroplates thickening layer (129).Photoresist lithography operations is carried out in front; reverse side spin coating photoresist; solidify to form photoresist diaphragm three (130); for preventing that described plating thickening layer (129) is corroded, the positive selective corrosion liquid that adopts carries out wet etching, and positive, reverse side is removed photoresist; form chip electrode metal level (127; 128), so far complete the making step of embedding chip interconnects encapsulation, structure as shown in figure 11.
Described in step S109, in described chip electrode metal level (127,128), sputtered film is TiW/Cu rete, sputter thickness
tiW and thickness
cu; Described chip electrode metal level (127,128) is Cu/Ni/Au metal level, and electroplating Cu thicknesses of layers is 3～5 μ m, and electroplated Ni thicknesses of layers is 5～8 μ m, and electroplating Au thicknesses of layers is 0.5～1.2 μ m.
Above specific embodiments of the invention are described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and those skilled in the art can make various distortion or amendment within the scope of the claims, all should belong to protection content of the present invention.
Claims (7)
1. the embedding chip interconnects method for packing based on anode oxidation technology, is characterized in that, at least comprises the following steps:
S1: anodic oxidation pre-treatment step, described aluminium base (101) is placed in to anodic oxidation electrolyte and carries out anodic oxidation preliminary treatment, make surface form one deck pellumina (102), to increase substrate surface adhesive force;
S2: photoresist mask fabrication step against corrosion, will be divided into tow sides through S1 described aluminium base after treatment (101), positive as making the embedding surface of chip, reverse side is as the surface that makes radiation aluminium through post; Described front is carried out to the operation of photoresist spin coating, front baking, exposure, development, rear baking, at the described positive straight-flanked ring photoresist mask (103,104) that forms; Described reverse side is carried out to the same operation of photoresist, form aluminium through post photoresist mask (105) at described reverse side;
S3: two-sided anodic oxidation step, to be placed in anodic oxidation electrolyte through S2 described aluminium base after treatment (101) and carry out anodic oxidation, anodic oxidation part is made porous alumina layer (107,108), the not positive straight-flanked ring aluminium cavity (106) that forms of oxidized portion, reverse side forms aluminium through post (109), and described porous alumina layer (107,108) thickness is greater than chip thickness;
S4: metal mask making step, remove described straight-flanked ring photoresist mask (103,104) and aluminium through post photoresist mask (105), described aluminium base (101) is placed in to aluminium oxide corrosive liquid and erodes pellumina (102) and partially porous type alumina layer (107,108), described porous alumina layer (107,108) corrosion is to highly consistent with front straight-flanked ring aluminium cavity (106) and reverse side aluminium through post (109);
At the upper positive sputter layer of metal layer mask (110) of described aluminium base (101), reverse side sputter layer of metal layer (111), upper by photoresist gluing, front baking, exposure, development, rear baking formation photoetching offset plate figure mask (112) at described metal mask layer (110) again, at the reverse side spin coating photoresist of described aluminium base (101), solidify to form photoresist diaphragm one (113) and be corroded for preventing described metal level (111);
S5: the embedding cavity making step of selective corrosion, adopt corresponding selective corrosion liquid sequentially metal mask layer (110), porous alumina layer (107) to be carried out to wet etching respectively, in straight-flanked ring aluminium chamber (106), form the embedding chamber of chip (114,115);
S6: die bonding layer making step, remove described photoetching offset plate figure mask (112) and photoresist diaphragm one (113), at the reverse side spin coating photoresist of described aluminium base (101), solidify to form photoresist diaphragm two (116) and be corroded for preventing described metal level (111), adopt selective corrosion corrosion to fall positive metal mask layer (110);
In described positive sputter layer of metal, electroplate thickening, and carry out the operation of photoresist spin coating, front baking, exposure, development, rear baking, form embedding cavity photoresist mask (119,120), adopt selective corrosion liquid to carry out wet etching, remove embedding cavity photoresist mask (119,120), form chip attach layer (117,118);
S7: the embedding step of chip, remove photoresist diaphragm two (116), chip one (121) and chip two (122) are embedded in to the embedding chamber (114 of described chip with conducting resinl, 115) in, be bonded in die bonding layer (117,118) upper rear solidifying, chip electrode is towards exposing outside;
S8: dielectric layer is filled making step, with photosensitive medium to described front carry out spin coating, leave standstill, front baking, exposure, development, rear baking, form dielectric layer (123) and Filled Dielectrics porous alumina layer (126), expose electrode dielectric layer through hole (124,125), being placed in vacuum furnace is cured;
S9: chip electrode metal level making step, in the upper positive sputter layer of metal of positive dielectric layer (123), two-sided plating thickening, reverse side forms electroplates thickening layer (129); Photoresist lithography operations is carried out in front; reverse side spin coating photoresist; solidify to form photoresist diaphragm three (130); for preventing that described plating thickening layer (129) is corroded; the positive selective corrosion liquid that adopts carries out wet etching, more positive, reverse side removal photoresist, forms chip electrode metal level (127; 128), so far complete the making step of embedding chip interconnects encapsulation.
2. the method for claim 1, is characterized in that:
Anodic oxidation electrolyte described in step S1, S3 is the acid class electrolyte such as sulfuric acid, phosphoric acid, chromic acid or oxalic acid;
Decomposition voltage 10～20V in step S1;
The photoresist of straight-flanked ring described in step S2 mask (103,104) internal diameter arranges according to chip size, and the difference of internal diameter external diameter is set in 0.4～1mm scope, and aluminium through post photoresist mask (105) diameter is more than or equal to 0.2mm;
Large 10～20 μ m of the layer of porous alumina described in step S3 (107,108) Thickness Ratio chip thickness, decomposition voltage 50～70V;
Metal mask layer described in step S4 (110) and metal level (111) are TiW/Cu rete, and thickness is
tiW and thickness be
cu;
Selective corrosion liquid corresponding described in step S5, S6 is: the corrosive liquid of TiW is H
2o
2, Cu corrosive liquid proportioning (volume ratio) is HCl:H
2o
2: H
2o=1:3:10, the corrosive liquid proportioning (volume ratio) of simultaneously corroding Cu and Ni layer is HNO3:H2O=1:1, the corrosive liquid proportioning (mass ratio) of Au is I2:KI:H2O=3:20:100; Al corrosive liquid proportioning (volume ratio) is HNO
3: H
3pO
4: CH
3cOOH:H
2o=1:16:1:2; Woelm Alumina corrosive liquid proportioning (mass fraction) is the mixed liquor of 6% phosphoric acid and 1.8% chromic acid;
Die bonding layer (117,118) and chip electrode metal level (126,127) described in step S6, S7, S9, its sputtered film system is TiW/Cu rete, and electrodeposited coating is Cu/Ni/Au metal level;
Described in step S7, solidify to be specially and keep 100 DEG C of temperature-curable time 60～80min;
Dielectric layer time of repose described in step S8 is no less than 1 hour.
3. the aluminium base embedded type chip interconnects encapsulating structure of being manufactured by method described in claim 1, it is characterized in that, at least comprise aluminium base (101), chip (121,122), dielectric layer (123), chip electrode metal level (126,127); Described chip (121,122) be embedded in described aluminium base (101), the front of described aluminium base (101) is filled with described dielectric layer (123), described chip electrode metal level (127,128) is connected on the positive dielectric layer (123) of described aluminium base (101).
4. structure as claimed in claim 3, it is characterized in that, described aluminium base (101) front is also provided with Filled Dielectrics porous alumina layer (126), straight-flanked ring aluminium cavity (106), die bonding layer (117,118), and reverse side is also provided with porous alumina layer (108) and aluminium through post (109).
5. structure as claimed in claim 3, it is characterized in that, described dielectric layer (123) is PI or BCB, and described dielectric layer (123) thickness is 10～15 μ m, described chip electrode metal level (127,128) thickness is 3～5 μ m.
6. structure as claimed in claim 4, is characterized in that, under the porous alumina layer (108) of described aluminium base (101) reverse side, is set to electroplate thickening layer (129).
7. the structure as described in claim 4 and 5, is characterized in that, in described die bonding layer and chip electrode metal level (126,127), its sputtered layer is thickness
tiW and thickness
cu; Electroplate rete and be the Cu that thickness is 3～5 μ m, thickness is the Ni of 5～8 μ m, and thickness is the Au of 0.5～1.2 μ m.
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| CN105021303B (en) * | 2015-07-15 | 2018-04-17 | 哈尔滨工程大学 | A kind of manufacturing method of temperature sensor of aluminium base sensitive material |
| CN105118815A (en) * | 2015-08-13 | 2015-12-02 | 上海航天测控通信研究所 | Vertical interconnection structure for three-dimensional package based on aluminum substrates and preparation method thereof |
| CN105118815B (en) * | 2015-08-13 | 2017-09-29 | 上海航天电子通讯设备研究所 | A kind of three-dimension packaging vertical interconnecting structure based on aluminium base and preparation method thereof |
| CN105244313A (en) * | 2015-09-08 | 2016-01-13 | 上海航天测控通信研究所 | Interconnection manufacturing method for film through holes in substrate |
| CN108598007A (en) * | 2018-01-16 | 2018-09-28 | 安徽省祁门县黄山电器有限责任公司 | A kind of method of aluminium oxide or aluminium nitride ceramic substrate surface metalation |
| CN109930153A (en) * | 2019-04-24 | 2019-06-25 | 深圳市华星光电技术有限公司 | Etching liquid and etching device |
| CN111987010A (en) * | 2019-05-21 | 2020-11-24 | 上海航天电子通讯设备研究所 | Automatic eutectic welding method for power chip and picking suction head |
| US20210370643A1 (en) * | 2020-05-27 | 2021-12-02 | Metal Industries Research & Development Centre | Multilayer plate with composite material and method for manufacturing the same |
| US11766847B2 (en) * | 2020-05-27 | 2023-09-26 | Metal Industries Research & Development Centre | Multilayer plate with composite material and method for manufacturing the same |
| CN113881941A (en) * | 2021-11-15 | 2022-01-04 | 广州聚利笙科技有限公司 | Anodic aluminum oxide nano microarray chip based on MEMS and preparation process and application thereof |
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