CN104156325B - Conversion method and device of the chip logic address to physical address - Google Patents
Conversion method and device of the chip logic address to physical address Download PDFInfo
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- CN104156325B CN104156325B CN201410425355.5A CN201410425355A CN104156325B CN 104156325 B CN104156325 B CN 104156325B CN 201410425355 A CN201410425355 A CN 201410425355A CN 104156325 B CN104156325 B CN 104156325B
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Abstract
A kind of chip logic address to physical address conversion method and device, wherein, method includes：Failed areas is chosen on chip；Damage inactivation region；Failed areas is detected, obtains the logical address of fail bit memory cell in failed areas；According to the transformational relation of default logical address to physical address, Theoretical Physics address corresponding to the logical address of fail bit memory cell is obtained；Physical failure analysis is made to chip, by the Theoretical Physics address of fail bit memory cell compared with the physical location of failed areas, obtains Theoretical Physics address to the deviant of physical location；According to deviant, the logical address of chip is obtained to the transformational relation of physical address.By methods described and device, can solve the problems, such as that logical address is low and transforming mistakes be present to actual physical address efficiency in the prior art.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of chip logic address is to the conversion method of physical address
And device.
Background technology
, it is necessary to will be deposited in IC chip in chip secure perils detecting, chip reverse engineering or failure analysis
The logical address of storage unit or module and actual physical address are done conversion and confirmed, including array, module, sector, input are defeated
Go out the confirmation of unit, wordline, bit line, dummy word line, dummy etc., could then complete follow-up chip security detection,
Circuit function confirms or the work of failure analysis.
At present, typically technical staff is by studying circuit design or domain, so as to be extrapolated by logical address
Actual physical address.
But above method the problem of existing, has：(1) for the reason for the intellectual property protection, under many circumstances, it is difficult to
Get complete circuit design；(2) polytropy of layout design, even same layout design person, is typically due to
Reason, its design such as the design requirement of client, area limitation are also not quite similar.Therefore logical address is realized according to the above method
To the conversion of actual physical address, efficiency to be present low, defines the problem of difficult, and due to deviation be present, be also easy to cause to change
Error, influences subsequent treatment.
The content of the invention
The embodiment of the present invention solve the problems, such as be how to solve in the prior art logical address to actual physical address efficiency
It is low and the problem of transforming mistakes be present.
To solve the above problems, the embodiment of the present invention provides a kind of conversion method of chip logic address to physical address,
Methods described includes：Failed areas is chosen on the chip；Destroy the failed areas；The failed areas is detected, is obtained
The logical address of fail bit memory cell in the failed areas；Closed according to the conversion of default logical address to physical address
System, obtains Theoretical Physics address corresponding to the logical address of the fail bit memory cell；Make physical failure point to the chip
Analysis, by the Theoretical Physics address of the fail bit memory cell compared with the physical location of the failed areas, is managed
By the deviant of physical address to physical location；According to the deviant, the logical address of the chip is obtained to physical address
Transformational relation.
Optionally, the failed areas of choosing on the chip includes：At least two failures are chosen on the chip
Region.
Optionally, the invalid position region includes being arranged at the failed areas of chip corner position and is arranged at chip
The failed areas of center.
Optionally, the failed areas includes at least three fail bit memory cell；At least two fail bit storages
Unit is adjacent in the word line direction, and one in two adjacent in the word line direction fail bit memory cell with it is at least another
Individual fail bit memory cell is adjacent in bit line direction.
Optionally, the destruction failed areas includes：The failed areas is bombarded by converging laser beam.
Optionally, the destruction failed areas includes：By converging failed areas described in ion beam bombardment.
Optionally, also include after the destruction failed areas：By the image and electricity that detect the failed areas
Parameter signal intensity, judges whether the failed areas has been cut substrate location.
The embodiment of the invention also discloses a kind of conversion equipment of chip logic address to physical address, described device bag
Include：Unit is chosen, for choosing failed areas on the chip；Cut-sytle pollination unit, for destroying the failed areas；Obtain
Unit is taken, for detecting the failed areas, obtains the logical address of fail bit memory cell in the failed areas；First meter
Unit is calculated, for the transformational relation according to default logical address to physical address, obtains patrolling for the fail bit memory cell
Collect Theoretical Physics address corresponding to address；Comparing unit, for making physical failure analysis to the chip, the fail bit is deposited
The Theoretical Physics address of storage unit obtains Theoretical Physics address to actual bit compared with the physical location of the failed areas
The deviant put；Second computing unit, according to the deviant, the logical address of the chip is obtained to the conversion of physical address
Relation.
Optionally, the selection unit is used to choose at least two failed areas on the chip.
Optionally, the failed areas includes at least three fail bit memory cell；At least two fail bit storages
Unit is adjacent in the word line direction, and one in two adjacent in the word line direction fail bit memory cell with it is at least another
Individual fail bit memory cell is adjacent in bit line direction.
Compared with prior art, the technical scheme of the embodiment of the present invention has advantages below：
The failed areas chosen in advance by being destroyed on chip, and according to the failed areas of acquisition logically
Location, contrasts the Theoretical Physics address derived and whether actual destroyed position is consistent, so as to draw skew between the two
Amount.According to the offset information in multiple regions on the chip, logical address in chip can be obtained and turned to physical address
Rule is changed, so as to realize chip logic address to the rapid translating of physical address.
Further, by setting at least two failed areas, more fail messages can be obtained, so as to more accurate quick
Ground obtains in chip logical address to the conversion rule of physical address.
In addition, by setting one in fail bit memory cell adjacent in the word line direction in each failed areas
Individual and adjacent in bit line direction fail bit memory cell, the distribution of logical address in both directions can be obtained
Rule, so as to quickly obtain conversion of the logical address to physical address.
Brief description of the drawings
Fig. 1 is a kind of chip logic address of the embodiment of the present invention to the flow chart of the conversion method of physical address；
Fig. 2 is the position view that failed areas is distributed on chip in the embodiment of the present invention；
Fig. 3 is a kind of chip logic address of the embodiment of the present invention to the structural representation of the conversion equipment of physical address.
Embodiment
In the prior art, typically by technical staff by studying circuit design or domain, so as to by logic
Extrapolate actual physical address in address.But the reason for being in order at intellectual property protection, under many circumstances, it is difficult to get complete
Circuit design, and due to the polytropy of layout design, even same layout design person, according to the design of client
It is required that reason, its design such as area limitation are also not quite similar.Therefore realize logical address to actual physics according to the above method
It is low efficiency to be present in the conversion of address, defines the problem of difficult.
In actual applications, the conversion method based on the logical address that client is provided to physical address is found in chip and lost
Imitating the physical location of point, not only efficiency is low, and due to many dummy word lines in chip be present, dummy, redundant bit line with
And other designs etc., therefore the success rate for also resulting in detection is relatively low.Failpoint in chip can not be found under many circumstances
Actual position, make chip logic address to the transforming mistakes of actual physical address, it is difficult to effectively find failpoint or shadow
Ring subsequent treatment.In addition, sometimes in chip failpoint failure effect and unobvious, this also increases the difficulty of failure detection.
The failed areas that the embodiment of the present invention is chosen in advance by being destroyed on chip, and according to the failure area of acquisition
The logical address in domain, contrasts the Theoretical Physics address derived and whether actual destroyed position is consistent, so as to draw both
Between offset.According to the offset information in multiple regions on the chip, logical address can be obtained in chip to thing
The conversion rule of address is managed, so as to realize chip logic address to the rapid translating of physical address.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
The embodiments of the invention provide a kind of conversion method of chip logic address to physical address, reference picture 1, lead to below
Specific steps are crossed to be described in detail.
Step S101, chooses failed areas on the chip.
The embodiment of the present invention to be accomplished that the conversion of memory cell part logical address in chip to physical address,
Therefore the chosen area of failed areas is the memory cell part in chip in chip.
In specific implementation, two positions can be at least chosen on the chip as the failed areas, to obtain
Address d istribution rule between the two regions.Such as shown in Fig. 2 if the upper left position 1 of the chip is chosen respectively
Failed areas is used as with center 2, it is possible to obtains the Address d istribution of the memory cell in chip between the two positions
Rule.If choosing the upper left position 1 of the chip, center 2 and lower right position 3 respectively is used as failed areas,
It then can accordingly obtain the Address d istribution rule of memory cell between these three positions.
It is understood that the failed areas chosen is more, access unit address is believed in the chip that should be able to mutually obtain
Breath is also more, so as to faster and more accurately obtain chip logic address to the conversion rule of physical address.
In specific implementation, chip can be loaded into the vacuum chamber of focused ion beam (Focused Ion beam, FIB)
Room, and the memory cell of chip is placed in focal position.Zone map to be cut is drawn as one by the use of FIB inspection softwares
Failed areas.
In order to ensure the test sample amount of minimum to obtain logical address to the conversion rule of physical address, a failure area
Domain, i.e., at least to include three fail bit memory cell of memory cell in described pattern.It is understood that failed areas
Area it is bigger, comprising position memory cell it is more, then the associated address information obtained also can be more, obtain logical address and arrive
The efficiency of physical address translations rule also can be higher.
, can be to the mistake in failed areas in order to more fully obtain the change information of memory cell address in chip
Putting in order for position memory cell of effect is set.In the failed areas, at least two fail bit memory cell exist
One in two adjacent on word-line direction and adjacent in the word line direction fail bit memory cell and at least another failure
Position memory cell is adjacent in bit line direction.By making the fail bit memory cell two-by-two on word-line direction or bit line direction
It is adjacent, the regularity of distribution of access unit address in both directions in place can be obtained, so as to more accurately realize that position stores
Unit by logical address to physical address conversion.
Step S102, destroy the failed areas.
In specific implementation, it can be cut by converging failed areas described in ion beam bombardment until by the failed areas
The substrate location of bottom is cut, so as to cause the failed areas entirely ineffective, quickly to find the failure in follow-up test
Region.
During being cut by FIB equipment to specified failed areas, what can be equipped with by FIB equipment shows
Ripple device, real-time display are collected into the image electrical signal intensity related to the region secondary electron yield of cutting failed areas,
So as to judge whether cutting has arrived at the silicon chip substrate position of bottom.Specifically, due to cutting process can pass through metal level,
Oxide layer and substrate, therefore accordingly, signal intensity can present by bright dimmed, then brighten, shown by observation oscilloscope again
Pattern and its change in signal strength, it becomes possible to judge cutting whether in place.The mistake to all selections is completed according to the method described above
Imitate the destruction in region.
In specific implementation, the failed areas can also be bombarded by converging laser beam, until by the failed areas
The substrate location of bottom is cut to, so as to cause the failed areas entirely ineffective, quickly to find the mistake in follow-up test
Imitate region.
Step S103, the failed areas is detected, obtain the logical address of fail bit memory cell in the failed areas.
In specific implementation, specific test process can be：The chip is loaded into memory testing system, by testing
System is numbered compared with standard value to the corresponding electrical parameter of chip testing, and by obtained test electrical parameter data.If cross this
Parameter can not be by the way that then the parameter fails compared with standard value.The test system can record the ground of the chip of the failure automatically
Location and the logical address of the unit wherein to fail.The usual method of testing is that the chip in full wafer wafer is tested, because
After the completion of test, system can generate a wafer bitmap according to the shape of wafer and draw the bitmap of invalid position and corresponding mistake for this
Imitate the logical address of point.
Step S104, according to the transformational relation of default logical address to physical address, it is single to obtain the fail bit storage
Theoretical Physics address corresponding to the logical address of member.
For example, the logical address that fail bit memory cell is obtained by above-mentioned step S102 is：(258-453-ox04),
Represent the fail bit memory cell at wordline (WL) 258, bit line (BL) 453.
According to the transformational relation of default logical address to physical address, obtained logical address can be changed step by step
Into corresponding physical address.This is illustrated exemplified by sentencing bit line BL transformational relation.BL is changed by decimal number 453 first
Into binary number 111000101, the relation between binary number as shown in table 1 and default conversion numerical digit is obtained：
| Y8 | Y7 | Y6 | Y5 | Y4 | Y3 | Y2 | Y1 | Y0 |
| 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 |
Table 1
Wherein, Y [8] position is equal to right half part of the 1 table non ageing position memory cell in output domain, and Y [0] position is equal to
1 represents that the fail bit memory cell is odd bytes.Y [3-1] position is equal to 010 and represents the fail bit memory cell in BL [32-
47] between.Further, when Y [7] position is equal to 1, represent the fail bit memory cell between BL [40-47].Finally, lead to
The bit line position of the fail bit memory cell can be obtained in BL44 equal to 100 by crossing Y [6-4] position.
It is understood that the wordline of fail bit memory cell can also be managed according to similar default transformational relation
By upper physical address.Its conversion method is similar with the conversion method of above-mentioned bit line, and here is omitted.
Step S105, physical failure analysis is made to the chip, by the Theoretical Physics address of the fail bit memory cell
Compared with the physical location of the failed areas, Theoretical Physics address is obtained to the deviant of physical location.
In specific implementation, the physical analysis includes carrying out delamination operation to the failed areas.Specifically, can be with
, will be several layers of above chip using grinding and chemically treated method, including protective layer, metal level etc. removes, and exposes through hole and touches
Point (contact).After layer where arrival via-contact, it is possible to find the position storage destroyed purposely in the address according to breaking
Unit.Now the Theoretical Physics address obtained by step S104 is compared with destroyed physical location, it becomes possible to find
Whether both match consistent.If both position consistencies, illustrate that theoretic physical address is consistent with the physical address of reality,
If both are inconsistent, illustrate offset between the two be present, therefore cause Theoretical Physics address to be wrong.
The usual offset is due to caused by dummy word line, redundant word line, dummy or redundant bit line, it is therefore desirable to
Above-mentioned offset is added on the basis of theoretical physical address, can just obtain actual physical address.
Step S106, according to the deviant, the logical address of the chip is obtained to the transformational relation of physical address.
According to fail bit memory cell Theoretical Physics address in the multiple failed areas set on the chip and actual thing
The comparison of reason address can be found that the regularity of distribution of whole chip different zones physical address, so as to realize logical address in chip
To the conversion of physical address.
The embodiment of the present invention additionally provides a kind of chip logic address to the conversion equipment of physical address, as shown in figure 3, institute
State chip logic address includes to the conversion equipment 20 of physical address：Unit 201 is chosen, for choosing failure on the chip
Region；Cut-sytle pollination unit 202, for destroying the failed areas.Acquiring unit 203, for detecting the failed areas, obtain
Take the logical address of fail bit memory cell in the failed areas.First computing unit 204, for according to it is default logically
Location obtains Theoretical Physics address corresponding to the logical address of the fail bit memory cell to the transformational relation of physical address；Than
Compared with unit 205, for making physical failure analysis to the chip, by the Theoretical Physics address of the fail bit memory cell and institute
The physical location for stating failed areas is compared, and obtains Theoretical Physics address to the deviant of physical location；Second computing unit
206, according to the deviant, the logical address of the chip is obtained to the transformational relation of physical address.
In specific implementation, the selection unit 201 is used to choose at least two failed areas on the chip.
In specific implementation, the failed areas includes at least three fail bit memory cell；At least two failures
One in the adjacent in the word line direction and adjacent in the word line direction two fail bit memory cell of position memory cell with extremely
Another few fail bit memory cell is adjacent in bit line direction.
It is understood that above-mentioned chip logic address is to the conversion method of physical address and chip logic address to thing
The conversion equipment of reason address belongs under same technological thought, therefore on the converting means of the chip logic address to physical address
The content put is referred to said chip logical address to the appropriate section of the conversion method of physical address, and here is omitted.
One of ordinary skill in the art will appreciate that all or part of step in the various methods of above-described embodiment is can
To instruct the hardware of correlation to complete by program, the program can be stored in a computer-readable recording medium, storage
Medium can include：ROM, RAM, disk or CD etc..
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (5)
1. a kind of chip logic address is to the conversion method of physical address, it is characterised in that applied to memory cell in chip
Part, including：
At least two failed areas are chosen on the chip, and the failed areas includes being arranged at the failure of chip corner position
Region and the failed areas for being arranged at chip center position；Wherein, the failed areas stores including at least three fail bits
Unit；At least two fail bit memory cell are adjacent in the word line direction, and adjacent in the word line direction two failures
One in the memory cell of position is adjacent in bit line direction with least another fail bit memory cell；
Destroy the failed areas；
The failed areas is detected, obtains the logical address of fail bit memory cell in the failed areas；
According to the transformational relation of default logical address to physical address, the logical address pair of the fail bit memory cell is obtained
The Theoretical Physics address answered；
Physical failure analysis is made to the chip, by the Theoretical Physics address of the fail bit memory cell and the failed areas
Physical location be compared, obtain Theoretical Physics address to the deviant of physical location；
According to the deviant, the logical address of the chip is obtained to the transformational relation of physical address.
2. chip logic address as claimed in claim 1 is to the conversion method of physical address, it is characterised in that the destruction institute
Stating failed areas includes：The failed areas is bombarded by converging laser beam.
3. chip logic address as claimed in claim 1 is to the conversion method of physical address, it is characterised in that the destruction institute
Stating failed areas includes：By converging failed areas described in ion beam bombardment.
4. chip logic address as claimed in claim 1 is to the conversion method of physical address, it is characterised in that the destruction institute
State failed areas also includes afterwards：
By detecting the image and electrical parameter signal intensity of the failed areas, judge whether the failed areas has been cut
Substrate location.
5. a kind of chip logic address is to the conversion equipment of physical address, it is characterised in that including：
Unit is chosen, for choosing at least two failed areas on the chip；Wherein, the failed areas includes at least three
Individual fail bit memory cell；At least two fail bit memory cell are adjacent in the word line direction, and phase in the word line direction
One in two adjacent fail bit memory cell is adjacent in bit line direction with least another fail bit memory cell；
Cut-sytle pollination unit, for destroying the failed areas；
Acquiring unit, for detecting the failed areas, obtain the logical address of fail bit memory cell in the failed areas；
First computing unit, for the transformational relation according to default logical address to physical address, obtain the fail bit and deposit
Theoretical Physics address corresponding to the logical address of storage unit；
Comparing unit, for making physical failure analysis to the chip, by the Theoretical Physics address of the fail bit memory cell
Compared with the physical location of the failed areas, Theoretical Physics address is obtained to the deviant of physical location；
Second computing unit, according to the deviant, the logical address of the chip is obtained to the transformational relation of physical address.
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| CN104700903B (en) * | 2014-12-24 | 2018-06-19 | 上海华虹宏力半导体制造有限公司 | Memory chip scrambler verification method |
| CN105845592B (en) * | 2015-01-16 | 2018-11-16 | 中芯国际集成电路制造(上海)有限公司 | Method for failure analysis |
| CN106154133B (en) * | 2015-04-24 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | The address test method of chip and the failure analysis method of chip |
| US10296238B2 (en) * | 2015-12-18 | 2019-05-21 | Intel Corporation | Technologies for contemporaneous access of non-volatile and volatile memory in a memory device |
| CN109918284A (en) * | 2018-12-13 | 2019-06-21 | 江苏大学 | A kind of method and system constructing software failure region mode |
| CN109858233A (en) * | 2018-12-21 | 2019-06-07 | 惠州Tcl移动通信有限公司 | The mutual recognition methods of chip, device, storage medium and mobile terminal |
| CN112992251B (en) * | 2021-04-09 | 2022-05-17 | 长鑫存储技术有限公司 | Memory address test circuit and method, memory and electronic equipment |
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| CN101625904A (en) * | 2008-07-08 | 2010-01-13 | 中芯国际集成电路制造(上海)有限公司 | Method for verifying storage unit combination rule |
| CN101789357A (en) * | 2009-01-22 | 2010-07-28 | 中芯国际集成电路制造(上海)有限公司 | Regulating method of corresponding relationship between electrical address and physical address |
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