CN101789357A - Regulating method of corresponding relationship between electrical address and physical address - Google Patents
Regulating method of corresponding relationship between electrical address and physical address Download PDFInfo
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- CN101789357A CN101789357A CN200910045937A CN200910045937A CN101789357A CN 101789357 A CN101789357 A CN 101789357A CN 200910045937 A CN200910045937 A CN 200910045937A CN 200910045937 A CN200910045937 A CN 200910045937A CN 101789357 A CN101789357 A CN 101789357A
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Abstract
The invention provides a regulating method of a corresponding relationship between an electrical address and a physical address, which is used for obtaining a correct physical address of an unqualified cell by an electrical address of the unqualified cell in damaged logic die outputted by a bitmap system according to the corresponding relationship, thereby enhancing the success ratio of failure analysis. The method comprises the steps of: damaging the cell of a preset physical address in the die; detecting the die and outputting the electrical address of the damaged cell by the bitmap system; obtaining the physical address of the damaged cell by the electrical address on the basis of the corresponding relationship between the obtained electrical address and the physical address; comparing to obtain a deviation between the obtained physical address and the preset physical address; and regulating the corresponding relationship according to the deviation.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to the method for adjustment of electrical address and physical address corresponding relation.
Background technology
The inefficacy analysis is the important means that improves the semiconductor product yield, its principle is generally: at the chip of producing (die) when fault is arranged, by the inefficacy analysis, orient the physical location of disabling unit (cell), and analyze that to draw be which kind of defective causes described cell to lose efficacy, so that improve in the follow-up manufacturing process, improve yield.
Chip can be divided into based on the memory chip of realization memory function with to realize the logic chip of logic function substantially by its function, for memory chip, inefficacy analytical method commonly used is after chip fabrication technique is finished substantially, orient the physical location of inefficacy cell with laser manufacturing defect on chip, then each layer of chip peeled off out separately, analyzing is which kind of defective causes this cell to lose efficacy again.
For logic chip,, therefore, obtain the situation of whole die or die place wafer (wafer) usually by to storage cell inefficacy property analysis among the logic die owing to also comprise memory (RAM) unit (cell) usually among the die.
But because each interlayer of logic die has logical relation usually, therefore adopt the above-mentioned inefficacy analytical plan that is applicable to memory die, may just destroy described logical relation, thereby can't correct analysis go out the position of logic die inefficacy cell.
So industry adopts at present usually following proposal to the analysis of logic die inefficacy property: the electrical address that is detected defective cell among logic die and the output logic die by bitmap system (Bitmap Program); According to described electrical address, reach the corresponding relation of existing electrical address and physical address then, obtain the physical address of this defective cell, be positioned to the position of this defective cell, to carry out subsequent treatment.
But in this scheme application process, the cell that the described physical address of common appearance navigates to is not defective cell, the problem that the i.e. wrong feasible inefficacy analysis of physical address that finds out according to this corresponding relation is failed, need a kind of scheme of adjusting described corresponding relation badly, to improve the success rate of inefficacy analysis for this reason.
Summary of the invention
The invention provides the method for adjustment of electrical address and physical address corresponding relation, with according to this corresponding relation, by the electrical address of defective cell among the damage logic die of bitmap system output, obtain the correct physical address of this defective cell, and then improve the success rate of inefficacy analysis.
The present invention proposes the method for adjustment of electrical address and physical address corresponding relation, this method comprises: the cell that destroys preset physical address among the die; The bitmap system detects this die, and exports the electrical address of the cell of this destruction; Based on the corresponding relation of existing electrical address and physical address, obtain the physical address of this destruction cell by this electrical address; Compare this physical address of acquisition and the deviation of preset physical address; And adjust described corresponding relation according to this deviation.
The present invention is by destroying the cell of preset physical address, adopt the bitmap system to detect and export the electrical address of this cell then, go out the physical address of this cell again according to this electrical address and above-mentioned existing corresponding relation correspondence, and compare both deviations according to physical address and the preset physical address that correspondence goes out, described corresponding relation is adjusted, thereby when detecting damage logic die with the bitmap system and exporting the electrical address of defective cell, can this electrical address and adjusted corresponding relation obtain the correct physical address of defective cell, and then improve the success rate of inefficacy analysis.
Description of drawings
Fig. 1 is the flow chart of electrical address and physical address corresponding relation method of adjustment in the embodiment of the invention;
Fig. 2 is the structural representation that piecemeal is selected in the embodiment of the invention;
Fig. 3 is the schematic diagram of physical address skew in the embodiment of the invention.
Embodiment
Problem at background technology, the embodiment of the invention proposes: if can calculate the physical address of the defective cell that obtains according to the electrical address that has the output of corresponding relation and bitmap system, deviation with this defective cell actual physical address, that just can be adjusted this corresponding relation based on described deviation, can carry out the inefficacy analysis of success according to adjusted corresponding relation.
Fig. 1 is the flow chart of electrical address and physical address corresponding relation method of adjustment in the embodiment of the invention, and in conjunction with this figure as can be known, based on above-mentioned idea, the described method of adjustment that the embodiment of the invention proposes comprises step:
Step 1, the cell of preset physical address among the destruction die;
Because before ground floor metal wire connection technology is finished, no matter be deposit oxide layer or etching pattern, under scanning electron microscopy (SEM), all can cause very large disturbance to distinguishing each cell, be difficult to distinguish each cell, therefore preferable selection is to connect at the ground floor metal wire to destroy preset physical address cell after technology is finished; And because after second layer metal line connection technology is finished, each cell generally couples together by metal wire, if destroy a cell, then may cause the inefficacy of related with it a plurality of or even a slice cell, make subsequent step to carry out smoothly, the therefore preferable described second layer metal line that is chosen in usually connects the cell that destroys preset physical address before technology begins.In sum, preferable, before the ground floor metal wire connects technology and finishes back and second layer metal line and connect technology and begin, the cell of preset physical address among the destruction die.
Step 2, the bitmap system detects this die, and exports the electrical address of the cell of this destruction;
Step 3 based on the corresponding relation of existing electrical address and physical address, obtains the physical address of this destruction cell by this electrical address;
Step 4 compares this physical address of acquisition and the deviation of preset physical address;
For step 1, can adopt multiple mode to destroy this cell, the preferable focused ion beam (FIB) of passing through is bombarded destruction to cell, and its accuracy is higher, can guarantee can not destroy other cell.Behind this external bombardment cell, bombardment place can produce pit, because the method for adjustment that the embodiment of the invention proposes is usually used in the manufacture craft of die, therefore behind this cell of bombardment, also has subsequent technique, for guaranteeing that subsequent technique can not be subjected to this pit and destroy, preferable can insert filler in this pit, described filler can be oxide, requires filler to satisfy less or no influence to the subsequent technique influence usually, conditions such as it is convenient to reach filling, and technology is simple.
Correct for guaranteeing the corresponding relation of adjusting; improve and adjust accuracy rate and efficient; usually can select a plurality of die to destroy cell among each die; the selection mode of cell among die and the die has multiple; for example according to the distribution situation of blockette in the wafer (block); select modes such as a plurality of die, follow-up will the description by embodiment.
Can realize the adjustment of described corresponding relation by above-mentioned steps 1～5, but preferable, can also verify, the correctness of adjusting with further affirmation the corresponding relation of adjusting.
Checking adjusts whether correct scheme can detect the die that has damaged with the bitmap system, export the electrical address of defective cell among this damage die then, and based on adjusted corresponding relation, find physical address by electrical address, whether defective, if qualified, then adjusted corresponding relation is correct if adopting physical failure analysis means such as (PFA) to detect the cell of this physical address correspondence again, if defective, then adjusted corresponding relation is incorrect.
Below with reference to accompanying drawings the present invention is described in more detail, has wherein represented the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, the unnecessary details because they can be the present invention and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Embodiment
Such scheme can but be not limited to implement in the following way:
At first the bitmap of a plurality of wafers is folded figure, find out the higher a plurality of die of survival rate according to folded figure again, this moment, wafer remained unfulfilled whole manufacture crafts, and survival rate is represented after subsequent technique is finished herein, the probability that this die is qualified; Survival rate is higher herein only is a kind of predetermined condition, and it also can be other predetermined condition, only need help getting rid of other factors the influence of this programme is got final product.
After finding out the higher die of survival rate, select corresponding block according to the distribution situation of block in the wafer again, and in each block that selects, respectively select a die;
With reference to Fig. 2, in the present embodiment, select the block 20 of 8 two row four lines, in each block20, select a die 21 then, the position of die 21 is near the summit of each block 20; Illustrate two rectangles of 8 die 21 nestings.The mode of the illustrated this die of choosing can make that each point is verified mutually on the about rectangle, avoids independent reconnaissance may make cell among other factor affecting each points die, makes the problem that the subsequent implementation process is wrong;
After selecting die, when in each die, selecting cell, preferablely among each die only select a die, mistake can not occur, improve and adjust accuracy rate with the address of guaranteeing the output of subsequent bitmap system; What the position of the cell that selects among the die was preferable will discern easily, for example the sharp corner or the place etc. that keeps to the side.In the present embodiment, select near the cell the summit among each die, and preserve the SEM photo of cell, obtain the physical address of cell; Near the distance that is meant the cell of selection and this summit the wherein said summit is at preset range, and described preset range independently determined by the enforcement personnel, satisfy the cell that selects easily identification get final product.
After having selected cell, the cell that present embodiment adopts the FIB bombardment to select destroys the cell that selects, and then inserts oxide to fill this pit at the bombardment pit, avoids influencing subsequent technique; Wherein the process conditions of the cell of FIB bombardment selection are easy to obtain according to persons skilled in the art common practise, and present embodiment does not elaborate.
After destroying each cell that selects, adopt the bitmap system that each die is detected, and export the electrical address of the cell of each destruction by the bitmap system; According to the corresponding relation of existing electrical address and physical address, obtain the physical address of the cell of each destruction then;
With the physical address of the physical address of each cell of obtaining and each cell that preserves in advance relatively, compare both deviations; Referring to Fig. 3, be the physical address deviation schematic diagram that compares in the embodiment of the invention, 30 block among the figure for the die place under the cell of the physical address correspondence that obtains, the block at the die place under the cell of the physical address correspondence that label 31 representatives are preserved in advance, as can be seen, both laterally do not have skew, but vertical misalignment two units;
According to skew shown in Figure 3, the corresponding relation of physical address and electrical address is adjusted, for example after going out physical address, laterally remain unchanged, but two units of vertical misalignment are only defective cell physical address corresponding according to the electrical address correspondence.
In the present embodiment, after comparing above-mentioned skew adjustment corresponding relation, also adopt PFA that adjusted relation is verified: the die that selects other damage, detect this die with the bitmap system then, and export the electrical address of defective cell among this die by the bitmap system, according to this electrical address and adjusted corresponding relation, obtain the physical address of defective cell again.Implement according to reality, the corresponding relation of present embodiment adjustment can be used in the position of correctly orienting defective cell.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (13)
1. the method for adjustment of electrical address and physical address corresponding relation is characterized in that, comprising:
Destroy the unit of preset physical address in the chip;
The bitmap system detects this chip, and exports the electrical address of the unit of this destruction;
Based on the corresponding relation of existing electrical address and physical address, obtain the physical address of the unit of this destruction by this electrical address;
Compare this physical address of acquisition and the deviation of preset physical address; And
Adjust described corresponding relation according to this deviation.
2. whether correct the method for claim 1 is characterized in that, also comprises: after adjusting described corresponding relation, check adjusted corresponding relation step.
3. method as claimed in claim 2 is characterized in that, described checking procedure specifically comprises:
The bitmap system detects the chip of other damage, and exports the electrical address of defective unit in the chip of described other damage;
According to described adjusted corresponding relation, by this electrical address, the physical address of defective unit in the chip of described other damage of acquisition; And
Whether the unit of verifying described physical address correspondence is defective, and confirms that when qualified this adjusted corresponding relation is correct.
4. method as claimed in claim 3 is characterized in that, adopts the physical failure analysis to carry out described checking.
5. the method for claim 1 is characterized in that, bombards by focused ion beam and destroys this unit.
6. method as claimed in claim 5 is characterized in that, after bombardment, inserts filler to fill up this pit in the zone of this unit bombardment pit.
7. method as claimed in claim 6, described filler are oxide.
8. the method for claim 1 is characterized in that, described chip has a plurality of; And the step that also is included in a plurality of chips of selection in the wafer.
9. method as claimed in claim 8 is characterized in that, described selection step specifically comprises:
The bitmap of a plurality of wafers is folded figure;
Based on folded figure effect, in described a plurality of wafers, pick out the chip that survival rate satisfies predetermined condition.
10. method as claimed in claim 8 is characterized in that, selects described a plurality of chip according to the distribution situation of blockette in the wafer.
11. method as claimed in claim 10 is characterized in that, the blockette of described a plurality of chips under separately is different, and
Ruined unit is in preset range with the distance on corresponding blockette summit in each chip.
12. as the described method of each claim in the claim 1～11, it is characterized in that, in a chip, only destroy a unit.
13. the method for claim 1 is characterized in that, the unit of preset physical address in the destruction chip before the ground floor metal wire connects technology and finishes the back is connected technology with this a back technology and begin.
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| CN200910045937A CN101789357A (en) | 2009-01-22 | 2009-01-22 | Regulating method of corresponding relationship between electrical address and physical address |
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| CN200910045937A CN101789357A (en) | 2009-01-22 | 2009-01-22 | Regulating method of corresponding relationship between electrical address and physical address |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104156325A (en) * | 2014-08-26 | 2014-11-19 | 上海华虹宏力半导体制造有限公司 | Method and device for converting logical address of chip into physical address of chip |
| CN104575613A (en) * | 2015-02-10 | 2015-04-29 | 武汉新芯集成电路制造有限公司 | Electrical failure analysis method |
| CN105845592A (en) * | 2015-01-16 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Method for failure analysis |
| CN106154133A (en) * | 2015-04-24 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The address method of testing of chip and the failure analysis method of chip |
| CN106251908A (en) * | 2016-08-02 | 2016-12-21 | 武汉新芯集成电路制造有限公司 | A kind of verification method of the corresponding relation of electrical address and physical address |
| CN112216621A (en) * | 2020-10-14 | 2021-01-12 | 上海华虹宏力半导体制造有限公司 | Memory wafer test method and test device |
-
2009
- 2009-01-22 CN CN200910045937A patent/CN101789357A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104156325A (en) * | 2014-08-26 | 2014-11-19 | 上海华虹宏力半导体制造有限公司 | Method and device for converting logical address of chip into physical address of chip |
| CN105845592A (en) * | 2015-01-16 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Method for failure analysis |
| CN105845592B (en) * | 2015-01-16 | 2018-11-16 | 中芯国际集成电路制造(上海)有限公司 | Method for failure analysis |
| CN104575613A (en) * | 2015-02-10 | 2015-04-29 | 武汉新芯集成电路制造有限公司 | Electrical failure analysis method |
| CN104575613B (en) * | 2015-02-10 | 2017-10-24 | 武汉新芯集成电路制造有限公司 | A kind of electrical property failure analysis method |
| CN106154133A (en) * | 2015-04-24 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The address method of testing of chip and the failure analysis method of chip |
| CN106154133B (en) * | 2015-04-24 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | The address test method of chip and the failure analysis method of chip |
| CN106251908A (en) * | 2016-08-02 | 2016-12-21 | 武汉新芯集成电路制造有限公司 | A kind of verification method of the corresponding relation of electrical address and physical address |
| CN106251908B (en) * | 2016-08-02 | 2019-03-12 | 武汉新芯集成电路制造有限公司 | A kind of verification method of the corresponding relationship of electrical address and physical address |
| CN112216621A (en) * | 2020-10-14 | 2021-01-12 | 上海华虹宏力半导体制造有限公司 | Memory wafer test method and test device |
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Application publication date: 20100728 |