CN106251908B - A kind of verification method of the corresponding relationship of electrical address and physical address - Google Patents
A kind of verification method of the corresponding relationship of electrical address and physical address Download PDFInfo
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- CN106251908B CN106251908B CN201610620746.1A CN201610620746A CN106251908B CN 106251908 B CN106251908 B CN 106251908B CN 201610620746 A CN201610620746 A CN 201610620746A CN 106251908 B CN106251908 B CN 106251908B
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- address
- unit
- physical address
- corresponding relationship
- electrical
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C2029/1806—Address conversion or mapping, i.e. logical to physical address
Abstract
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of verification method of the corresponding relationship of electrical address and physical address, the corresponding relationship correctness of verifying electrical address and physical address is compared to by the threshold voltage of unit corresponding to the physical address to conversion and the unit positioned at the unit periphery, to realize the precise verification to the corresponding relationship of electrical address and physical address, this method restriction not stringent to failure mode, and it is easy to operate, fast, to effectively increase verification efficiency and success rate.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to the corresponding relationships of a kind of electrical address and physical address
Verification method.
Background technique
Ineffectiveness analysis is to improve the important means of semiconductor product yield, and principle is usual are as follows: in the chip produced
In the event of failure, by ineffectiveness analysis, the position of disabling unit (failbit) is oriented, and analyzes and obtains it is which kind of is lacked
Falling into causes the disabling unit to fail, and in order to improve in subsequent fabrication process, improves yield；In ineffectiveness analytic process
In, the corresponding relationship (scramble) between electrical address and physical address has the function of key.
The verification method of the corresponding relationship between electrical address and physical address generally comprises rough verifying and finely at present
Verifying；Rough verifying are as follows: offer scramble file first, secondly using laser chip specific position (such as chip
The upper left corner) label (mark) is beaten to destroy the physical address in chip (such as upper left corner), then corresponded to using test chip checking
Electrical address whether have a Problem of Failure generation, and rough orientation is had to pair.Fine verification are as follows: selection certain failure modes
Sample (sample of (single bit CT open)) carry out physical failure analysis (Physical failure analysis,
Abbreviation PFA) it is whether correct accurately to verify the corresponding relationship between electrical address and physical address.But due to failure mode
It must be obvious hard failure (hard fail), just be easier to observe during PFA in this way, just can guarantee and test
The successful progress of card, such as single data bit memory cell through-hole disconnect (single bit CT open) this kind of failure mode,
Therefore the failure mode that can choose is very limited, and the PFA step include SEM (scanning electron microscope,
Scanning electron microscope) see VC (voltage contrast, voltage-contrast), FIB (Focused Ion Beam, focus from
Beamlet) sample cutting, or even TEM (Transmission Electron Microscope, transmission electron microscope) is needed to see
Survey and etc., step is very cumbersome, these are all that those skilled in the art do not expect to see.
Summary of the invention
In view of the above problems, the invention discloses the verifyings of a kind of electrical address and the corresponding relationship of physical address
Method includes the following steps:
The corresponding relationship and a sample with disabling unit of electrical address and physical address to be verified are provided, and described
Sample is provided with through-hole；
Obtain the electrical address of the disabling unit；
According to the corresponding relationship of the electrical address and physical address to be verified by the electrical address of the disabling unit
Be converted to physical address；
By the sample grinding horizontal plane (CT level) to through-hole；
In the corresponding unit of the physical address for finding out conversion on the sample；
The corresponding unit of the physical address and the unit progress threshold voltage neighbouring with the unit to the conversion
(Vt) it tests, and judges whether the corresponding relationship of the electrical address to be verified and physical address is correct according to test result.
The verification method of the corresponding relationship of above-mentioned electrical address and physical address, wherein in the method, if described turn
The corresponding unit of the physical address that changes and different from the threshold voltage of the neighbouring unit of the unit (bits), then described in judgement
The corresponding relationship of electrical address and physical address to be verified is correct.
The verification method of the corresponding relationship of above-mentioned electrical address and physical address, wherein in the method, if described turn
The corresponding unit of the physical address that changes and identical as the threshold voltage of the neighbouring unit of the unit, then judge described to be verified
Electrical address and the corresponding relationship of physical address be wrong.
The verification method of the corresponding relationship of above-mentioned electrical address and physical address, wherein in the method, utilize nanometer
Detector (nano-prober) is carried out to the corresponding unit of the physical address of the conversion and with the neighbouring unit of the unit
Threshold voltage test.
The verification method of the corresponding relationship of above-mentioned electrical address and physical address, wherein the disabling unit is soft mistake
Imitate (soft fail) or hard failure (hard fail).
The verification method of the corresponding relationship of above-mentioned electrical address and physical address, wherein described to grind the sample
To the through-hole horizontal plane the step of specifically: using the method oxide layer that covers the sample surfaces and metal of grinding
Layer removal, until the through-hole is exposed.
The verification method of the corresponding relationship of above-mentioned electrical address and physical address, wherein in the method, utilize craft
The sample is ground to the horizontal plane of the through-hole by the method for grinding or mechanical lapping.
The verification method of the corresponding relationship of above-mentioned electrical address and physical address, wherein the sample is storage core
Piece.
The verification method of the corresponding relationship of above-mentioned electrical address and physical address, wherein the sample is data holding
(data retention) has abnormal single data bit memory cell (singlebit) or neighbouring Double Data position storage unit
(two bits)。
The verification method of the corresponding relationship of above-mentioned electrical address and physical address, wherein in the method, utilize bitmap
System obtains the electrical address of the disabling unit.
Foregoing invention is with the following advantages or beneficial effects:
The invention discloses the verification methods of a kind of electrical address and the corresponding relationship of physical address, pass through the object to conversion
The threshold voltage of unit corresponding to reason address and the unit positioned at the unit periphery is compared to verifying electrical address and object
The corresponding relationship correctness of address is managed, to realize the precise verification to the corresponding relationship of electrical address and physical address, the party
The method restriction not stringent to failure mode, and it is easy to operate, fast, to effectively increase verification efficiency and success rate.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent.Identical label indicates identical part in all the attached drawings.Not can according to than
Example draws attached drawing, it is preferred that emphasis is shows the gist of the present invention.
Fig. 1 is the verification method flow chart of the corresponding relationship of electrical address and physical address in the embodiment of the present invention；
Fig. 2 is the Id-Vg curve of disabling unit and adjacent unit in a specific embodiment of the invention.
Specific embodiment
As shown in Figure 1, the present embodiment is related to a kind of verification method of the corresponding relationship of electrical address and physical address, specifically
, this method comprises the following steps:
Step S1 provides the corresponding relationship and a sample with disabling unit of electrical address and physical address to be verified
Product, which can be the memory chip of the storage unit for being provided with any type, and (the storage core on piece is provided with
Through-hole)；The corresponding relationship of the electrical address to be verified and physical address is scramble file, and the sample of the disabling unit can
Think that data maintain abnormal single data bit memory cell or neighbouring Double Data position storage unit etc.；In implementation of the invention
In example, the failure mode of disabling unit is not particularly limited, which can be soft failure, or hard to lose
Effect, this has no effect on the purpose of the present invention.
Step S2 obtains the electrical address of disabling unit.
In a preferred embodiment of the invention, the electrical address of disabling unit is obtained using bitmap system.
Step S3 turns the electrical address of disabling unit according to the corresponding relationship of electrical address and physical address to be verified
Turn to physical address.
Sample is ground to the horizontal plane of through-hole by step S4.
In a preferred embodiment of the invention, sample is ground to the water of through-hole using hand lapping or mechanical lapping
Plane.
In a preferred embodiment of the invention, the step of sample is ground to the horizontal plane of through-hole specifically: use
Oxide layer and the metal layer removal that the method for grinding covers sample surfaces, until stopping grinding after exposing through-hole.
It is corresponding on this sample that the physical address being converted in above-mentioned steps S3 is found out on step S5, Yu Shangshu sample
Unit.
Step S6, to the physical address being converted in above-mentioned steps S3 on this sample corresponding unit and with the list
The neighbouring unit of member carries out threshold voltage (Vt) test, and electrical address and physical address to be verified are judged according to test result
Corresponding relationship it is whether correct；If the physical address being converted in above-mentioned steps S3 on this sample corresponding unit and with
The threshold voltage of the neighbouring unit of the unit is different, then judges the corresponding relationship of above-mentioned electrical address to be verified and physical address
It is correctly, if the physical address being converted in above-mentioned steps S3 corresponding unit and neighbouring with the unit on this sample
Unit threshold voltage it is identical, then judge that the corresponding relationship of above-mentioned electrical address to be verified and physical address is wrong.
In a preferred embodiment of the invention, using nanometer detection device to the physics being converted in above-mentioned steps S3
Address corresponding unit and the unit progress threshold voltage test neighbouring with the unit on this sample.
Specifically, if the corresponding relationship of above-mentioned electrical address and physical address to be verified is correctly above-mentioned steps
The physical address being converted in S3 on this sample corresponding unit (i.e. fail address) Id-Vg curve will be located at
The Id-Vg curve of the unit on the unit periphery is different, as shown in Figure 2, wherein 1 is the physical address that is converted in the sample
The Id-Vg curve of upper corresponding unit, 2,3,4 be respectively corresponding on this sample positioned at the physical address being converted to
The Id-Vg curve of the unit on unit periphery, it is clear that, the physical address being converted in above-mentioned steps S3 is on this sample
The Id-Vg curve 1 of corresponding unit will be different from the Id-Vg curve 2,3,4 of unit on the unit periphery is located at；On if
The corresponding relationship for stating electrical address and physical address to be verified is physical address that is wrong, being converted in above-mentioned steps S3
The Id-Vg curve of corresponding unit will be with the Id-Vg curve basic one for the unit for being located at the unit periphery on this sample
It causes.
It should be appreciated by those skilled in the art that those skilled in the art are combining the prior art and above-described embodiment can be with
Realize change case, this will not be repeated here.Such change case does not affect the essence of the present invention, and it will not be described here.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, devices and structures not described in detail herein should be understood as gives reality with the common mode in this field
It applies；Anyone skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, anything that does not depart from the technical scheme of the invention, foundation
Technical spirit of the invention any simple modifications, equivalents, and modifications made to the above embodiment, still fall within the present invention
In the range of technical solution protection.
Claims (10)
1. a kind of verification method of the corresponding relationship of electrical address and physical address, which comprises the steps of:
The corresponding relationship and a sample with disabling unit of electrical address and physical address to be verified, and the sample are provided
It is provided with through-hole；
Obtain the electrical address of the disabling unit；
The electrical address of the disabling unit is converted according to the corresponding relationship of the electrical address and physical address to be verified
For physical address；
The sample is ground to the horizontal plane of the through-hole；
In the corresponding unit of the physical address for finding out conversion on the sample；
The corresponding unit of the physical address and the unit progress threshold voltage test neighbouring with the unit to the conversion, and
Judge whether the corresponding relationship of the electrical address to be verified and physical address is correct according to test result.
2. the verification method of the corresponding relationship of electrical address as described in claim 1 and physical address, which is characterized in that described
In method, if the corresponding unit of the physical address of the conversion and different from the threshold voltage of the neighbouring unit of the unit,
Then judge that the corresponding relationship of the electrical address to be verified and physical address is correct.
3. the verification method of the corresponding relationship of electrical address as claimed in claim 2 and physical address, which is characterized in that described
In method, if the corresponding unit of the physical address of the conversion and identical as the threshold voltage of the neighbouring unit of the unit,
Then judge that the corresponding relationship of the electrical address to be verified and physical address is wrong.
4. the verification method of the corresponding relationship of electrical address as described in claim 1 and physical address, which is characterized in that described
In method, using nanometer detection device to the corresponding unit of the physical address of the conversion and the unit neighbouring with the unit into
The test of row threshold voltage.
5. the verification method of the corresponding relationship of electrical address as described in claim 1 and physical address, which is characterized in that described
Disabling unit is soft failure or hard failure.
6. the verification method of the corresponding relationship of electrical address as described in claim 1 and physical address, which is characterized in that described
The step of sample is ground to the horizontal plane of the through-hole specifically: covered the sample surfaces using the method for grinding
Oxide layer and metal layer removal, until the through-hole is exposed.
7. the verification method of the corresponding relationship of electrical address as claimed in claim 6 and physical address, which is characterized in that described
In method, the sample is ground to the horizontal plane of the through-hole using the method for hand lapping or mechanical lapping.
8. the verification method of the corresponding relationship of electrical address as described in claim 1 and physical address, which is characterized in that described
Sample is memory chip.
9. the verification method of the corresponding relationship of electrical address as claimed in claim 8 and physical address, which is characterized in that described
Disabling unit is that data maintain abnormal single data bit memory cell or neighbouring Double Data position storage unit.
10. the verification method of the corresponding relationship of electrical address as described in claim 1 and physical address, which is characterized in that institute
It states in method, the electrical address of the disabling unit is obtained using bitmap system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610620746.1A CN106251908B (en) | 2016-08-02 | 2016-08-02 | A kind of verification method of the corresponding relationship of electrical address and physical address |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610620746.1A CN106251908B (en) | 2016-08-02 | 2016-08-02 | A kind of verification method of the corresponding relationship of electrical address and physical address |
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| Publication Number | Publication Date |
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| CN106251908A CN106251908A (en) | 2016-12-21 |
| CN106251908B true CN106251908B (en) | 2019-03-12 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112992251B (en) * | 2021-04-09 | 2022-05-17 | 长鑫存储技术有限公司 | Memory address test circuit and method, memory and electronic equipment |
| CN116153386B (en) * | 2023-04-21 | 2023-09-12 | 长鑫存储技术有限公司 | Semiconductor failure analysis method, storage medium and electronic device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI221911B (en) * | 2002-04-08 | 2004-10-11 | Winbond Electronics Corp | Verifying method for validity of Bitmap test program |
| CN101789357A (en) * | 2009-01-22 | 2010-07-28 | 中芯国际集成电路制造(上海)有限公司 | Regulating method of corresponding relationship between electrical address and physical address |
| CN104795340A (en) * | 2015-04-13 | 2015-07-22 | 上海华力微电子有限公司 | Method for analyzing failures due to defects of ONO (silicon oxide-silicon nitride-silicon oxide) thin films of Flash products |
| CN105206304A (en) * | 2015-09-12 | 2015-12-30 | 上海华虹宏力半导体制造有限公司 | Method and system for failure analysis of split gate type flash memory with shared word line |
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2016
- 2016-08-02 CN CN201610620746.1A patent/CN106251908B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI221911B (en) * | 2002-04-08 | 2004-10-11 | Winbond Electronics Corp | Verifying method for validity of Bitmap test program |
| CN101789357A (en) * | 2009-01-22 | 2010-07-28 | 中芯国际集成电路制造(上海)有限公司 | Regulating method of corresponding relationship between electrical address and physical address |
| CN104795340A (en) * | 2015-04-13 | 2015-07-22 | 上海华力微电子有限公司 | Method for analyzing failures due to defects of ONO (silicon oxide-silicon nitride-silicon oxide) thin films of Flash products |
| CN105206304A (en) * | 2015-09-12 | 2015-12-30 | 上海华虹宏力半导体制造有限公司 | Method and system for failure analysis of split gate type flash memory with shared word line |
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