CN101625904A - Method for verifying storage unit combination rule - Google Patents
Method for verifying storage unit combination rule Download PDFInfo
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- CN101625904A CN101625904A CN200810040356A CN200810040356A CN101625904A CN 101625904 A CN101625904 A CN 101625904A CN 200810040356 A CN200810040356 A CN 200810040356A CN 200810040356 A CN200810040356 A CN 200810040356A CN 101625904 A CN101625904 A CN 101625904A
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Abstract
The invention provides a method for verifying a storage unit combination rule, which is used for verifying the correctness of the combined rule of storage units of a storage chip, and comprises the following steps: 1, marking a position to be damaged on the storage chip to be verified; 2, adopting a focused ion beam to make a damaged notch at the position to be damaged; 3, adopting a tester to test the storage chip, and marking a disabled position of the storage unit tested by the tester; 4, removing a medium layer and a metal connecting line layer on the surface of an active layer of the storage unit, and determining the position of the storage unit having the damaged notch made in the step 2; and 5, comparing the disabled position of the storage unit tested in the step 3 with the position of the storage unit having the damaged notch determined in the step 4 to perform combined verification on the storage units. By making the damaged notch with the focused ion beam and removing the medium layer and the metal connecting line layer on the surface of the active layer of the storage unit, the method for verifying the storage unit combination can effectively solve the problems of the prior verification method that the storage chip is easy to be failed entirely and has low precision.
Description
Technical field
The present invention relates to the field tests of storage chip, relate in particular to the verification method of same memory cell combination in the storage chip.
Background technology
Storage chip is the common electronic product in present consumer electronics market.Storage chip can effectively be stored the numerical information of a constant volume.The storage chip product is normally repeated to form by some identical storage unit, therefore only design basic storage unit usually in the design phase of storage chip, then described basic storage unit is combined to form complete storage chip product according to certain rules.When being tested, the storage chip of making to verify whether combination (Scramble) rule of storage unit conforms to the combination rule of design phase.The storage chip that has only the combination rule of making storage unit to conform to the combination rule of design phase, just can carry out accurate in locating to the unit that lost efficacy at follow-up test phase, the failure analysis of doing product reaches the performance of raising storage chip and the purpose of yield.
The verification method of storage unit combination rule is to adopt optical microscope and laser that institute's proofing chip manufacturing is artificially damaged recess on the conventional store chip; Adopt test machine to have the storage chip of damage to test then, determine the last damage position of the storage chip bitmap of testing on the test machine (bitmap) artificial manufacturing; Comparison actual artificially storage chip make the position of damage and the storage chip bitmap tested on the position damaged just can verify whether the combination of memory chip stores unit of actual fabrication consistent with the combination of the storage unit of desired design.Classic method is because the area of damage from laser can be very big, thereby can not accurately determine the physical location of the storage unit of actual damage.Therefore, determining that storage chip artificially makes the position of damage and can only carry out roughly affirmation, promptly the accuracy of position is lower, thereby causes the accuracy of comparison result low.Simultaneously, adopt laser, easily cause damaging the problem of the global failure that excessively causes storage chip the artificial unmanageable problem of energy that has laser of damaging of the storage chip manufacturing of being verified.
Summary of the invention
The object of the present invention is to provide a kind of verification method of storage unit combination rule, the accuracy damage lower and artificial manufacturing that the verification method that makes up with storage unit on the solution conventional store chip exists easily causes the problem of storage chip global failure.
For achieving the above object, the verification method of storage unit combination rule of the present invention, wherein, the storage unit repeated combination is a storage chip.This storage chip comprise storage unit active region layer, be formed on the dielectric layer of surfaces of active regions and the metal connecting line layer on the dielectric layer.The verification method of storage unit combination rule of the present invention may further comprise the steps: step 1: mark is treated damage position on storage chip to be verified; Step 2: adopt focused ion beam at the damage recess for the treatment of the damage position making predetermined area and the degree of depth; Step 3: adopt the test machine test to make the storage chip of damage recess, the storage-unit-failure position that the labeled test machine is tested; Step 4: remove the dielectric layer and the metal connecting line layer on active layer surface, memory chip stores unit, the position of the damage recess that determining step 2 is made; Step 5: the position of the damage recess that storage-unit-failure position that comparison step 3 records and step 4 are determined.The position that mark is to be damaged in the step 1 is to adopt optical microscope and laser several treat damage position at storage chip mark to be verified.
Further, several of institute's mark are treated damage position cluster a jiao at storage chip to be verified.The damage position for the treatment of of the damage recess that step 2 is made is the some one treated in damage position of cluster one jiao of storage chip to be verified.Between step 2 and step 3, also comprise with metal filled damage recess.Further, adopt the chemical gas-phase method plated metal to fill described damage recess.The metal of filling the damage recess adopts platinum, tungsten or molybdenum.Dielectric layer and metal connecting line layer that step 4 is removed described storage chip active layer surface adopt wet etching to remove.Wherein, wet etching adopts hydrogen fluoride solution.
Compare with the verification method of storage unit combination rule on the conventional store chip, the verification method of storage unit combination rule of the present invention, by adopting the ion focus bundle to make the area and the degree of depth that damage recess on the storage chip can accurately be controlled the damage recess of making, avoid occurring because of damaging the problem that excessively causes the chip global failure.Dielectric layer by removing active layer surface on the storage chip and metal connecting line layer can accurately be determined the position of the storage unit damaged, the comparative result of the logical address of the storage unit of damaging on the storage chip bitmap that therefore can more accurately obtain the storage unit physical address of actual damage on the storage chip and be tested improves the accuracy of storage unit combination checking.
Description of drawings
Below in conjunction with the drawings and specific embodiments the verification method of storage unit combination of the present invention is made further specific description in detail.
Fig. 1 is the verification method synoptic diagram of storage unit combination of the present invention.
Embodiment
The verification method of the storage unit combination of present embodiment, wherein, the storage unit repeated combination is a storage chip, storage unit is combined to form the storage unit complete structure of storage chip according to certain rules.For whether the combination rule of verifying storage unit on the storage chip of making meets the combination rule of design phase storage unit in advance, just need verify to the storage chip of making.
The checking of the described storage unit combination of present embodiment can effectively guarantee can carry out accurate in locating to the storage unit that lost efficacy in the follow-up test, improves the performance and the yield of storage chip.Usually comprise the active region layer of storage unit, the dielectric layer on active region layer surface and the metal connecting line layer on the dielectric layer on the storage chip.
The verification method of storage unit combination of the present invention is consulted Fig. 1, and may further comprise the steps: step S1: mark is treated damage position on storage chip to be verified.The position that mark is to be damaged among the step S1 is to adopt optical microscope and laser several treat damage position at storage chip mark to be verified.The laser energy that adopt when adopting optical microscope and laser labelling to treat damage position this moment is little, and the damage from laser time is short.Be easy to find when adopting among the subsequent step S2 focused ion beam to make the damage recess under high enlargement ratio for making and treat damage position, the damage position for the treatment of of step S1 institute mark is several, and cluster is at one jiao of storage chip to be verified.Make the damage position cluster for the treatment of of mark mainly contain two effects at storage chip one jiao: one, make step S2 position to be damaged, location fast; Two, after step S4 removes the dielectric layer and metal connecting line layer of surfaces of active regions, the active area of storage unit just is exposed to the surface of chip, if the storage unit active area with square storage chip vertex position is with reference to active area, can determine the accurate position of the storage unit of the relative vertex position of storage unit that actual active area damages so fast.Optical microscope and laser is no longer as making the damage recess in the verification method of storage unit of the present invention combination, only is used for mark to treat damage position, do not influence the operate as normal of the storage unit for the treatment of the damage position correspondence.
Step S2: adopt focused ion beam at the damage recess for the treatment of the damage position making predetermined area and the degree of depth.Its energy of the relative laser of focused ion beam is easy to control, and the relative laser of damaged area is littler, and the lesion depths in the unit interval also can be controlled relatively more accurately.
The damage position for the treatment of that step S2 makes the damage recess is step S1 cluster some one for the treatment of in the damage position together.The relative step 1 of damage recess is made treats that the damage that damage position causes is darker, can cause the inefficacy of the storage unit of correspondence position under the damage recess.Before the test of carrying out step S3, can in the damage recess that step S2 makes, fill metal, can directly cause the word line of damage recess position metal connecting line layer and the short circuit between the bit line like this, be convenient to step S3 and can test the staggered inefficacy that the damage recess causes among the step S2.Filling metal in the damage recess adopts chemical vapour deposition technique to fill.During test, for being different from metal material of copper or the aluminium of making storage chip dielectric layer and metal connecting line layer, the metal of filling the damage recess adopts platinum, tungsten or molybdenum all can.The metal of filling the damage recess in the present embodiment adopts platinum, for realizing the staggered inefficacy of damage recess position, can adopt tungsten or molybdenum to realize equally.Step S3: adopt the test machine test to make the storage chip of damage recess, the storage-unit-failure position that the labeled test machine is tested.But the logical address of the storage unit that the test machine Validity Test that adopts the test storage chip lost efficacy to the storage chip bitmap.
Step S4: the position of removing the dielectric layer and the damage recess that metal connecting line layer determining step S2 makes on active layer surface, memory chip stores unit.When the dielectric layer of removing active layer surface, memory chip stores unit and metal connecting line layer, can see the exact position of the storage unit of the damage active area that exposes clearly.
Step S5: storage unit combination checking is carried out in the storage unit position of the damage recess that storage-unit-failure position that comparison step S3 records and step S4 determine.Be that the storage unit actual physical address that damage recess that whether position of the storage unit of the inefficacy logical address correspondence measured of comparison step S4 is determined with step S4 causes damaging is complementary, so just can verify whether storage unit combination rule is correct on the storage chip of making.Dielectric layer and metal connecting line layer that step S4 removes described storage chip active layer surface adopt wet etching to remove.Wherein, wet etching adopts hydrogen fluoride solution.
The verification method of storage unit of the present invention combination can effectively solve the problem that laser in the traditional verification method easily causes the storage chip global failure by the damage recess that adopts focused ion beam to make the memory chip stores unit.Plated metal in the damage recess of making can improve testing efficiency in the test result after obtaining damaging under the little damaged area like this.Further, dielectric layer by removing active layer surface, memory chip stores unit and metal connecting line layer can determine to damage the exact position that recess causes the storage unit damaged exactly, the comparative result of the logical address of the storage unit of damaging on the storage chip bitmap that therefore can more accurately obtain the storage unit physical address of actual damage on the storage chip and be tested improves the accuracy of storage unit combination checking.
Claims (9)
1, a kind of verification method of storage unit combination rule, described storage unit repeated combination is a storage chip, described storage chip comprise storage unit active area, be formed on the dielectric layer of surfaces of active regions and the metal connecting line layer on the dielectric layer, the verification method of described storage unit combination may further comprise the steps:
Step 1: mark is treated damage position on described storage chip to be verified;
Step 2: adopt focused ion beam at the damage recess for the treatment of the damage position making predetermined area and the degree of depth;
Step 3: adopt the test machine test to make the storage chip of damage recess, the storage-unit-failure position that the described test machine of mark is tested;
Step 4: remove the dielectric layer and the metal connecting line layer on active layer surface, described memory chip stores unit, the position of the damage recess that determining step 2 is made;
Step 5: the position of the damage recess that storage-unit-failure position that comparison step 3 records and step 4 are determined.
2, the verification method of storage unit combination rule according to claim 1 is characterized in that, described step 1 be adopt optical microscope and laser on described storage chip to be verified mark several treat damage position.
As the verification method of storage unit combination rule as described in the claim 2, it is characterized in that 3, several of described mark are treated damage position cluster a jiao at described storage chip to be verified.
As the verification method of storage unit combination rule as described in the claim 3, it is characterized in that 4, the damage position for the treatment of that described step 2 is made the damage recess is the some one treated in damage position of cluster one jiao of described storage chip to be verified.
5, the verification method of storage unit combination rule according to claim 1 is characterized in that, also comprises the step with metal filled damage recess between step 2 and step 3.
6, as the verification method of storage unit combination rule as described in the claim 5, it is characterized in that, adopt the chemical gas-phase method plated metal to fill described damage recess.
As the verification method of storage unit combination rule as described in the claim 5, it is characterized in that 7, the metal of described filling damage recess adopts platinum, tungsten or molybdenum.
8, the verification method of storage unit combination rule according to claim 1 is characterized in that, dielectric layer and metal connecting line layer that described step 4 is removed described storage chip active layer surface adopt wet etching to remove.
As the verification method of storage unit combination rule as described in the claim 8, it is characterized in that 9, described wet etching adopts hydrogen fluoride solution.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200810040356A CN101625904A (en) | 2008-07-08 | 2008-07-08 | Method for verifying storage unit combination rule |
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| CN200810040356A CN101625904A (en) | 2008-07-08 | 2008-07-08 | Method for verifying storage unit combination rule |
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| CN101625904A true CN101625904A (en) | 2010-01-13 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104156325A (en) * | 2014-08-26 | 2014-11-19 | 上海华虹宏力半导体制造有限公司 | Method and device for converting logical address of chip into physical address of chip |
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2008
- 2008-07-08 CN CN200810040356A patent/CN101625904A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104156325A (en) * | 2014-08-26 | 2014-11-19 | 上海华虹宏力半导体制造有限公司 | Method and device for converting logical address of chip into physical address of chip |
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Application publication date: 20100113 |