CN104113383A - Signal reflection annihilation calculating method - Google Patents
Signal reflection annihilation calculating method Download PDFInfo
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- CN104113383A CN104113383A CN201410345747.0A CN201410345747A CN104113383A CN 104113383 A CN104113383 A CN 104113383A CN 201410345747 A CN201410345747 A CN 201410345747A CN 104113383 A CN104113383 A CN 104113383A
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Abstract
The invention discloses a signal reflection annihilation calculating method. The signal reflection annihilation calculating method includes selecting a reflection annihilation example, dividing a delayed signal into a plurality of superposed signals, calculating the reflection condition of each signal, superposing the reflection conditions of all the signals, calculating reflection conditions of the signals through simulation software, and comparing a result calculated through the method with a result calculated through the software. According to signal reflection annihilation calculating method, validity and correctness of the signal reflection annihilation calculating method are fully verified, so that reasons for occurrence of a reflection annihilation phenomenon are fundamentally explained, and recognition and re-understanding of the reflection annihilation phenomenon are facilitated.
Description
Technical field
The present invention relates to a kind of method of calculated signals, specifically a kind of method of calculating signal reflex annihilation, belongs to computerized information field.
Background technology
Since entering 21 century, the clock frequency of electronic product is more and more higher, the signal rate of transmission is also more and more faster, problems of Signal Integrity is more and more outstanding, and designer for solve problems of Signal Integrity and for the time of designing new product shorter and shorter, how fast and effeciently solving problems of Signal Integrity is the difficult problem that design engineer need to face.And the key that solves problems of Signal Integrity is how to accomplish impedance matching, namely how can reduce as much as possible the problem of the reflection being caused by impedance mismatch.
In the time that signal is propagated in transmission line, the transient impedance that signal is experienced changes, and part signal will be reflected back signal source along the direction contrary with the former direction of propagation, and this phenomenon is called reflection.
And in the time that the rise time of signal (Tr) postpones (the propagation time Td of signal on transmission line) much larger than transmission line, reflection can be buried in the rising edge of signal, to such an extent as to reflection exerts an influence hardly to the quality of signal.That is to say as long as enough short (it is generally acknowledged Tr >=10*Td) of transmission line reflected and can be ignored the impact of signal.
For this phenomenon how to understand signal reflex annihilation, there is no method or the explanation of fine understanding all the time yet, in documents and materials, often see reflection and fall into oblivion this word, seldom mention but fall into oblivion about the reflection of signal the reason occurring.
Owing to solving the importance of problems of Signal Integrity for design of electronic products, extremely need a kind of method that signal reflex falls into oblivion of calculating, this has very important significance for the reflex in research signal integrity theory and the design of electronic product.
Summary of the invention
In order to overcome the defect of prior art, better understanding signal reflex falls into oblivion this phenomenon and it is quantized to calculate, to be conducive to solve potential problems of Signal Integrity, the present invention proposes a kind of method that signal reflex falls into oblivion of calculating, and can better explain that by calculating reflection falls into oblivion the reason occurring.
To achieve these goals, the present invention adopts following technical scheme:
Calculate the method that signal reflex falls into oblivion, comprise the following steps:
S1: at input collection signal;
S2: the signal of collection is divided into several sub-signals, and preserves the data of all sub-signals;
S3: according to the electric parameter of circuit, calculate the reflected signal of each sub-signal by reflection computational methods, and preserve the data of all reflected signals;
S4: read the data of reflected signal, relation generates superposed signal chronologically;
S5: the result of calculation of this superposed signal and signal simulation is compared and verified.
Particularly, comprise analog signal and digital signal at the signal of input collection, wherein said analog signal comprises electric current, voltage, and power, frequency, described electric parameter comprises signal source internal impedance, transmission line impedance and load impedance.
Preferably, in step S2, sub-signal is that the signal to gathering carries out producing after dividing potential drop.
Preferably, in step S2, sub-signal is that the signal to gathering produces after by time delay, and wherein said delay is rise time to signal or the delay of fall time.
Preferably, in step S2, the signal after sub-signal stack is identical with the signal of collection.
Preferably, in step S2, the signal of collection produces sub-signal via dividing potential drop deferred mount, and described dividing potential drop deferred mount is comparator or dividing potential drop delay circuit equipment.
Preferably, in step S3, calculate and preserve the data of the reflected signal of each sub-signal via a calculation element, described calculation element comprises memory, and wherein memory is for storing current signal data, electric parameter and the program of carrying out calculating.
Preferably, in step S3, described memory is push-up storage.
Particularly, described memory also stores the database for recording sub-signal and reflected signal data thereof.
Particularly, in step S3, described reflection computational methods are: at signal source Vs, internal impedance Zs, transmission line impedance Z
0, load impedance Z
llink in, sub-signal V
itransmit while arriving load sub-signal (V
i* ρ
l) will be reflected back toward signal source, wherein reflection coefficient ρ
l=(Z
l-Z
0)/(Z
l+ Z
0), be reflected back toward sub-signal (V after signal source
i* ρ
l) signal source generation secondary reflection, the signal (V being reflected by source
i* ρ
l* ρ
s) can propagate to load direction wherein reflection coefficient ρ
s=(Z
s-Z
0)/(Z
s+ Z
0), go successively, until signal stabilization.
Compared with prior art, the present invention has following remarkable advantage and beneficial effect: by the result of calculation contrast of above-mentioned result of calculation and simulation software, fully verify above-mentioned for calculating validity and the accuracy of the method that reflects annihilation, thereby fundamentally explain the reason of the generation of reflection annihilation, contribute to re-recognize and understand reflection annihilation, and being conducive to solve potential problems of Signal Integrity.
Brief description of the drawings
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described further, wherein:
Fig. 1 is according to the schematic process flow diagram of a specific embodiment of the inventive method;
Fig. 2 is according to the primary circuit figure of a specific embodiment of the inventive method;
Fig. 3 is according to the signal reflex schematic diagram of a specific embodiment of the inventive method;
Fig. 4 is according to the Acquisition Circuit figure of a specific embodiment of the inventive method;
Fig. 5 is according to the sub-signal figure of a specific embodiment of the inventive method;
Fig. 6 is according to the sub-signal stacking chart of a specific embodiment of the inventive method;
Fig. 7 is according to the load terminal voltage change curve of a specific embodiment of the inventive method;
Fig. 8 is the load end signal stacking chart according to a specific embodiment of the inventive method;
Fig. 9 is the receiving terminal overlaid waveforms figure according to a specific embodiment of the inventive method;
Figure 10 is according to the generation oscillogram of the ADS simulation software of a specific embodiment of the inventive method; Wherein: W, waveform; T, time.
Embodiment
Fall into oblivion this phenomenon in order better to understand signal reflex, and it is calculated, to contribute to solving problems of Signal Integrity potential in design of electronic products, describe the present invention below with reference to each execution mode shown in the drawings.But these execution modes do not limit the present invention, the conversion in structure, method or function that those of ordinary skill in the art makes according to these execution modes is all included in protection scope of the present invention.
According to a specific embodiment of the present invention, in a link, signal source Vs, source internal impedance Zs, transmission line impedance Z
0, load impedance Z
l, as shown in Figure 2.Signal sends (supposing that signal is that level is a rising edge of Vs) by signal source Vs, and in the time arriving transmission line, due to the existence of internal impedance Zs, signal has carried out dividing potential drop herein, supposes that signal level is V herein
i=Vs*Z
0/ (Z
s+ Z
0) propagation forward of signal continuation afterwards, if load impedance does not mate with transmission line impedance in the time arriving load, can reflect, reflection coefficient is ρ
l=(Z
l-Z
0)/(Z
l+ Z
0), part signal V
i* ρ
lto be reflected can source, now V
r=V
i+ V
i* ρ
l; If source internal impedance Zs and transmission line impedance Z
0do not mate, secondary reflection will occur, reflection coefficient is ρ
s=(Z
s-Z
0)/(Z
s+ Z
0), the signal V being reflected by source
r=V
i* ρ
l* ρ
scan propagate to load direction, go successively, until signal stabilization.
In Fig. 3, abcdef represents respectively the amount that reflect of signal in source and load, ace represents respectively the amount before being reflected for the first time, for the second time, for the third time of load end, bdf represents respectively the amount before being reflected for the first time, for the second time, for the third time of source, ABC represents respectively the level value before source reflects for the first time, for the second time, for the third time, and A ' B ' C ' represents respectively the level value after load end reflects for the first time, for the second time, for the third time.The signal being reflected will be superimposed upon on original signal, thereby the transmission quality of signal is exerted an influence, and reduces as much as possible impedance mismatch for better signal integrity only has, and reduces reflection.In figure, the concrete data relationship calculating is, the volume reflection of signal: a=A, b=a* ρ
l, c=b* ρ
s, d=c* ρ
l, e=d* ρ
s, f=e* ρ
l; Level value before former end reflection: A=a, B=a+b+c, C=a+b+c+d+e; Level value after former end reflection: A'=a, B'=a+b+c+d, C'=a+b+c+d+e+f.
One specific embodiment of the method according to this invention, first chooses an example, and with reference to Fig. 4, it is that 80/3V rising time is the ladder step signal of 20ns that signal source Vs sends a voltage magnitude, and source impedance Zs is 50/3 ohm, transmission line impedance Z
0be 50 ohm, transmission line postpones for 1ns, load impedance Z
lit is 150 ohm.In the time that this signal arrives transmission line, due to transmission line impedance Z
0with the dividing potential drop effect of source internal impedance Zs, this step signal is propagated along transmission line with the level of 20V, and signal can be at source and load end generation multiple reflections afterwards.The method according to this invention comprises the following steps:
S1: at input collection signal, for example, via a dividing potential drop deferred mount, it is comparator or dividing potential drop delay circuit equipment, this collection signal is that a voltage magnitude is that 80/3V rising time is the step signal of 20ns.
S2: it is that 1V rising time is the step signal of 1ns that the rising edge signal of 20V level that propagates into transmission line is divided into 20 level, i.e. first sub-signal V as shown in Figure 5
1=1V, t
1=1ns, wherein 19 step signals below postpone respectively 1ns, 2ns, 3ns with respect to first step ... until 19ns, superpose on the time domain step signal of the 20V/20ns that just equals original of these 20 step signals, i.e. all sub-signal V as shown in Figure 6
iconsistent with original signal Vs feature after stack.These 20 step signals are except postponing, other whole identical, so only need to calculate one of them, then does corresponding delay to other reflection configuration, and by signal data acquisition and be kept in a database, described database can be kept in the memory of a calculation element.The source reflection coefficient of link is ρ
s=(Z
s-Z
0)/(Z
s+ Z
0)=(50/3-50)/(50/3+50)=-0.5, load end reflection coefficient is ρ
l=(Z
l-Z
0)/(Z
l+ Z
0)=(150-50)/(150+50)=0.5.
S3: for example, via the calculation element being connected with this dividing potential drop deferred mount, calculating first rising edge level is that 1V rising time is the reflection case of the step signal of 1ns.Can calculate first step signal and propagate into load end by Reflection formula above time, the voltage waveform that load end receives.Here the time that signal is arrived to transmission line is designated as 0ns, and because the delay of transmission line is 1ns, therefore the time of signal arrival load end is 1ns.Now load end generation primary event, and in 1ns time after this, load terminal voltage will remain unchanged, until the generation of load end secondary reflection, so load terminal voltage V
1=V
0+ V
0* ρ
l=1+1*0.5=1.5V.The time that signal is reflected back source through overload is 2ns, and now signal, in source, primary event also occurs, so load terminal voltage V
2=V
1+ V
0* ρ
l* ρ s=1.5+1*0.5* (0.5)=1.25V.The time that signal arrives load end after secondary reflection again in source is 3ns, and load end secondary reflection now occurs, and in 1ns time after this, load terminal voltage will remain unchanged, until the generation of load end triple reflection, and load terminal voltage is V
3=V
2+ V
0* ρ
l* ρ s* ρ
l=1.25+1*0.5* (0.5) * 0.5=1.125V, the like, and the reflected signal data that calculate are kept in database, load end order of reflection and load are accepted the situation of voltage as following table calculated data.Load end receives voltage, and curve is as shown in Figure 7 over time.
| ? | For the first time | For the second time | For the third time | The 4th time | The 5th time | The 6th time | The 7th time | The 8th time |
| Time | 1ns | 3ns | 5ns | 7ns | 9ns | 11ns | 13ns | 15ns |
| Voltage | 1.5 | 1.125 | 1.21875 | 1.195313 | 1.201172 | 1.199707 | 1.200073 | 1.199982 |
S4: analyze the sequential relationship of these 20 step signals, and superpose.There is load end primary event in first step signal, load end secondary reflection occurs when 3ns in the time of 1ns, and load end triple reflection occurs when 5ns, after the like.Because second step signal is with respect to first step signal delay 1ns, so the time of second step signal generation load end primary event is 2ns, when 4ns, there is load end secondary reflection, when 6ns, there is load end triple reflection, the like learn, there is load end primary event at 20ns in the 20 step signal, load end secondary reflection occurs when 22ns, when 24ns, there is load end triple reflection, after the like.
By above-mentioned analysis, after doing phase delay, the voltage that these 20 step signals can be produced at receiving terminal and the waveform of time superpose.Fig. 8 is first three step signal, is step1, step2 and the step3 schematic diagram in load end stack.20 step signals superpose rear waveform as Fig. 9 at voltage and the waveform of time of receiving terminal generation, and its peak-peak is V
m=24.4799V.
S5: utilize a signal emulation module to carry out emulation to above-mentioned link, to verify feasibility and the accuracy of said method.Signaling module can comprise or move the simulation softwares such as SPICE, EWB, Matlab and ADS.Figure 10 is the voltage and the waveform of time that the load end exported after the above-mentioned link of ADS simulation software emulation receives, and the m1 in figure is in the time of 21.003ns, waveform arrival peak-peak 24.4791V, and signal starts to stablize afterwards.By the result of calculation contrast of above-mentioned hand computation result and simulation software, fully verify above-mentioned for calculating validity and the accuracy of the method that reflects annihilation, thereby fundamentally explain the reason of the generation of reflection annihilation, contribute to re-recognize and understand reflection annihilation, more contributing to solve the problem of signal integrity.
The above, be better calculated examples of the present invention, and the present invention is not limited to above-mentioned account form, as long as it reaches technique effect of the present invention with identical means, all should belong to protection scope of the present invention.
Claims (10)
1. calculate the method that signal reflex falls into oblivion, it is characterized in that, comprise the following steps:
S1: at input collection signal;
S2: the signal of collection is divided into several sub-signals, and preserves the data of all sub-signals;
S3: according to the electric parameter of circuit, calculate the reflected signal of each sub-signal by reflection computational methods, and preserve the data of all reflected signals;
S4: read the data of reflected signal, relation generates superposed signal chronologically;
S5: the result of calculation of this superposed signal and signal simulation is compared and verified.
2. a kind of method that signal reflex falls into oblivion of calculating according to claim 1, it is characterized in that, comprise analog signal and digital signal at the signal of input collection, wherein said analog signal comprises electric current, voltage, power, frequency, described electric parameter comprises signal source internal impedance, transmission line impedance and load impedance.
3. a kind of method that signal reflex falls into oblivion of calculating according to claim 1, is characterized in that, in step S2, sub-signal is that the signal to gathering carries out producing after dividing potential drop.
4. a kind of method that signal reflex falls into oblivion of calculating according to claim 1, is characterized in that, in step S2, sub-signal is that the signal to gathering produces after by time delay, and wherein said delay is rise time to signal or the delay of fall time.
5. a kind of method that signal reflex falls into oblivion of calculating according to claim 1, is characterized in that, in step S2, the signal after sub-signal stack is identical with the signal of collection.
6. a kind of method that signal reflex falls into oblivion of calculating according to claim 1, is characterized in that, in step S2, the signal of collection produces sub-signal via dividing potential drop deferred mount, and described dividing potential drop deferred mount is comparator or dividing potential drop delay circuit equipment.
7. a kind of method that signal reflex falls into oblivion of calculating according to claim 1, it is characterized in that, in step S3, calculate and preserve the data of the reflected signal of each sub-signal via a calculation element, described calculation element comprises memory, and wherein memory is for storing current signal data, electric parameter and the program of carrying out calculating.
8. a kind of method that signal reflex falls into oblivion of calculating according to claim 7, is characterized in that, described memory is push-up storage.
9. according to a kind of method of calculating signal reflex annihilation described in claim 1-8 any one, it is characterized in that, described memory also stores the database for recording sub-signal and reflected signal data thereof.
10. a kind of method that signal reflex falls into oblivion of calculating according to claim 1, is characterized in that, described step S3 reflection computational methods are specially: at signal source (Vs), and internal impedance (Zs), transmission line impedance (Z
0), load impedance (Z
l) link in, sub-signal (V
i) transmit while arriving load sub-signal (V
i* ρ
l) will be reflected back toward signal source, wherein reflection coefficient (ρ
l)=(Z
l-Z
0)/(Z
l+ Z
0), be reflected back toward sub-signal (V after signal source
i* ρ
l) signal source generation secondary reflection, the signal (V being reflected by source
i* ρ
l* ρ
s) can propagate to load direction wherein reflection coefficient (ρ
s)=(Z
s-Z
0)/(Z
s+ Z
0), go successively, until signal stabilization.
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| CN102577190A (en) * | 2009-08-26 | 2012-07-11 | 英国国防部 | Hybrid reflectometer system (HRS) |
-
2014
- 2014-07-18 CN CN201410345747.0A patent/CN104113383A/en active Pending
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| CN1808446A (en) * | 2005-01-22 | 2006-07-26 | 鸿富锦精密工业（深圳）有限公司 | Method of obtaining equivalent model of coupled transmission line in high-speed circuit |
| CN102577190A (en) * | 2009-08-26 | 2012-07-11 | 英国国防部 | Hybrid reflectometer system (HRS) |
| CN102082522A (en) * | 2009-11-26 | 2011-06-01 | 广东易事特电源股份有限公司 | Voltage step controlling method and step wave cascade multilevel inverter |
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