CN104113334A - Multi-mode clock reference source realization device - Google Patents
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Abstract
The present invention discloses a multi-mode clock reference source realization device. The multi-mode clock reference source realization device is composed of a controlled frequency generator, a high quality factor multi-band frequency frequency selective network, a multi-mode frequency divider, an automatic frequency calibration unit, a digital signal-to-analog signal converter, and the like. By setting the control bits of the device, a clock reference source function of a multi-mode output frequency can be realized. While the frequency division coefficients of the multi-mode frequency divider are selected by the control bits, the automatic frequency calibration unit generates the digital control bits to control the work status of the controlled frequency generator by the digital signal-to-analog signal converter. The output of the controlled frequency generator is used as the input of the multi-mode frequency divider for frequency division by the high quality factor multi-band frequency frequency selective network, and then the frequency division is outputted to the automatic calibration unit again. The calibrated clock output is used as the final output of the whole device, and is used as the clock reference source of other electronic devices. The multi-mode clock reference source realization device of the present invention has the advantages of being simple in structure, high in clock precision and low in cost, being easy to realize, etc., and can substitute for the conventional clock reference source device to be widely used in the electronic devices needing clock control.
Description
1. technical field:
The present invention is a kind of multimode timing reference input implement device, and the device that is mainly the various electronic applications such as communication, tester, electronic equipment for consumption provides accurate reference clock.
2. background technology
Along with the develop rapidly of modern communications, control and integrated circuit technique, high stable and high precision timing reference input have become one of critical component determining various electronic system performance qualities.Particularly, in electronic equipment for consumption, constantly reduce costs the direct driving force that also becomes a technical development and breakthrough.In the electronic device improving constantly in integrated level, traditional timing reference input has become bottleneck, all cannot reach the demand of modern electronic equipment and device in manufacture, packaging technology, cost and technical performance.The present invention realizes technically has epoch-making meaning to traditional timing reference input alternative.Particularly solve that output frequency is in the past single, frequency is drifted about in time and cannot realize high frequency reference clock etc. and be badly in need of the technical barrier of breaking through.The device that the present invention proposes has overcome the shortcomings of above traditional timing reference input, is widely used when needed in the electronic equipment of clock system and integrated circuit (IC) products
3. technology contents
Technical problem: in electronic equipment and device, the main a lot of traditional timing reference input adopting cannot carry out the system integration in chip at present, and in the time requiring timing reference input to have higher output frequency, just need proportion phase-locked loop circuit to realize double frequency function, thereby obviously increase equipment cost.Meanwhile, under the requirement of high frequency output, traditional timing reference input production yield also can reduce thereupon greatly.Particularly traditional timing reference input often can only provide single reference clock frequency.
Technical scheme:
The invention discloses a kind of multimode timing reference input implement device, this device is made up of to five parts such as analog signal converters controlled frequency generator, high quality factor multiband frequency-selective network, multi-modulus frequency divider, automatic frequency alignment unit, digital signal.
This device is by realizing the timing reference input function of multimode output frequency to the setting of its control bit.When control bit is selected multi-modulus frequency divider divide ratio, automatic frequency alignment unit produces digital control position, and after analog signal converter, controls the operating state of controlled frequency generator through digital signal.Frequency division is carried out in the output of controlled frequency generator input as multi-modulus frequency divider after high quality factor multiband frequency-selective network, automatic calibration unit is delivered in then this frequency division output again, clock after calibration is output as the final output of whole device, as the timing reference input of other electronic installation.The advantages such as the present invention has simple in structure, and clock accuracy is high, is easy to realize, with low cost; Can replace traditional clock reference source apparatus, when needed extensive use in the electronic equipment of clock system.
Beneficial effect:
It is simple that the present invention has apparatus structure, and output frequency precision is high, be easy to realize in integrated circuit, and the advantage such as with low cost; Can extensively replace traditional clock reference source apparatus, in the electronic equipment of clock system, generally use when needed.
1, the present invention is the reference source device of realizing the output of multimode clock frequency, compared with traditional reference source, output frequency can be set flexibly, has overcome the shortcoming of the single output frequency of traditional reference source.Connect simply, be easy to realize, save power consumption and area simultaneously.
2, the controlled frequency generator in the present invention can produce very high output frequency, and is not subject to the impact of operating time.
3, the installation cost in the present invention is low, and yield is high, has overcome traditional clock reference source apparatus medium frequency the difficult problems such as drift occur with external environment;
The present invention can be integrated in chip and obtain the reference clock that frequency accuracy is high, no longer needs to have outside device to produce reference clock, has reduced cost, is applicable to being very much widely used in each adhesive integrated circuit.
Brief description of the drawings:
Fig. 1 is block diagram of the present invention.
Fig. 2 is the block diagram of realizing of multi-modulus frequency divider and the cascade of automatic frequency alignment unit.
Fig. 3 is controlled frequency generator, the digital signal block diagram of realizing to analog signal converter and the cascade of automatic frequency alignment unit.
Fig. 4 is the block diagram of realizing of high quality factor multiband frequency-selective network and the cascade of automatic frequency alignment unit.
Fig. 5 is the block diagram of realizing of automatic frequency alignment unit.
Fig. 6 is the circuit diagram of the sub-frequency divider of multimode in first and second embodiment.
Fig. 7 be the first embodiment multi-modulus frequency divider realize block diagram.
Fig. 8 is the partial circuit figure of automatic frequency alignment unit in the first embodiment.
Fig. 9 be the second embodiment multi-modulus frequency divider realize block diagram.
Figure 10 is the partial circuit figure of automatic frequency alignment unit in the second embodiment.
Embodiment
Control bit C1, C2...Cn is as the input signal of automatic frequency alignment unit, and these input signals produce corresponding inversion signal through inverter, and input signal and its inversion signal are by n the control bit A1 of logical operation output of gate circuit, A2...An; Then A1, A2...An produces respectively three groups of control bit A11, A12...A1n, A21, A22...A2n, A31, A32...A3n; Control bit C1, C2...Cn directly determines the divide ratio of multi-modulus frequency divider; A1, A2...An controls the output frequency of controlled frequency generator indirectly to analog circuit transducer by digital circuit; A1, A2...An passes through to control A11, A12...A1n, A21, A22...A2n and A31, A32...A3n determines high quality factor multiband frequency-selective network jointly.Therefore, whole device is by control bit C1 is set flexibly, and C2...Cn coordinates the design of concrete unit module that multimode timing reference input can be provided.
Embodiment 1:
In this device, multi-modulus frequency divider is made up of three sub-frequency dividers of multimode, has 8 control bits and is respectively s3, s2, s1, c3, c2, c1, d2, d1.Wherein the combination of the Different Logic of the sub-frequency divider of each multimode can realize N1 frequency division (wherein N1=2,3.4,5); This frequency divider is made up of 4 d type flip flops, 4 inverters, 4 NOR gate, 3 NAND gate, an XOR gate.After three sub-frequency divider cascades of multimode, attainable divide ratio is 40,48,60,64,96,120,128,256 etc.
Control bit s3, s2, s1, c3, c2, c1, d2, d1 as the digital input signals of automatic frequency alignment unit, exports two digital signal A2 by logical circuit simultaneously, A1, wherein the implementation of output terminals A 1 is that input, the inverter 12 of inverter 11 inputted, the output of the output of the output of the input of the output of inverter 13, inverter 15, inverter 16, inverter 17, inverter 18 is as the input of NAND gate 21; The input of the input of the output of the input of inverter 11, the input of inverter 12, inverter 13, the input of inverter 14, inverter 15, the output of inverter 16, inverter 17, the output of inverter 18 are as the input of NAND gate 22; The input of the output of the input of the output of inverter 18, the output of inverter 17, inverter 11, the input of inverter 12, inverter 13, the output of inverter 15, inverter 16 is as the input signal of NAND gate 23; The output of the output of NAND gate 21, the output of NAND gate 22, NAND gate 23 is as the input signal of NAND gate 27, and now the output of NAND gate 27 is the value of A1.The implementation of output terminals A 2 is similar to A1, and final A1A2 is output as ' 00 ', ' 01 ', ' 10 ', ' 11 '.The output frequency of controlled frequency generator is controlled in four kinds of array outputs of A1A2 indirectly to analog circuit transducer by digital circuit.When 00 ' time of A2A1=', whole loop is in resting state, and system does not have frequency output; When 01 ' time of A2A1=', controlled frequency generator is output as f1; When 10 ' time of A2A1=', controlled frequency generator is output as f2; When 11 ' time of A2A1=', controlled frequency generator is output as f3 (f3 is different design frequency for wherein f1, f2).Then f1, f2, the frequency of f3 is as the input signal of high quality factor multiband frequency-selective network, now at A11, A12 and A21, under the control of A22, high quality factor multiband frequency-selective network is selected accurate output frequency f1, f2, f3 in corresponding frequency range.
Output frequency f1, f2, f3 is first as the input of multi-modulus frequency divider 1, and the output signal of multi-modulus frequency divider 1 is as the input signal of multi-modulus frequency divider 2, and the output signal of multi-modulus frequency divider 2 is as the input signal of multi-modulus frequency divider 3.When the digital input signals of automatic frequency alignment unit is s3s2s1=' 110 ', c3c2c1=' 010 ', 00 ' time of d2d1=', the divide ratio of multi-modulus frequency divider is 64, now the digital signal of automatic frequency alignment unit is output as A1A2=' 01 ', the output frequency of controlled frequency generator is f1, this frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, after frequency division, the output of multi-modulus frequency divider is again as the input of automatic frequency alignment unit, and now whole device is output as f1/64; When the digital input signals of automatic frequency alignment unit is s3s2s1=' 110 ', c3c2c1=' 110 ', 000 ' time of d2d1=', the divide ratio of multi-modulus frequency divider is 128, now the digital signal of automatic frequency alignment unit is output as A1A2=' 01 ', the output frequency of controlled frequency generator is f1, this frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, after frequency division, the output of multi-modulus frequency divider is again as the input of automatic frequency alignment unit, and now whole device is output as f1/128; When the digital input signals of automatic frequency alignment unit is s3s2s1=' 110 ', c3c2c1=' 110 ', 00 ' time of d2d1=', the divide ratio of multi-modulus frequency divider is 256, now the digital signal of automatic frequency alignment unit is output as A1A2=' 01 ', the output frequency of controlled frequency generator is f1, this frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, after frequency division, the output of multi-modulus frequency divider is again as the input of automatic frequency alignment unit, and now whole device is output as f1/256.When the digital input signals of automatic frequency alignment unit is s3s2s1=' 111 ', 00 ' time of c3c2c1=' 000 ' d2d1=', the divide ratio of multi-modulus frequency divider is 40, now the digital signal of automatic frequency alignment unit is output as A1A2=' 10 ', the output frequency of controlled frequency generator is f2, this frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, after frequency division, the output of multi-modulus frequency divider is again as the input of automatic frequency alignment unit, and now whole device is output as f2/40; When the digital input signals of automatic frequency alignment unit is s3s2s1=' 111 ', c3c2c1=' 001 ', 00 ' time of d2d1=', the frequency dividing ratio coefficient 60 of multi-modulus frequency divider, now the digital signal of automatic frequency alignment unit is output as A1A2=' 10 ', controlled frequency occur under switch control output frequency be f2, this frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, after frequency division, the output of multi-modulus frequency divider is again as the input of automatic frequency alignment unit, and now whole device is output as f2/60; When the digital input signals of automatic frequency alignment unit is s3s2s1=' 111 ', c3c2c1=' 101 ', 00 ' time of d2d1=', the divide ratio of multi-modulus frequency divider is 120, now the digital signal of automatic frequency alignment unit is output as A1A2=' 01 ', the output frequency of controlled frequency generator is f2, this frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, after frequency division, the output of multi-modulus frequency divider is again as the input of automatic frequency alignment unit, and now whole device is output as f2/120.When the digital input signals of automatic frequency alignment unit is s3s2s1=' 110 ', c3c2c1=' 001 ', 00 ' time of d2d1=', the divide ratio of multi-modulus frequency divider is 48, now the digital signal of automatic frequency alignment unit is output as A1A2=' 11 ', the output frequency of controlled frequency generator is f3, this frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, after frequency division, the output of multi-modulus frequency divider is again as the input of automatic frequency alignment unit, and now whole device is output as f3/48; When the digital input signals of automatic frequency alignment unit is s3s2s1=' 110 ', c3c2c1=' 101 ', 00 ' time of d2d1=', the divide ratio of multi-modulus frequency divider is 96, now the digital signal of automatic frequency alignment unit is output as A1A2=' 12 ', the output frequency of controlled frequency generator is f3, this frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, after frequency division, the output of multi-modulus frequency divider is again as the input of automatic frequency alignment unit, and now whole device is output as f3/96.
Embodiment 2:
In this device, multi-modulus frequency divider is made up of two sub-frequency dividers of multimode and a single mode frequency divider, has 6 control bits, is respectively s3, s2, s1, c3, c2, c1.Single mode frequency divider is made up of two d type flip flops, can realize 4 frequency divisions, and the structure of two sub-frequency dividers of multimode is identical with the structure of the sub-frequency divider of multimode in embodiment 1.
Control bit s3, s2, s1, c3, c2, the c1 while is as the digital input signals of automatic frequency alignment unit, export two digital signal A2 by logical circuit, A1, the implementation of output terminals A 1 is the input as NAND gate 28 of the input signal of inverter 15 and the output signal of inverter 16, the output of the output of inverter 15 and inverter 14 is as the input of NAND gate 27, NAND gate 27, 28 output is as the input of NAND gate 29, the output signal of NAND gate 29 is given NAND gate 26, the input of inverter 11 simultaneously, the input of inverter 12, the output of inverter 13 is as the input signal of NAND gate 26, the output of the output of NAND gate 26 and NAND gate 25 is as the input of NAND gate 31, now the output of NAND gate 31 is the value of A1.The implementation of output terminals A 2 is similar to A1, and final A1A2 is output as ' 00 ', ' 01 ', ' 10 ', ' 11 '.The output frequency of controlled frequency generator is controlled in four kinds of array outputs of A1A2 indirectly to analog circuit transducer by digital circuit.When 00 ' time of A2A1=', whole loop is in resting state, and system does not have frequency output; When 01 ' time of A2A1=', controlled frequency generator is output as f1; When 10 ' time of A2A1=', controlled frequency generator is output as f2; When 11 ' time of A2A1=', controlled frequency generator is output as f3 (f3 is different design frequency for wherein f1, f2).Then f1, f2, the frequency of f3 is as the input signal of high quality factor multiband frequency-selective network, now at A11, A12 and A21, under the control of A22, high quality factor multiband frequency-selective network is selected accurate output frequency f1, f2, f3 in corresponding frequency range.
Output frequency f1, f2, f3 is first as the input of single mode frequency divider, and four frequency division output signals after single mode frequency division are as the input signal of multi-modulus frequency divider.When the digital input signals of automatic frequency alignment unit is s3s2s1=' 110 ', 000 ' time of c3c2c1=', it is 16 that multimode is selected the divide ratio of frequency divider, now the digital signal of automatic frequency alignment unit is output as A1A2=' 01 ', the output frequency of controlled frequency generator is f1, this frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, after frequency division, the output of multi-modulus frequency divider is again as the input of automatic frequency alignment unit, and now whole device is output as f1/64; When the digital input signals of automatic frequency alignment unit is s3s2s1=' 110 ', 010 ' time of c3c2c1=', the divide ratio of multi-modulus frequency divider is 32, now the digital signal of automatic frequency alignment unit is output as A1A2=' 01 ', the output frequency of controlled frequency generator is f1, this frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, after frequency division, the output of multi-modulus frequency divider is again as the input of automatic frequency alignment unit, and now whole device is output as f1/128; When the digital input signals of automatic frequency alignment unit is s3s2s1=' 110 ', 110 ' time of c3c2c1=', the divide ratio of multi-modulus frequency divider is 64, now the numeral of automatic frequency alignment unit is output as A1A2=' 01 ', the output frequency of controlled frequency generator is f1, this frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, after frequency division, the output of multi-modulus frequency divider is again as the input of automatic frequency alignment unit, and now whole device is output as f1/256.When the digital input signals of automatic frequency alignment unit is s3s2s1=' 011 ', 000 ' time of c3c2c1=', the divide ratio of multi-modulus frequency divider is 10, now the digital signal of automatic frequency alignment unit is output as A1A2=' 10 ', the output frequency of controlled frequency generator is f2, this frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, after frequency division, the output of multi-modulus frequency divider is again as the input of automatic frequency alignment unit, and now whole device is output as f2/40; When the digital input signals of automatic frequency alignment unit is s3s2s1=' 011 ', 001 ' time of c3c2c1=', the divide ratio of multi-modulus frequency divider is 15, now the digital signal of automatic frequency alignment unit is output as A1A2=' 10 ', the output frequency of controlled frequency generator is f2, this frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, after frequency division, the output of multi-modulus frequency divider is again as the input of automatic frequency alignment unit, and now whole device is output as f2/60; When the digital input signals of automatic frequency alignment unit is s3s2s1=' 111 ', 101 ' time of c3c2c1=', the divide ratio of multi-modulus frequency divider is 30, now the digital signal of automatic frequency alignment unit is output as A1A2=' 01 ', the output frequency of controlled frequency generator is f2, this frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, after frequency division, the output of multi-modulus frequency divider is again as the input of automatic frequency alignment unit, and now whole device is output as f2/120.When the digital input signals of automatic frequency alignment unit is s3s2s1=' 010 ', 001 ' time of c3c2c1=', the divide ratio of multi-modulus frequency divider is 12, now the digital signal of automatic frequency alignment unit is output as A1A2=' 11 ', the output frequency of controlled frequency generator is f3, this frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, after frequency division, the output of multi-modulus frequency divider is again as the input of automatic frequency alignment unit, and now whole device is output as f3/48; When the digital input signals of automatic frequency alignment unit is s3s2s1=' 110 ', 001 ' time of c3c2c1=', the frequency dividing ratio coefficient of multi-modulus frequency divider is 24, now the digital signal of automatic frequency alignment unit is output as A1A2=' 12 ', the output frequency of controlled frequency generator is f3, this frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, after frequency division, the output of multi-modulus frequency divider is again as the input of automatic frequency alignment unit, and now whole device is output as f3/96.
Claims (4)
1. the invention discloses a kind of multimode timing reference input implement device, this device is made up of to five parts such as analog signal converters controlled frequency generator, high quality factor multiband frequency-selective network, multi-modulus frequency divider, automatic frequency alignment unit, digital signal.
This device is by realizing the timing reference input function of multimode output frequency to the setting of its control bit.When control bit is selected multi-modulus frequency divider divide ratio, automatic frequency alignment unit produces digital control position, and after analog signal converter, controls the operating state of controlled frequency generator through digital signal.Frequency division is carried out in the output of controlled frequency generator input as multi-modulus frequency divider after high quality factor multiband frequency-selective network, automatic calibration unit is delivered in then this frequency division output again, clock after calibration is output as the final output of whole device, as the timing reference input of other electronic installation.
2. multimode timing reference input implement device according to claim 1, it is characterized in that at control bit C1, when C2...Cn determines multi-modulus frequency divider divide ratio, automatic frequency alignment unit is also at C1, under the control of C2...Cn, produce set of number control bit A1, A2...An by logic control circuit.Multi-modulus frequency divider can be realized it by single mode frequency divider and the sub-frequency divider cascade of multimode and realize simple in structure and mode of operation flexible operation.Control bit C1, C2...Cn, as the input signal of multi-modulus frequency divider, can realize different divide ratios by different combinations, and the structure of sub-frequency divider, number, cascade system are determined by the divide ratio of needs.Control bit C1, C2...Cn is simultaneously as automatic frequency alignment unit input signal, and these signals produce corresponding inversion signal through inverter, and input signal and its inversion signal are exported multiple control bit A1, A2...An by gate circuit logical operation; Like this, at same group of control bit C1, under C2...Cn controls, the frequency dividing ratio of multi-modulus frequency divider and the output of the digital signal of automatic frequency alignment unit have been determined simultaneously.
3. multimode timing reference input implement device according to claim 1, the output frequency that it is characterized in that controlled frequency generator be by automatic frequency alignment unit by control bit C1 is set, C2...Cn produce control bit A1, A2...An determine.
Control bit C1, C2...Cn is as the input signal of automatic frequency alignment unit, and these signals produce corresponding inversion signal through inverter, and input signal and its inversion signal are exported multiple control bit A1, A2...An by gate circuit logical operation; Control bit A1, the Different Logic combination of A2...An is the input signal to analog signal converter as digital signal, determines the output frequency of controlled frequency generator, and this characteristic has ensured that controlled frequency generator has wider operating frequency range.Like this, at same group of control bit C1, under C2...Cn controls, the output frequency of controlled frequency generator and the output of the digital signal of automatic frequency alignment unit have been determined simultaneously.
4. multimode timing reference input implement device according to claim 1, the Frequency Band Selection that it is characterized in that high quality factor multiband frequency-selective network be by automatic frequency alignment unit by control bit C1 is set, C2...Cn produce control bit A1A2...An determine.In high quality factor multiband frequency-selective network, inductance, electric capacity and variable capacitance are to be realized by switched inductors array, switched capacitor array and switched varactor array, and different switch combination settings can obtain different frequency-selecting frequency ranges.Control bit C1, C2...Cn, as the input signal in automatic frequency alignment unit, can produce different digital signal A1, A2...An under different logic controls; Then A1, A2...An, as the input signal of three Different Logic circuit, produces respectively three groups of digital signal A11, A12...A1n, A21, A22...A2n and A31, A32...A3n.Wherein A11, the switch of A12...A1n control switch capacitor array, A21, the switch of A22...A2n control switch electric inductance array, A31, A32...A3n controls the switch of variable capacitance array.
Like this, at same group of control bit C1, under C2...Cn controls, the Frequency Band Selection of high quality factor multiband frequency-selective network and the output of the digital signal of automatic frequency alignment unit have been determined simultaneously.Now, the output signal of the wide-band of controlled frequency generator output can obtain frequency output accurately after high quality factor multiband frequency-selective network, this output frequency is as the input signal of multi-modulus frequency divider, under the effect of corresponding divide ratio, realize accurate frequency division, output frequency after frequency division is delivered to automatic calibration unit again, and the clock after calibration is output as the final output of whole device.
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| CN112994682A (en) * | 2021-05-10 | 2021-06-18 | 上海灵动微电子股份有限公司 | Clock frequency divider, microcontroller and phase-locked loop circuit based on switched capacitor |
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| CN1196608A (en) * | 1997-04-11 | 1998-10-21 | 三星电子株式会社 | Digital processing phase lock loop for synchronous digital micro-wave apparatus |
| US20070132515A1 (en) * | 2005-12-08 | 2007-06-14 | Lee Ja Y | Wide-band multimode frequency synthesizer and variable frequency divider |
| CN102006095A (en) * | 2010-10-21 | 2011-04-06 | 华东师范大学 | Automatic frequency calibration channel selection filter for multi-frequency multi-mode wireless transceiver |
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| CN1196608A (en) * | 1997-04-11 | 1998-10-21 | 三星电子株式会社 | Digital processing phase lock loop for synchronous digital micro-wave apparatus |
| US20070132515A1 (en) * | 2005-12-08 | 2007-06-14 | Lee Ja Y | Wide-band multimode frequency synthesizer and variable frequency divider |
| CN102006095A (en) * | 2010-10-21 | 2011-04-06 | 华东师范大学 | Automatic frequency calibration channel selection filter for multi-frequency multi-mode wireless transceiver |
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| CN112994682A (en) * | 2021-05-10 | 2021-06-18 | 上海灵动微电子股份有限公司 | Clock frequency divider, microcontroller and phase-locked loop circuit based on switched capacitor |
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