CN1196608A - Digital processing phase lock loop for synchronous digital micro-wave apparatus - Google Patents
Digital processing phase lock loop for synchronous digital micro-wave apparatus Download PDFInfo
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- CN1196608A CN1196608A CN 97110527 CN97110527A CN1196608A CN 1196608 A CN1196608 A CN 1196608A CN 97110527 CN97110527 CN 97110527 CN 97110527 A CN97110527 A CN 97110527A CN 1196608 A CN1196608 A CN 1196608A
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Abstract
A digital processing phase lock loop for stably construction of an initial network synehronous by diversifying a period of phase control comprising: a reference clock receiving unit for receiving electric or optical signal of 8KH2, a phase comparator for comparing the reference clock outputted from the reference clock receiving unit with a self-clock fedback, a phase control unit for performing a phase control auording to the period of phase control corresponding to each predetermined mode, outputting data of 16 bits, a signal converter for covnverting the data of 16 bits into an analog signala VCO for operating by inputting the analog signal according to instantaneous frequency, and a frequency divider.
Description
The present invention generally speaking relates to the synchronous microwave transmitter, more particularly, relates to a kind of digital processing phase-locked loop that carries out synchronization timing and at this moment produce Phase synchronization speed when getting in touch with other communication network.
Usually, as shown in fig. 1, the digital processing phase-locked loop of synchronous microwave transmitter is made up of following each several part: reference clock receiving element 2, phase comparator 4, carry out the microprocessor 6 of phase control, D/A 8, VCO (voltage-controlled type oscillator) 10 and frequency divider 12.Be added on the reference clock receiving element 2 as if the crosspoint of the reference clock that resembles 8 kilo hertzs of signals of telecommunication or light signal and so on from external signal input unit or above-mentioned digital processing phase-locked loop, reference clock receiving element 2 just is added to it on phase comparator 4 after receiving this reference clock.Phase comparator 4 carries out bit comparison mutually with reference clock with the clock signal of feeding back at output of removing at frequency divider 12 usefulness N then, thereby detects phase difference between the two, and detected value is exported to microprocessor 6.At this moment, the data of output are generally got 8 binary digits.Microprocessor 6 carries out phase control so that carry out phase-lockedly, and encircles pass filter to suppress shake, outputs it to D/A 8 again.For example, can adopt the 80C51 chip as microprocessor 6.D/A 8 will convert analog signal to from the digital signal of microprocessor 6 outputs, again it will be added to VCO10.Import analog signal according to its instantaneous frequency during VCO10 work.Phase-lockedly when working, VCO10 carries out.Here, do not finish as if phase-locked.The output of VCO10 is just constantly fed back through frequency divider 12, thereby finally finishes phase-locked task.Signal is added to the processing unit of transmitter by the processor associative unit after phase-locked.
As mentioned above, prior art adopts microprocessor to carry out phase-locked.Yet, since prior art to answering speed slow, generally wanted for 8 seconds, thereby in the digital microwave transmitter, will form hypotactic path and need time more than 30 minutes.In addition, prior art has such shortcoming, and promptly except that phase comparator 4, remaining assembly all is contained in the outside as independent circuits, thereby needs very wide circuit board in the digital processing phase-locked loop.
Therefore, the objective of the invention is to spread out and provide the network arrangements for initial synchronisat constitutionally stable a kind of digital processing phase-locked loop by cycle with phase control.
Another object of the present invention provides a kind of digital processing phase-locked loop of using for phase alignment under definition status and benchmark swap status.
Consult following detailed description in conjunction with the accompanying drawings and be understood that above-mentioned and various other characteristics of the present invention and advantage.In the accompanying drawing:
Fig. 1 is the block diagram of the digital processing phase-locked loop of prior art synchronous microwave transmitter,
Fig. 2 is the block diagram of the digital processing phase-locked loop of synchronous microwave transmitter of the present invention;
Fig. 3 is the oscillogram of the signal of input phase comparator of the present invention.
Describe most preferred embodiment of the present invention in detail referring to accompanying drawing below.
Should be noted that, even same element is also represented with same numbering shown in the accompanying drawing that separates.In addition, in the following description, for more fully understanding the present invention, details to individual elements of physical circuit etc. has all been done detailed description, but the experts in present technique field obviously know, can implement the present invention too not according to the explanation of these details.In addition, to those known function and CONSTRUCTED SPECIFICATION, explanation no longer in detail can make theme of the present invention thicken because do like that on the contrary here.In addition, the used concrete term of inventor also can change, and these terms consider that its effect in the present invention or invention practice names, and therefore this name is made by whole contents of the present invention.
Fig. 2 is the block diagram of synchronous microwave transmitter digital processing phase-locked loop of the present invention.Referring to Fig. 2, the present invention adopts the FPGA (through the gate array of filing and programming) that is made up of reference clock receiving element 22, phase comparator 24 and phase control unit 26 to design.
At the host exchange place, reference clock receiving element 22 of the present invention comprises the E1 associative unit of getting in touch with the 2EA each point and has the E1 generating unit of E1 framer.In addition, also have a circuit unit, can get in touch with the clock that 155M (megaton) light that transmits from other NE (network components) and the signal of telecommunication extract.Have, the subordinate switch is got in touch with the clock that 155M (megaton) signal of telecommunication that sends from central station extracts again.At this moment, get 8 kilo hertzs from the reference clock of reference clock receiving element 22 outputs.If 8 kilo hertzs of electricity or light signal as reference clock are added to reference clock receiving element 22, then the reference clock receiving element is added to the signal of receiving on the phase comparator 24 after receiving this signal.
As shown in Figure 3, phase comparator 24 of the present invention with 8 kilo hertzs reference clock with compare by the self-clocking of counter clock (i.e. 51.47 nanoseconds the cycle) feedback of 19.44 megahertzes by frequency divider 32, and produce the phase detection information of 8 binary digits.Then, this phase detection information is added on the phase control unit 26.
Phase control unit 26 carries out phase control so that phase-locked, and encircles pass filter to suppress jitter phenomenon, signal is sent to D/A 28 again.For example, the design instruction of phase control unit 26 of the present invention can be done following use, wishes that promptly FPGA (IC10) has 10,000 sizes and 8 binary digit word lengths.In addition, there is 1 millisecond of mode to 8 second mode in the cycle of phase control unit.
1 millisecond of mode is used under the ultrahigh speed, and 10 milliseconds of modes are used at a high speed down.In addition, 1 second mode to 8 second mode also can be determined the cycle of phase control by the situation of network synchronous device.Particularly, under 8 seconds modes, have the characteristics of leisure, thereby do not produce phase transformation.Therefore, 8 seconds modes are used when suppressing shake.For this reason, at microwave crosspoint place, when exchange was not made mistakes, the phase difference of allowing can successfully be compensated.In these cases, 8 seconds modes are called " lock mode ".The phase-locked speed that the cycle of above-mentioned phase control produces makes the network synchronous device of microwave transmitter can hand over hand keep synchronous.
So the data of 16 binary digits input to D/A 28 from phase control unit 26, be added on the VCO 30 after converting the digital signal of phase control unit 26 output to analog signal by D/A 28.Import analog signal by its instantaneous frequency during VCO 30 work.Phase-lockedly finish during promptly by VCO 30 work.Here, if phase-locked not finishing, the output of VCO 30 is just constantly fed back through frequency divider 32, thereby finally finishes phase-locked task.Finish phase-locked signal is added to transmitter by the processor associative unit processing unit.
The D/A switch binary digit of D/A 28 of the present invention is decided to be 16.In addition, the central frequency of VCO 30 of the present invention is 155.520 megahertzes, and the scope of FREQUENCY CONTROL is got ± 1555.2 He Zhi.In addition, the minimum frequency control range gets 3.05 * 10
-10He Zhi.
In sum, the present invention produces phase-locked speed by disperseing phase place control cycle and employing FPGA, and therefore, the present invention has such advantage, promptly can make network stabilization ground reach initial synchronous regime in synchronous microwave equipment.
With regard to some specific embodiments content of the present invention has been described above, but this only is for example, should not be considered as limitation of the present invention.Do not breaking away under spirit of the present invention described in the appended claims and the scope prerequisite, the experts in present technique field can carry out various modifications to the foregoing description.
Claims (3)
1. a kind of digital processing phase-locked loop of synchronous microwave transmitter is characterized in that comprising:
A reference clock receiving element is for 8 kilo hertzs electricity or the light signal as the reference clock that receive from external signal input unit or crosspoint;
A phase comparator in order to the described reference clock of described reference clock receiving element output is compared with the self-clocking that feeds back by 19.44 megahertz counter clocks, produces the phase detection information of 8 binary digits then;
A phase control unit, in order to according to phase control corresponding to each predetermined way-ultrahigh speed mode, high speed mode and low speed mode-cycle carry out phase control, import described phase detection information simultaneously, thereby and export 16 binary digit data in order to encircle pass filter to suppress shake;
A signal converter is in order to convert described 16 binary digit data to analog signal;
A VCO (voltage-controlled type oscillator) is in order to import described analog signal according to its instantaneous frequency; With
A frequency divider, in order to divide the output frequency of described VCO by predetermined way, then with described frequency feedback through frequency division, thereby to the motor synchronizing signal of 8 kilo hertzs of described phase comparator outputs.
2. digital processing phase-locked loop as claimed in claim 1 is characterized in that, described reference clock receiving element, described phase comparator and described phase control unit are designed to FPGA together.
3. digital processing phase-locked loop as claimed in claim 1, it is characterized in that, described phase control unit is decided to be the phase control cycle 1 millisecond of mode under ultrahigh speed, under high speed, be decided to be 10 milliseconds of modes, in the time determining its described cycle, be decided to be 1 second to 8 seconds mode by the state of network synchronous device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 97110527 CN1105420C (en) | 1997-04-11 | 1997-04-11 | Digital processing phase lock loop for synchronous digital micro-wave apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 97110527 CN1105420C (en) | 1997-04-11 | 1997-04-11 | Digital processing phase lock loop for synchronous digital micro-wave apparatus |
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| Publication Number | Publication Date |
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| CN1196608A true CN1196608A (en) | 1998-10-21 |
| CN1105420C CN1105420C (en) | 2003-04-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 97110527 Expired - Fee Related CN1105420C (en) | 1997-04-11 | 1997-04-11 | Digital processing phase lock loop for synchronous digital micro-wave apparatus |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1286530B (en) * | 1999-11-12 | 2010-06-02 | 中兴通讯股份有限公司 | Method for implementing digital phase-locked loop in clock synchronizing system |
| CN104113334A (en) * | 2013-04-17 | 2014-10-22 | 苏州芯通微电子有限公司 | Multi-mode clock reference source realization device |
-
1997
- 1997-04-11 CN CN 97110527 patent/CN1105420C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1286530B (en) * | 1999-11-12 | 2010-06-02 | 中兴通讯股份有限公司 | Method for implementing digital phase-locked loop in clock synchronizing system |
| CN104113334A (en) * | 2013-04-17 | 2014-10-22 | 苏州芯通微电子有限公司 | Multi-mode clock reference source realization device |
| CN104113334B (en) * | 2013-04-17 | 2018-03-30 | 苏州芯通微电子有限公司 | Multimode timing reference input realization device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1105420C (en) | 2003-04-09 |
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