CN1286530B - Method for implementing digital phase-locked loop in clock synchronizing system - Google Patents
Method for implementing digital phase-locked loop in clock synchronizing system Download PDFInfo
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- CN1286530B CN1286530B CN 99117206 CN99117206A CN1286530B CN 1286530 B CN1286530 B CN 1286530B CN 99117206 CN99117206 CN 99117206 CN 99117206 A CN99117206 A CN 99117206A CN 1286530 B CN1286530 B CN 1286530B
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Abstract
A method for realizing the digital phase-locked loop in clock synchronizing system includes judging if it is locked, continuously tracking if it is or continuously trapping if it is not, switching to trapping parameters in more narrow band if the clock in near to locking or switching to those in more broad band if it is not trapped, judging if it is unlocked in tracking, switching to clock source and changing to trapping parameters in more narrow band if it is, and executing low-pass method and outputting if it is not. Its advantages are fast and smooth capture of clock source.
Description
The present invention relates to the clock system of communication transmission field, especially relate to high-performance clock synchro system digital phase-locked loop implementation method.
High performance clock system is that any communication transmission field is requisite, and has determined the performance of whole transmission system to a great extent, can be referred to as the heart of transmission system.Clock system is based on the synchronization principles of phase-locked loop, follow the tracks of the reference clock source of a high accuracy, high stability, after output frequency and incoming frequency compare through phase place (frequency), draw one and differ (difference on the frequency) value, pass through the low-pass filtering method again, remove to control high performance voltage controlled oscillator (VCXO), make that finally the strict maintenance of output frequency and incoming frequency is identical.And in the middle of this most critical be exactly the low-pass filtering method, i.e. phase-locked loop method.The quality of method will directly influence the rapidity of clock seizure, the accuracy and the stability of clock tracing.Phase-locked loop method generally all adopts several groups of parameters: catch parameter for two groups, one group of tracking parameter is wherein caught parameter catching range very big (proportionality coefficient is very big) for first group, and the corresponding clock jitter that causes is also very big; And second group of seizure parameter catching range dwindled, and the corresponding clock jitter that causes is also smaller.And traditional phase-locked loop method is when losing lock or switching clock source, all adopt first group of the non-constant width of pull-in range to catch parameter at once, because parameter and tracking parameter differ greatly, and cause clock to produce violent frequency change and shake in capture-process, the probability that error code produces increases greatly.Traditional clock system, pull-in time are also long, generally are no less than half a minute, and what have reaches 3 minutes even longer, and the accuracy of clock tracing and stability are not ideal enough, and this will influence real-time, accuracy and the stability of data traffic transmission.
Purpose of the present invention just is to provide a kind of new digital phase-locked loop implementation method, and the seizure parameter is organized in adaptive control more, shortens the time that digital phase-locked loop is caught greatly, for all kinds of transmission systems provide a high performance clock system.
To achieve these goals, digital phase-locked loop implementation method of the present invention may further comprise the steps:
1) after the phase-locked loop program begins, at first reads the phase difference between input reference source and the output clock, make comparisons, judge whether clock locks with last phase difference;
2), then continue to follow the tracks of the input reference source if present clock locks; Execution in step 4);
3) if also not locking of present clock needs to continue to catch; In continuing capture-process, the self adaptation switching of catching parameter has two kinds of situations:
If a input reference source is approaching with the frequency of output clock, is i.e. during clock approach locking, automatically switches to the narrower seizure parameter of pullin banwidth and catch execution in step 5);
If b has worsened seriously in original in some cases clock source, clock source, front and back difference is very big, when taking place to adopt current seizure parameter to catch within a certain period of time, automatically switch to the wideer seizure parameter of pullin banwidth and catch execution in step 5) less than the input clock source;
4) in tracing process, need judge whether because clock source deterioration etc. is former thereby cause the clock losing lock, if losing lock then needs switching clock source, and change that to catch parameter be the narrowest parameter of pullin banwidth, return step 1); If there is not losing lock, then execution in step 5);
5) calculate corresponding dac value (DA) according to the phase demodulation difference, remove to control VCXO (VCXO) after converting aanalogvoltage to, return step 1) after waiting for a period of time.
In above-mentioned phase-locked loop implementation method, in order to satisfy various system requirements, parameter can have a lot of groups, and allows the car following-theory value to have than large deviation.Can pass through Theoretical Calculation, and in conjunction with the practical application circuit, what provide the most suitable system respectively organizes parameter.
After phase-lock technique improved, the present invention was before and after switching during used clock source, as far as possible near original parameter that adopts; In capture-process, adopt the parameter adaptive method, each group of flexible configuration is caught parameter, makes calling program can catch, capture smoothly new clock source fast.Phase-locked loop pull-in time therefore of the present invention is short, and the output clock is accurate, stable, and the clock source is switched level and smooth, the timing synchronization performance excellence.
Below in conjunction with accompanying drawing and specific embodiment the present invention is done further detailed description.
Fig. 1 is a second order digital phase-locked loop model schematic diagram;
Fig. 2 is the schematic diagram of the specific implementation of digital phase-locked loop;
Fig. 3 is improved phase-lock technique schematic flow sheet;
Fig. 4 is an example flow chart of improving phase-locked program.
Present embodiment adopts traditional second order two type digital phase-locked loops.The Mathematical Modeling of second order digital phase-locked loop as shown in Figure 1.
F among the figure (s) is the transfer function of low pass filter, and Kv is a loop gain.F (s)=1+a/s, a are integral coefficient.The closed loop transfer function, of phase-locked loop is:
H(s)＝θ
0(s)/θ
i(s)＝(2ξωs+ω
2)/(s
2+2ξωs+ω
2)
ξ in the formula=(Kv/4a)
1/2, ω=(aKv)
1/2ξ is a damping coefficient, and ω is a free oscillation frequency.
As long as ξ, ω are selected, can obtain Kv and a value by last two formulas.
As can be seen, H (s) has low-pass characteristic, and is proper as long as ξ, ω select, the just shake of filtering input phase preferably.Narrow bandwidth (ξ, ω product little) can effectively suppress shake, locked-center frequency exactly, but follow-up control is poor, generally is used in when catching; Increased bandwidth (ξ, ω product big) can improve follow-up control, but cause bigger phase jitter, generally is used in when following the tracks of.
Actual phase lock circuitry model as shown in Figure 2.Wherein Programmable Logic Controller is finished phase demodulation (position A among Fig. 2), and CPU finishes phase-lock technique (position B among Fig. 2), exports digital to analog converter D/A control VCXO crystal oscillating circuit (position C among Fig. 2) to through conversion.
Wherein, the transfer function of low pass filter and the conversion method of various parameters (being phase-locked program) realize by CPU, promptly among Fig. 2 shown in the B of position.Km be digital phase discriminator differ the conversion coefficient of counting output value to phase difference; K θ is a discriminator sensitivity; Kn is the digitlization conversion coefficient of VCXO control voltage; Kf is the voltage-controlled sensitivity of voltage controlled oscillator.Kf, K θ has following relation between the Kv:
Kv＝Kf·Kθ
To selected voltage controlled oscillator, Kf is known, and Kv can determine by selected ξ, ω, determine K θ by following formula again.After the clock frequency of digital phase discriminator was determined, Km also promptly determined.After the resolution of digital to analog converter was determined, Kn determined thereupon.
Km, K θ, Kn can be merged into Kd, then Kd=KmK θ Kn.
Theoretical and experimental analysis shows, selects bigger proportionality coefficient Kd, moderate integral coefficient a when catching soon, can enter tracking mode quickly; Then less Kd, a of choosing can improve the drift tracking ability when following the tracks of, and considers better and removes shake.Phase-locked loop method generally all adopts two groups to catch parameter, one group of tracking parameter, wherein catches parameter catching range very big (proportionality coefficient Kd is very big) for first group, and the corresponding clock jitter that causes is also very big; And second group of seizure parameter catching range dwindled, and the corresponding clock jitter that causes is also smaller.And phase-locked loop method in the past is when losing lock or switching clock source, all adopts first group to catch parameter at once, to frequency near the time transform second group of seizure parameter again into.Though the non-constant width of pull-in range because parameter and tracking parameter differ greatly, causes clock to produce violent frequency change and shake in capture-process, the probability that error code produces increases greatly, and it is longer that pull-in time also becomes.
Pull-in time is short in order to make, the switching of clock source is level and smooth, and the present invention adopts many group parameters, and adopts the phase-locked loop method of adaptive control parameter, and its flow process illustrates that as shown in Figure 3 general steps is as follows:
After the phase-locked loop program began, step 301 at first read the phase difference between input reference source and the output clock, makes comparisons with last phase difference, and step 302 judges whether clock locks.If twice phase difference is identical, illustrate that then the input reference source is identical with the frequency of output clock, promptly clock locks, execution in step 304, the output clock is as long as continuation tracking input reference source is just passable.If twice phase difference is inequality, illustrate that then the input reference source is inequality with the frequency of output clock, i.e. also not locking of clock needs to continue to catch.In continuing capture-process 303, the self adaptation switching of catching parameter has two kinds of situations: if 1. the input reference source is approaching with the frequency of output clock, i.e. clock approach locking then automatically switches to the narrower seizure parameter of pullin banwidth and catches; If has worsened seriously in 2. original in some cases clock source, clock source, front and back difference is very big, when taking place to adopt current seizure parameter to catch less than the input clock source within a certain period of time, Automatic Program switches to the wideer seizure parameter of pullin banwidth and catches; Execution in step 307 then.After above-mentioned tracing process 304, step 305 need judge whether that if losing lock, then step 306 promptly needs switching clock source because clock source deterioration etc. is former thereby cause the clock losing lock, and changes that to catch parameter be the narrowest parameter of pullin banwidth, returns step 301; If there is not losing lock, then execution in step 307, carry out low circulation method and export the result, return step 301 after waiting for a period of time.
For example, for following real system (hardware environment):
A) phase demodulation counting clock frequency: 70MHz;
B) D/A precision: 16;
C) VCXO nominal frequency: 19.44MHz; Voltage range: 0.5～4.5V; Voltage-controlled scope: ± 9ppm;
D) than phase frequency: 8kHz.
E) CPU 78C32 dominant frequency: 16.384MHZ
If native system uses conventional methods, parameter and theoretical value are more approaching, are respectively:
Catch parameter 1; Proportionality coefficient Kd=0.9282, integral coefficient a=4.95e-3;
Catch parameter 2: proportionality coefficient Kd=0.4243, integral coefficient a=247e-4;
Tracking parameter: proportionality coefficient Kd=0.042, integral coefficient a=7e-6;
From beginning to capture the total time that enters tenacious tracking is 43 seconds; The clock source has error code to produce when switching; Shake and jitter transfer function are not very desirable.
At said system, present embodiment adopts the proportionality coefficient bigger than conventional phase locked loops in order to shorten pull-in time; Clock jitter in order to reduce to follow the tracks of adopts the integral coefficient littler than conventional phase locked loops.Calculate and the side circuit application experiment by theory analysis,, obtain to improve later phase-lock technique parameter for said system:
Catch parameter for first group: proportionality coefficient Kd=102.5, integral coefficient a=0.0068;
Catch parameter for second group: proportionality coefficient Kd=76.4, integral coefficient a=0.00053;
Tracking parameter: proportionality coefficient Kd=60.8, integral coefficient a=0.00000049;
As previously mentioned, generally when switching clock source, the difference in clock source own is little, and method is very responsive to the discriminating of clock deterioration situation, so used clock source frequency is more or less the same before and after switching, there is no need to adopt first group to catch parameter, as long as adopt second group catch parameter just can be gently and to capture, because second group is caught parameter near tracking parameter, so the variation of handoff procedure clock smoothly with lifting, frequency does not almost change, and has stopped the possibility that error code produces.Certainly, consider that the clock source is worsened serious in some cases, clock source, front and back difference is very big, so when taking place to adopt second group of seizure parameter to catch within a certain period of time less than the input clock source, program can automatically switch to first group of seizure parameter and catch, and guarantees to capture quickly and accurately the input clock source.
Program circuit after the improvement is (Fig. 3 is the concrete refinement of Fig. 2) as shown in Figure 3: at first execution in step 401, judge whether to detecting for the first time input clock benchmark and the phase difference of exporting clock.If for the first time, then execution in step 402,403, read the phase demodulation initial value, and establish that to catch parameter be first group of parameter (promptly catching 1 soon), make catching range big, and pull-in time is short; If not for the first time, then execution in step 404, read and calculate the phase demodulation value, calculate the phase demodulation difference twice according to a preceding phase demodulation value.Step 405 judges whether to catch 1 state soon near input reference source and current being in then, if condition satisfies, then execution in step 416, phase-locked loop seizure parameter is changed into catch 2 soon, carries out 406 again.If condition does not satisfy, then directly carry out 406 and judge whether locking.If not locking, then step 407 judges whether to be in second group of parameter state (promptly catching 2 soon).Catch 2 soon if not being in, then execution in step 415, calculate corresponding dac value (DA) according to the phase demodulation difference, convert to remove to control VCXO (VCXO) behind the aanalogvoltage and return; Catch 2 soon if be in, then execution in step 408, judged whether to carry out to catch 2 soon more than 30 times.If less than 30 times, then execution in step 415, also export corresponding DA value, and if exceeded 30 times, then explanation is caught 2 seizure soon and had been lost efficacy, in order to reduce pull-in time, step 409 transfers to automatically catches 1 soon.At above-mentioned steps 406 places, if judge and to lock, then to put parameter current be tracking parameter to step 410.Step 411 judges whether losing lock then, and promptly whether the difference of input and output clock skew is greater than threshold values (then illustrating clock when the long-term follow input clock a reference source greater than threshold values, because worsen or the other reasons losing lock in the clock source); If losing lock, then step 412,413 is switched corresponding clock source according to concrete needs, and is changed to second group and catches parameter catching a parameter, gets back to step 401; If there is not losing lock, then execution in step 414,415, preserve current phase demodulation value, calculate corresponding DA value, export VCXO to and return.
After the rationalization improvement to program structure process, in above-mentioned same system environments, some indexs of this example are as follows:
1. pull-in time
From begin to capture enter tenacious tracking total time less than 5 seconds;
2. switch in the clock source
No error code is switched in the clock source;
3. the output jitter index of not having input jiffer
4.2M mouthful jitter transfer function
From These parameters as can be seen, clock output prograin and stability have reached the requirement of transmission field; The clock performance index satisfy ITU-T G.813 with the relevant index request of suggestion G.823, the index request of part index number in the suggestion wherein comprises that output jitter produces and jitter transfer function etc.
For the comparatively simple system of present embodiment, adopt two groups of self adaptation switchings of catching parameter just can reach satisfied effect.Certainly,, adopt the seizure parameter of three groups or more groups, and adopt parameter adaptive control method of the present invention, can make also that pull-in time shortens, clock switches level and smooth for some comparatively complicated systems.
Claims (5)
1. digital phase-locked loop in clock synchronizing system implementation method may further comprise the steps:
1) after the phase-locked loop program begins, at first reads the phase difference between input reference source and the output clock, make comparisons, judge whether clock locks with last phase difference;
2), then continue to follow the tracks of the input reference source if present clock locks; Execution in step 4);
3) if also not locking of present clock needs to continue to catch; In continuing capture-process, the switching of catching parameter has two kinds of situations:
If a input reference source is approaching with the frequency of output clock, is i.e. during clock approach locking, switches to the narrower seizure parameter of pullin banwidth and catch execution in step 5);
If b has worsened seriously in original in some cases clock source, clock source, front and back difference is very big, when taking place to adopt current seizure parameter to catch within a certain period of time, switch to the wideer seizure parameter of pullin banwidth and catch execution in step 5) less than the input clock source;
4) in tracing process, need judge whether because clock source deterioration etc. is former thereby cause the clock losing lock, if losing lock then needs switching clock source, and change that to catch parameter be the narrowest parameter of pullin banwidth, return step 1); If there is not losing lock, then execution in step 5);
5) calculate corresponding dac value according to the phase demodulation difference, remove to control VCXO (VCXO) after converting aanalogvoltage to, return step 1) after waiting for a period of time.
2. a kind of digital phase-locked loop in clock synchronizing system implementation method as claimed in claim 1 is characterized in that: described seizure parameter can have a lot of groups, and described parameter adopts the proportionality coefficient bigger than theoretical numerical value; The integral coefficient that employing is littler than theoretical numerical value.
3. a kind of digital phase-locked loop in clock synchronizing system implementation method as claimed in claim 2 is characterized in that: described parameter adopts two groups to catch parameter, one group of tracking parameter, and first group of pullin banwidth of catching parameter is bigger than second group of seizure parameter.
4. a kind of digital phase-locked loop in clock synchronizing system implementation method as claimed in claim 3, it is characterized in that: in described capture-process, if the frequency of output clock is near the input reference source and currently be in first group and catch parameter state, phase-locked loop is caught parameter and is then automatically switched to second group and catch parameter and catch; In described capture-process, when taking place to adopt second group of seizure parameter to catch within a certain period of time, then automatically switch to first group of seizure parameter and catch less than the input clock source; In described switching clock source step, at first adopt second group of seizure parameter to catch.
5. a kind of digital phase-locked loop in clock synchronizing system implementation method as claimed in claim 4, it is characterized in that: adopt described second group of seizure parameter to catch, surpass 30 times continuously, when still catching, automatically switch to first group of seizure parameter and catch less than the input clock source.
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| CN1333538C (en) * | 2005-03-18 | 2007-08-22 | 北京北方烽火科技有限公司 | Digital phase-lock method for clock signal in radio-frequency Layuan module |
| CN101098220B (en) * | 2006-06-29 | 2010-08-18 | 中兴通讯股份有限公司 | Digital phase-locked loop based clock synchronization method and system thereof |
| CN102271231B (en) * | 2010-06-01 | 2013-01-02 | 北京创毅视讯科技有限公司 | Clock recovering device and method |
| CN110912154B (en) * | 2019-11-20 | 2021-05-14 | 国网浙江省电力有限公司电力科学研究院 | Control method of self-adaptive phase-locked oscillator |
| CN112540665B (en) * | 2020-12-25 | 2023-05-02 | 瓴盛科技有限公司 | Memory frequency switching device and method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1196608A (en) * | 1997-04-11 | 1998-10-21 | 三星电子株式会社 | Digital processing phase lock loop for synchronous digital micro-wave apparatus |
| CN1204894A (en) * | 1997-05-21 | 1999-01-13 | 三星电子株式会社 | Digital phase locked loop circuit and method therefor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1196608A (en) * | 1997-04-11 | 1998-10-21 | 三星电子株式会社 | Digital processing phase lock loop for synchronous digital micro-wave apparatus |
| CN1204894A (en) * | 1997-05-21 | 1999-01-13 | 三星电子株式会社 | Digital phase locked loop circuit and method therefor |
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