CN104112651A - Rectifier chip making process - Google Patents

Rectifier chip making process Download PDF

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Publication number
CN104112651A
CN104112651A CN201410315792.1A CN201410315792A CN104112651A CN 104112651 A CN104112651 A CN 104112651A CN 201410315792 A CN201410315792 A CN 201410315792A CN 104112651 A CN104112651 A CN 104112651A
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Prior art keywords
boron
silicon chip
phosphorus source
diffusion furnace
phosphorus
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CN201410315792.1A
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CN104112651B (en
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王道强
魏庆山
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Yangzhou Hy Technology Development Co Ltd
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Yangzhou Hy Technology Development Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02096Cleaning only mechanical cleaning
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052Wet cleaning only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/2225Diffusion sources

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

The invention relates to a rectifier chip making process which comprises the following steps: (1) a silicon wafer is put in mixed acid and thinned; (2) cleaning, phosphorus attaching, phosphorus source pre-deposition, phosphorus slicing and sandblasting are sequentially carried out on the silicon wafer obtained from (1); (3) cleaning, boron coating, phosphorus source pushing and oxide layer removing are sequentially carried out on the sandblasted silicon wafer; (4) cleaning, boron coating, boron diffusion and boron slicing are sequentially carried out on the silicon wafer of which the oxide layer removed; and (5) a means of glass passivation is adopted, and chemical nickel plating is performed to complete chip making. A product made by the method of the invention has high stability and high reliability.

Description

A kind of rectifier chip fabrication technique
Technical field
The present invention relates to high-power semiconductor rectifying device technical field, relate in particular to a kind of rectifier chip fabrication technique.
Background technology
ESD with the plain edition bridge rectifier of current routine tests, under normal air pattern, conventionally can bear about 2KV test, can bear voltage in order to promote test, by analysis, be mainly the chip of rectifier, adopt conventional production method, its performance cannot be born higher ESD test voltage, therefore after assembling, cannot reach client's test request.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of rectifier chip fabrication technique, solves deficiency of the prior art, makes product can bear higher test voltage.
The technical scheme that the present invention solves the problems of the technologies described above is as follows:
A kind of rectifier chip fabrication technique, comprises the following steps:
(1) pack silicon chip into the gaily decorated basket, put into nitration mixture and carry out attenuate; In corrosion process, wave the gaily decorated basket, promote corrosion uniformity, guarantee the consistency of attenuate amount, etching time 10-15s, corrodes and puts into fast three grades of mobile pure water and rinse afterwards, until the residual acid on silicon chip rinses well, more than water resistance value reaches 10 Ω cm;
(2) silicon chip in (1) is cleaned successively, attached phosphorus, phosphorus source pre-deposition, phosphorus burst and sandblast;
When Wafer Cleaning, use respectively and breathe out rub liquid and hot pure water and carry out ultrasonic concussion, breathe out the liquid proportioning of rubbing for breathing out powder: the H that rubs 2o=90g:14400ml, Warm degree: 80 ± 5 DEG C, time 10-20min, then puts into silicon chip HF solution and soak 4-6min, and HF solution ratio is HF:H 2o:H 2o 2=2000:10000:200, Warm degree: 25 ± 10 DEG C, finally to wash by water, circulating water concussion, bath, dry, Wafer Cleaning is complete;
The attached phosphorus of silicon chip, chooses the paper shape phosphorus source that is not less than 70% concentration, is clipped in the middle of 2 silicon chips, comes successively on quartz boat, and entering diffusion furnace after drained carries out phosphorus source pre-deposition;
Phosphorus burst, because of the complete silicon chip of phosphorus source pre-deposition, relative between two, be difficult for separately, need put it in the HF that is not less than 15 DEG C and soak, time 16-24H, after silicon chip separates naturally, washes by water, ultrasonic concussion, bath, guarantees that silicon chip surface is without residual acid;
Sandblast, does not carry out the one side of phosphorus source pre-deposition and carries out sandblast to silicon chip, selecting model is the white fused alumina sand of W40, uses sand-blasting machine to grind silicon chip, and removal amount is at 15-25um.
(3) silicon chip after sandblast is cleaned successively, phosphorus source advances and deoxidation layer again;
Clean in same step (2) and clean, the silicon chip after cleaning, by relative between two the one side of carrying out phosphorus source pre-deposition, the neat quartz boat of putting into, carries out phosphorus source and advances;
Deoxidation layer, carries out sandblast to silicon chip another side, removes surface oxide layer, removal amount 2-5um.
(4) silicon chip after deoxidation layer is cleaned successively, is coated with boron, boron diffusion, boron burst and sandblast;
Clean in same step (2) and clean, silicon chip after cleaning, not attached phosphorus face is coated with to boron, first carry out dosing: the preparation boron oxide of boron water: EGME=100g:400ml, stir 6 ± 2h, after precipitation 6 ± 2h, by solution Filter paper filtering, be coated with the preparation boron water of boron liquid: aluminum nitrate solution: alumina powder=50ml:6ml:0.5g, more than stirring 10min
Not attached silicon chip phosphorus one is faced up to lie in and be coated with on boron sol evenning machine rotating platform, first pressing suction sheet key is adsorbed on silicon chip on rotating platform, make silicon chip start rotation by start key again, use writing brush to dip painting boron liquid (nib 4/5 need immerse and be coated with in boron liquid with upper volume) silicon chip is coated with to boron; Writing brush is from silicon chip, middle mind-set edge is coated with boron, after filling silicon chip, lift pen, machine can stop the rotation automatically, take off on the filter paper that silicon chip is placed in heating plate and dry 9 ± 1min, the sequencing when putting takes off on the filter paper that silicon chip is placed in stainless steel disc, and silicon chip is coated with to boron face and is coated with boron face relative stacking between two, and gently spread a little aluminium powder at attached phosphorus face, boron diffusion is carried out in the last neat preparation on quartz boat of putting into;
Boron burst, puts into the silicon chip after boron diffusion to be not less than the HF of 15 DEG C and to soak, and time 10-18H after silicon chip separates naturally, washes by water, ultrasonic concussion, bath, guarantees that silicon chip surface is without residual acid;
Sandblast, carries out sandblast to silicon chip two sides, and selecting model is the white fused alumina sand of W40, uses sand-blasting machine to grind silicon chip, and attached phosphorus face 1-3um is coated with boron face 5-6um.
On the basis of technique scheme, the present invention can also do following improvement:
Further, the nitration mixture in described step (1) is HF:HNO 3: C 2h 4o 2: H 2sO 4the mixed solution of=9:9:12:4;
Further, phosphorus source pre-deposition in described step (2) is that concentration is after being not less than 70% phosphorus source concentration and being attached on silicon chip, enter temperature and be in the diffusion furnace of 550 DEG C and first carry out the decomposition of phosphorus source, time 1-2h, and then to enter temperature be to carry out pre-deposition in the diffusion furnace of 1200 DEG C, time is 2-4h, and the ratio that passes into gas in described diffusion furnace is nitrogen 92.3%-83.3%, oxygen 7.7%-16.7%;
Further, it is that the diffusion furnace of 1250 DEG C spreads that the phosphorus source of described step (3) advances as silicon chip being put into temperature again, and the time is 10-15h, and the ratio that passes into gas in described diffusion furnace is nitrogen 90.9%-80%, oxygen 9.1%-20%;
Further, described boron is diffused as that to put into temperature be that the diffusion furnace of 1250 DEG C spreads by being coated with silicon chip after boron, and the time is 15-20h, and the ratio that passes into gas is nitrogen 90.9%-80%, oxygen 9.1%-20%.
This technique invention made chip out, is assembled into after bridge rectifier, and aspect ESD electrostatic test, more conventional chip can bear higher voltage, and stability is also better, also higher in client dependability.
The invention has the beneficial effects as follows:
1. by the technology mode of triple diffusion, deepen silicon chip doping content, promote its functional characteristic;
2. have the higher resistance to survey of ESD static, reliability is higher;
3. its power consumption of finished product after assembling is also low compared with conventional products.
Embodiment
Below principle of the present invention and feature are described, example, only for explaining the present invention, is not intended to limit scope of the present invention.
Embodiment 1:
A kind of rectifier chip fabrication technique, comprises the following steps:
(1) silicon chip is put into nitration mixture and carried out attenuate, etching time 10s, corrodes and puts into fast three grades of mobile pure water and rinse afterwards, until the residual acid on silicon chip rinses well, more than water resistance value reaches 10 Ω cm;
(2) silicon chip is used respectively and breathe out rub liquid and hot pure water and carry out ultrasonic concussion and clean, after cleaning, choose the paper shape phosphorus source of 70% concentration, be clipped in the middle of two silicon chips, come successively on quartz boat, after drained, enter diffusion furnace and carry out phosphorus source pre-deposition, then carry out phosphorus burst and sandblast;
(3) silicon chip is cleaned according to cleaning way in step (2), for the silicon chip after cleaning, by relative between two the one side of carrying out phosphorus source pre-deposition, the neat quartz boat of putting into, carrying out phosphorus source advances again, then silicon chip another side is carried out to sandblast, remove surface oxide layer, removal amount is 5um;
(4) first silicon chip is cleaned according to the cleaning way in step (2), configuration is coated with boron liquid, by being coated with boron sol evenning machine, silicon chip is coated with to boron, then carries out boron diffusion and boron burst;
(5) finally in conjunction with the mode of glassivation, through chemical nickel plating, chip completes.
Wherein said nitration mixture is HF:HNO 3: C 2h 4o 2: H 2sO 4the mixed solution of=9:9:12:4;
Phosphorus source pre-deposition in described step (2) is that silicon chip after attached phosphorus is put into temperature is that the diffusion furnace of 550 DEG C first carries out the decomposition of phosphorus source, time 1h, and then to enter temperature be to carry out pre-deposition in the diffusion furnace of 1200 DEG C, time is 2h, the ratio that passes into gas in described diffusion furnace is 92.3%, oxygen 7.7%;
It is that the diffusion furnace of 1250 DEG C spreads that the phosphorus source of described step (3) advances as silicon chip being put into temperature again, and the time is 15h, and the ratio that passes into gas in described diffusion furnace is nitrogen 90.9%, oxygen 9.1%;
Described boron is diffused as that to put into temperature be that the diffusion furnace of 1250 DEG C spreads by being coated with silicon chip after boron, and the time is 15h, and the ratio that passes into gas is nitrogen 90.9%, oxygen 9.1%;
This technique invention made chip out, is assembled into after bridge rectifier, and aspect ESD electrostatic test, more conventional chip can bear higher voltage, and stability is also better, also higher in client dependability.
Embodiment 2:
A kind of rectifier chip fabrication technique, comprises the following steps:
(1) silicon chip is put into nitration mixture and carried out attenuate, etching time 15s, corrodes and puts into fast three grades of mobile pure water and rinse afterwards, until the residual acid on silicon chip rinses well, more than water resistance value reaches 10 Ω cm;
(2) silicon chip is used respectively and breathe out rub liquid and hot pure water and carry out ultrasonic concussion and clean, after cleaning, choose the paper shape phosphorus source of 80% concentration, be clipped in the middle of two silicon chips, come successively on quartz boat, after drained, enter diffusion furnace and carry out phosphorus source pre-deposition, then carry out phosphorus burst and sandblast;
(3) silicon chip is cleaned according to cleaning way in step (2), for the silicon chip after cleaning, by relative between two the one side of carrying out phosphorus source pre-deposition, the neat quartz boat of putting into, carrying out phosphorus source advances again, then silicon chip another side is carried out to sandblast, remove surface oxide layer, removal amount is 5um;
(4) first silicon chip is cleaned according to the cleaning way in step (2), configuration is coated with boron liquid, by being coated with boron sol evenning machine, silicon chip is coated with to boron, then carries out boron diffusion and boron burst;
(5) finally in conjunction with the mode of glassivation, through chemical nickel plating, chip completes.
Wherein said nitration mixture is HF:HNO 3: C 2h 4o 2: H 2sO 4the mixed solution of=9:9:12:4;
Phosphorus source pre-deposition in described step (2) is that silicon chip after attached phosphorus is put into temperature is that the diffusion furnace of 550 DEG C first carries out the decomposition of phosphorus source, time 2h, and then to enter temperature be to carry out pre-deposition in the diffusion furnace of 1200 DEG C, time is 4h, the ratio that passes into gas in described diffusion furnace is nitrogen 83.3%, oxygen 16.7%;
It is that the diffusion furnace of 1250 DEG C spreads that the phosphorus source of described step (3) advances as silicon chip being put into temperature again, and the time is 15h, and the ratio that passes into gas in described diffusion furnace is nitrogen 80%, oxygen 20%;
Described boron is diffused as that to put into temperature be that the diffusion furnace of 1250 DEG C spreads by being coated with silicon chip after boron, and the time is 20h, and the ratio that passes into gas is nitrogen 80%, oxygen 20%;
This technique invention made chip out, is assembled into after bridge rectifier, and aspect ESD electrostatic test, more conventional chip can bear higher voltage, and stability is also better, also higher in client dependability.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any amendment of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims (5)

1. a rectifier chip fabrication technique, is characterized in that, comprises the following steps:
(1) silicon chip is put into nitration mixture and carried out attenuate, remove damage layer;
(2) silicon chip is cleaned successively, attached phosphorus, phosphorus source pre-deposition, phosphorus burst and sandblast;
(3) silicon chip after sandblast is cleaned, is coated with boron successively, phosphorus source advances and deoxidation layer again;
(4) silicon chip after deoxidation layer is cleaned successively, is coated with boron, boron diffusion and boron burst;
(5) finally in conjunction with the mode of glassivation, through chemical nickel plating, chip completes.
2. a kind of rectifier chip fabrication technique according to claim 1, is characterized in that, the nitration mixture in described step (1) is HF:HNO 3: C 2h 4o 2: H 2sO 4the mixed solution of=9:9:12:4.
3. a kind of rectifier chip fabrication technique according to claim 1, it is characterized in that, phosphorus source pre-deposition in described step (2) is that concentration is after being not less than 70% phosphorus source concentration and being attached on silicon chip, enter temperature and be in the diffusion furnace of 550 DEG C and first carry out the decomposition of phosphorus source, time 1-2h, and then to enter temperature be to carry out pre-deposition in the diffusion furnace of 1200 DEG C, the time is 2-4h, in described diffusion furnace, pass in proportion gas: nitrogen 92.3%-83.3%, oxygen 7.7%-16.7%.
4. a kind of rectifier chip fabrication technique according to claim 1, it is characterized in that, it is that the diffusion furnace of 1250 DEG C spreads that the phosphorus source of described step (3) advances as silicon chip being put into temperature again, time is 10-15h, in described diffusion furnace, pass in proportion gas: nitrogen 90.9%-80%, oxygen 9.1%-20%.
5. according to a kind of rectifier chip fabrication technique according to claim 1, it is characterized in that, described boron is diffused as that to put into temperature be that the diffusion furnace of 1250 DEG C spreads by being coated with silicon chip after boron, time is 15-20h, in described diffusion furnace, pass in proportion gas: nitrogen 90.9%-80%, oxygen 9.1%-20%.
CN201410315792.1A 2014-07-03 2014-07-03 A kind of rectifier chip fabrication technique Active CN104112651B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105977155A (en) * 2016-07-01 2016-09-28 扬州虹扬科技发展有限公司 Making process of fast recovery chip
CN107068561A (en) * 2017-03-27 2017-08-18 扬州虹扬科技发展有限公司 A kind of preparation method of ultralow forward voltage rectifier chip
CN109712876A (en) * 2018-12-30 2019-05-03 重庆市妙格半导体研究院有限公司 A kind of PN junction method of diffusion

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102386092A (en) * 2010-09-02 2012-03-21 南通康比电子有限公司 Manufacturing method of low-leakage diode chip
CN102496619A (en) * 2011-12-26 2012-06-13 天津环联电子科技有限公司 Protector chip of light emitting diode and production technology thereof
CN102983072A (en) * 2012-10-25 2013-03-20 南通康比电子有限公司 Diffusion method for low fragment rate diode
CN103000500A (en) * 2012-10-25 2013-03-27 南通康比电子有限公司 Deep diffusion process for manufacturing diodes
CN103606522A (en) * 2013-10-23 2014-02-26 蚌埠天宇机械工具有限公司 GPP diode chip production process

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102386092A (en) * 2010-09-02 2012-03-21 南通康比电子有限公司 Manufacturing method of low-leakage diode chip
CN102496619A (en) * 2011-12-26 2012-06-13 天津环联电子科技有限公司 Protector chip of light emitting diode and production technology thereof
CN102983072A (en) * 2012-10-25 2013-03-20 南通康比电子有限公司 Diffusion method for low fragment rate diode
CN103000500A (en) * 2012-10-25 2013-03-27 南通康比电子有限公司 Deep diffusion process for manufacturing diodes
CN103606522A (en) * 2013-10-23 2014-02-26 蚌埠天宇机械工具有限公司 GPP diode chip production process

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105977155A (en) * 2016-07-01 2016-09-28 扬州虹扬科技发展有限公司 Making process of fast recovery chip
CN105977155B (en) * 2016-07-01 2020-03-20 扬州虹扬科技发展有限公司 Manufacturing process of fast recovery chip
CN107068561A (en) * 2017-03-27 2017-08-18 扬州虹扬科技发展有限公司 A kind of preparation method of ultralow forward voltage rectifier chip
CN109712876A (en) * 2018-12-30 2019-05-03 重庆市妙格半导体研究院有限公司 A kind of PN junction method of diffusion

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