CN104104368B - Four-channel dynamic amplitude-modulated signal generator - Google Patents
Four-channel dynamic amplitude-modulated signal generator Download PDFInfo
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- CN104104368B CN104104368B CN201410368206.XA CN201410368206A CN104104368B CN 104104368 B CN104104368 B CN 104104368B CN 201410368206 A CN201410368206 A CN 201410368206A CN 104104368 B CN104104368 B CN 104104368B
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Abstract
The invention provides a four-channel dynamic amplitude-modulated signal generator, wherein the traditional 32-bit MCU is combined with an FPGA, the traditional 32-bit MCU is simulated to a dual-channel DAC, and the MCU is used as the peripheral of the FPGA instead of usual main equipment, so as to realize the four-channel dynamic amplitude-modulated signal generator. After a data interface between the FPGA and a DAC module (which actually is simulated by the MCU) is configured with a signal time sequence, the FPGA can realize the purpose only by conveying DDS data into the 'DAC' module according to time sequence requirements. The four-channel dynamic amplitude-modulated signal generator provided by the invention breaks through the top-to-bottom design method of the traditional signal generator, and originally simulates the traditional 32-bit MCU to the peripheral of the DAC; in the other hand, hardware characteristics are adequately utilized, and software intervention is furthest reduced, thus the running efficiency is great.
Description
Technical field
The present invention relates to signal exogenous estrogen field, in particular to a kind of four-way dynamic amplitude modulation signal generator.
Background technology
After electric current of intermediate frequency is modulated by low-frequency current, its amplitude and frequency are with the amplitude of low-frequency current and the change of frequency
The electric current of change is referred to as modulating frequency current.The method applying this electric current therapy disease is referred to as modulated medium frequency elec trotherapy.This treatment
Method has the features such as fast, no pain, Small side effects, curative effect are lasting of producing effects, by clinically widely used.
In medical electrotherapy equipment, most crucial part is the generation of amplitude modulation(PAM) waveform (am), by different
Modulation waveform, the change of carrier wave, after signal is amplified, and export human body.
The angle occurring from signal, in the definition of medical electric current, the frequency range of the medical electric current of intermediate frequency is 1khz
～5khz is not high.But the feature in conjunction with medical apparatus and instruments itself and the consideration of equipment cost, rarely have and can accomplish to unify
, low-cost medical signal generator of intermediate frequency, especially for some special applications, such as three-dimensional intermediate frequency interference electric therapeutic equipment, also
Need to accomplish the Phase synchronization of signal, modulation depth is adjusted etc..This complicated application, traditional using 32 even 8
Almost cannot realize in the system of singlechip chip.
Content of the invention
A first aspect of the present invention discloses a kind of four-way dynamic amplitude modulation signal generator, by 32 traditional mcu and
Fpga combines, and is modeled to dual pathways dac using 32 traditional mcu, using mcu as fpga peripheral hardware, rather than common master
Equipment, realizes four-way dynamic amplitude modulation signal generator.
In the disclosure, described four-way dynamic amplitude modulation signal generator, including a mcu, the 2nd mcu and a fpga core
Piece, be each configured between a mcu and fpga chip and between the 2nd mcu and fpga chip data/address bus, public when
Clock bus and low speed communication bus；
Configuration-direct in described fpga chip, for producing unified reference clock letter according to the outside oscillator signal providing
Number and by described common clock bus synchronous a to mcu, the 2nd mcu, and the number calculating 4 dac passages for timesharing
According to conversion, this data conversion is based on dds (direct digital synthesis technique) algorithm and produces am synthetic waveform, and the distribution in sequential
Down by described data/address bus time sharing transmissions a to mcu and the 2nd mcu；
A described mcu, the 2nd mcu are used for the peripheral hardware as described fpga chip, are used for:
A mcu, the 2nd mcu and described fpga chip is made to keep being in same ginseng by described common clock bus
Examine under clock signal；
It is connected with described fpga chip by data/address bus and receive described am synthetic waveform；And
There is provided two output amplitude-modulated signal outputs according to the am synthetic waveform of described fpga chip transmission respectively.
In further enforcement, a described mcu, the 2nd mcu are all using stm32f10x/stm32f20x/stm32f40x
One of family chip, and a mcu is identical with the 2nd mcu.
In further enforcement, a described mcu is configured to main logic control chip, passes through spi with described fpga chip
Bus communication.
In further enforcement, the reference clock signal of the fixed frequency that described fpga chip produces, when being applied to public
Clock bus；
A described mcu, the intervalometer of the 2nd mcu all work in external timing signal pattern, and a mcu, the 2nd mcu divide
Other to this signals collecting and count；
A described mcu, the 2nd mcu are for signal-count result, in timing cycles, complete according to different time slots
Become respective task；
In the process time slot of the 2nd mcu, the waveform calculating 4 dac passages respectively adopts data, and transmits to described number
According to bus；
In the process time slot of a mcu, gather the data on described data/address bus respectively and complete a dac conversion.
From the above technical solution of the present invention shows that, move the beneficial effects of the present invention is proposing a kind of four-way of simplification
State amplitude-modulated signal generator, four-way signal can synchronous, asynchronous two ways export, and can be defeated in the frequency range allowing
Go out am random waveform；On the one hand, break through the top-down method for designing of the traditional signal generator, Promethean by tradition 32
Mcu is modeled to dac peripheral hardware；On the other hand, make full use of ardware feature, reduce software intervention, operational efficiency pole to greatest extent
Good.
Brief description
Fig. 1 is the theory diagram of the four-way dynamic amplitude modulation signal generator of an embodiment of the present invention.
Specific embodiment
In order to know more about the technology contents of the present invention, especially exemplified by specific embodiment and coordinate institute's accompanying drawings to be described as follows.
As shown in figure 1, according to the preferred embodiment of the present invention, a kind of four-way dynamic amplitude modulation signal generator, by tradition
32 mcu and fpga combine, be modeled to dual pathways dac using 32 traditional mcu, using mcu as fpga peripheral hardware, and not
It is common main equipment, realize four-way dynamic amplitude modulation signal generator.
In the present embodiment, as shown in figure 1, four-way dynamic amplitude modulation signal generator, including a mcu1a, the 2nd mcu1b
And a fpga chip 2, it is each configured between a mcu and fpga chip and between the 2nd mcu and fpga chip counting
According to bus 3, common clock bus 4 and low speed communication bus 5.
Wherein, low speed communication bus 5 is that<the low speed PORT COM between ->fpga, for preparing the transmission of data for mcu.
In the present embodiment, clock signal is produced by fpga chip 2, and by common clock bus 4 be synchronized to mcu (1a and
1b), for coordinating the control sequential of mcu (1a and 1b) and fpga chip.
Aforementioned fpga chip 2, is additionally operable to the change data that timesharing calculates each dac passage, and timesharing under the distribution of sequential is sent
Toward mcu<->fpga data/address bus, thus transmit to two mcu (1a and 1b).
Configuration-direct in this fpga chip 2, for producing unified reference clock letter according to the outside oscillator signal providing
Number and by described common clock bus synchronous a to mcu, the 2nd mcu, and the number calculating 4 dac passages for timesharing
According to conversion, this data conversion is based on dds (direct digital synthesis technique) algorithm and produces am synthetic waveform, and the distribution in sequential
Down by described data/address bus time sharing transmissions a to mcu and the 2nd mcu；
A described mcu, the 2nd mcu are used for the peripheral hardware as described fpga chip, are used for:
A mcu, the 2nd mcu and described fpga chip is made to keep being in same ginseng by described common clock bus
Examine under clock signal；
It is connected with described fpga chip by data/address bus and receive described am synthetic waveform；And
There is provided two output amplitude-modulated signal outputs according to the am synthetic waveform of described fpga chip transmission respectively.
Preferably, a described mcu1a can be configured to main logic control chip, passes through with described fpga chip 2
Spi bus communication.For example in the present embodiment, a mcu adopts stm32f1031rc chip, and the 2nd mcu is also adopted by
stm32f103rc.
In the enforcement of alternative, an aforementioned mcu1a, the 2nd mcu1b are all using stm32f10x/stm32f20x/
One of stm32f40x family chip, and a mcu is identical with the 2nd mcu.
As it was previously stated, in the present embodiment, completed the synthesis of am waveform by fpga chip 2, by means of dds (Direct Digital frequency
Rate synthesizes) algorithm, extremely high frequency synthetic waveform can be produced, due to the am synthesizer realized using high speed fpga chip, can meet
The synthesis of any am waveform.
With reference to shown in Fig. 1, the reference clock signal of the fixed frequency that described fpga chip 2 produces, it is applied to common clock
Bus 4；
A described mcu1a, the intervalometer (in figure tim5ch1) of the 2nd mcu1b all work in external timing signal pattern,
First mcu, the 2nd mcu are respectively to this signals collecting and count；
A described mcu, the 2nd mcu are for signal-count result, in timing cycles, complete according to different time slots
Become respective task；
In the process time slot of the 2nd mcu, the waveform calculating 4 dac passages respectively adopts data, and transmits to described number
According to bus；
In the process time slot of a mcu, gather the data on described data/address bus respectively and complete a dac conversion.
In the present embodiment, the process logical order of a mcu is<intervalometer collection reference clock>,<time slot judgement>,<adopts
Collection data>,<dac conversion>, this process be entirely have that hardware completes it is not necessary to the intervention of any software, therefore embody
The high efficiency of whole four-way dynamic amplitude modulation signal generator and uniqueness (i.e. the specificity of mcu model).
Double mcu (1a, 1b) and fpga chip 2 (4.19430mhz) under identical clock bus, simultaneously to drive clock
Count, (4.19430mhz), to ensure dac synchronism output.
In the present embodiment, described outside oscillator signal is the active crystal oscillator of a hs-a370-67.108864mhz, is supplied to
Fpga chip 2, by its corresponding clock of distribution:
1) obtain 8.388608mhz after 8 frequency dividings and be supplied to each mcu.
2) obtain 4.194304mhz after 16 frequency dividings to export to the clock letter of the enumerator of each mcu as cpld/fpga
Number.
This signal 16 divides the dds clock obtaining 262.144khz again.This signal can also be by 1) two divided-frequency again.
3) work such as internal memory operation of cpld/fpga, works under 67.108864mhz speed completely.
Double mcu (1a, 1b) determine currently respective behavior with fpga chip 2 according to count value, as shown in the table:
With reference to shown in Fig. 1, ti1s:0, select tim5_ch1 as the input of ti1, mms [2:0], 010, select tim5 more
New events are as trigger input (trog).Ccds:1, when there is update event, sends the dma request of ccx.
In the dac of stm32 designs, dma2_ch3 and dma2_ch4 is that hardware distributes to dma " exclusive " passage, simply
Dac module opens dma function, no matter which kind of mode to trigger dac conversion with, hardware will automatically be passed for dac using dma passage
Delivery data, so when tim5 overflows, formulates him and produces a trgo signal, dma1,2 is automatically completed dma data transfer
And dac changes two work.Therefore 14,15 two behaviors in former sequential, it is convenient to omit.
Although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention.The affiliated skill of the present invention
Has usually intellectual, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations in art field.Cause
This, protection scope of the present invention ought be defined depending on those as defined in claim.
Claims (4)
1. a kind of four-way dynamic amplitude modulation signal generator is it is characterised in that include: a mcu, a 2nd mcu and fpga
Chip, is each configured with data/address bus, public between a mcu and fpga chip and between the 2nd mcu and fpga chip
Clock bus and low speed communication bus；Wherein the first mcu, the 2nd mcu are as the peripheral hardware of fpga, rather than common main equipment
To realize four-way dynamic amplitude modulation signal generator, and a mcu, the 2nd mcu are respectively provided with two dac passages；
Configuration-direct in described fpga chip, for producing unified reference clock signal simultaneously according to the outside oscillator signal providing
By described common clock bus synchronous a to mcu, the 2nd mcu, and the data calculating 4 dac passages for timesharing turns
Change, this data conversion is based on dds algorithm and produces am synthetic waveform, and by described data/address bus timesharing under the distribution of sequential
Transmit to a mcu and the 2nd mcu；
A described mcu, the 2nd mcu are used for the peripheral hardware as described fpga chip, are used for:
When making a mcu, the 2nd mcu and described fpga chip keep being in same reference by described common clock bus
Under clock signal；
It is connected with described fpga chip by data/address bus and receive described am synthetic waveform；And
There is provided two output amplitude-modulated signal outputs according to the am synthetic waveform of described fpga chip transmission respectively.
2. four-way dynamic amplitude modulation signal generator according to claim 1 it is characterised in that a described mcu, second
Mcu is all using one of stm32f10x/stm32f20x/stm32f40x family chip, and a mcu and the 2nd mcu uses
Identical chip.
3. four-way dynamic amplitude modulation signal generator according to claim 1 is it is characterised in that a described mcu configures
Based on logic control chip, communicated by low speed communication bus with described fpga chip, described low speed communication bus be spi total
Line.
4. four-way dynamic amplitude modulation signal generator according to claim 1 is it is characterised in that described fpga chip produces
Fixed frequency reference clock signal, be applied to common clock bus；
A described mcu, the intervalometer of the 2nd mcu all work in external timing signal pattern, and a mcu, the 2nd mcu are right respectively
External timing signal is acquired and counts；
A described mcu, the 2nd mcu are based on signal-count result, in timing cycles, are completed respectively according to different time slots
From task；
The waveform that described fpga chip calculates 4 dac passages in the process time slot of the 2nd mcu respectively adopts data, and transmits
To described data/address bus；
Described fpga chip gathers the data on described data/address bus respectively in time slot and completes once in processing of a mcu
Dac changes.
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| CN201410368206.XA CN104104368B (en) | 2014-07-29 | 2014-07-29 | Four-channel dynamic amplitude-modulated signal generator |
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| CN112180772A (en) * | 2019-07-01 | 2021-01-05 | 华东师范大学 | DDS and signal generator implementation system based on stm32 single chip microcomputer and broadband operational amplifier |
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| GB2118384A (en) * | 1982-03-26 | 1983-10-26 | Plessey Co Plc | Digital amplitude modulator |
| US4424812A (en) * | 1980-10-09 | 1984-01-10 | Cordis Corporation | Implantable externally programmable microprocessor-controlled tissue stimulator |
| CN85107310A (en) * | 1985-10-08 | 1986-07-23 | 中国人民解放军空军总医院 | Computer mid-frequency electrotherapy device |
| CN101339446A (en) * | 2008-07-18 | 2009-01-07 | 电子科技大学 | Double channel synchronous DDS device capable of modulating phase and amplitude |
| CN102354256A (en) * | 2011-08-01 | 2012-02-15 | 上海交通大学 | Multi-channel synchronizing signal generator based on field program gate array (FPGA) and AD9959 |
| CN102723931A (en) * | 2012-07-02 | 2012-10-10 | 优利德科技(成都)有限公司 | Wide-dynamic high-accuracy and edge time adjustable impulse wave producing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6654642B2 (en) * | 1999-09-29 | 2003-11-25 | Medtronic, Inc. | Patient interactive neurostimulation system and method |
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2014
- 2014-07-29 CN CN201410368206.XA patent/CN104104368B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4424812A (en) * | 1980-10-09 | 1984-01-10 | Cordis Corporation | Implantable externally programmable microprocessor-controlled tissue stimulator |
| GB2118384A (en) * | 1982-03-26 | 1983-10-26 | Plessey Co Plc | Digital amplitude modulator |
| CN85107310A (en) * | 1985-10-08 | 1986-07-23 | 中国人民解放军空军总医院 | Computer mid-frequency electrotherapy device |
| CN101339446A (en) * | 2008-07-18 | 2009-01-07 | 电子科技大学 | Double channel synchronous DDS device capable of modulating phase and amplitude |
| CN102354256A (en) * | 2011-08-01 | 2012-02-15 | 上海交通大学 | Multi-channel synchronizing signal generator based on field program gate array (FPGA) and AD9959 |
| CN102723931A (en) * | 2012-07-02 | 2012-10-10 | 优利德科技(成都)有限公司 | Wide-dynamic high-accuracy and edge time adjustable impulse wave producing method |
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