CN207992281U - Module occurs for multichannel reference clock - Google Patents
Module occurs for multichannel reference clock Download PDFInfo
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- CN207992281U CN207992281U CN201721889242.6U CN201721889242U CN207992281U CN 207992281 U CN207992281 U CN 207992281U CN 201721889242 U CN201721889242 U CN 201721889242U CN 207992281 U CN207992281 U CN 207992281U
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Abstract
The utility model belongs to Electronic Testing fields of measurement, is related to virtual instrument technique, is suitable for testing system to the digital/analog signal that port number, reference clock precision and stability have high requirement, such as frequency spectrograph, electromagnetic interference receiver test system.Module occurs for multichannel reference clock, includes the digital control card and clock integrated circuit boards connected by high speed connector, digital control card includes the machine frame connected by bus interface and FPGA module, and FPGA module is connect with clock integrated circuit boards；The utility model output clock lane quantity is more, can reach 5 road 100MHz and 2 road 10MHz outputs；Inner/outer input reference clock switches, and meets each equipment room synchronisation requirement of user；External reference clock signal 1MHz ~ 110MHz is continuously adjustable；Output clock stability can reach ± 50ppb in full temperature range；And individually output clock lane can turn off/open.Solve the application problems such as complexity, differentiated demand, the high stability faced in current demand signal test system.
Description
Technical field
The utility model belongs to Electronic Testing fields of measurement, is related to virtual instrument technique, when being suitable for port number, reference
There is the digital/analog signal of high requirement to test system, such as frequency spectrograph, electromagnetic interference receiver survey for clock precision and stability
Test system.
Background technology
Currently, domestic have some Clock generation module products, but there are port numbers less, external input reference clock frequency
Rate cannot be continuously adjusted, input power range is relatively narrow, export the technical problems such as reference clock stability and difference of mutually making an uproar.However, with
The rapid development of science and technology, test system integration module quantity is more and more, to the quantity demand of timing reference input and day
All to increase, complexity is more and more high, and signal speed tends to high speed, and the requirement to clock jitter and stability is also higher and higher.Cause
This, domestic existing Clock generation module cannot fully meet the market demand of test system now.
Invention content
The utility model is intended in view of the above-mentioned problems, proposing that the method for production of module occurs for a kind of multichannel reference clock.
The technical solution of the utility model is：
Module occurs for multichannel reference clock, includes the digital control card and clock board connected by high speed connector
Card, digital control card includes the machine frame connected by bus interface and FPGA module, and FPGA module is connect with clock integrated circuit boards；
Clock integrated circuit boards include two-way clock reference signal, respectively internal reference clock signal and external reference clock letter
Number；Wherein, internal reference clock signal is connected with the first power distribution module and clock modulate circuit in turn, to export
The internal reference clock of 10M；External reference clock signal be connected in turn reference clock selecting module, DDS frequency synthesis module,
Second power distribution module and clock modulate circuit；
The DDS frequency synthesis modules include sequentially connected phaselocked loop, voltage controlled crystal oscillator VCXO and the first one-to-two
Power divider, described first one-to-two power divider output end one end are connect with the second power distribution module, and the other end is logical
DDS is crossed to connect with phaselocked loop；
Second power distribution module include the second one-to-two power divider, the one one point of three power dividers with
And the 2nd 1 point of three power dividers, wherein the input terminal of the second one-to-two power divider and the first one-to-two power distribution
Device output end connects；The input terminal of two the one one point of three power dividers and the 2nd 1 point of three power dividers is separately connected
The output end of second one-to-two power divider, the one one point of three power dividers and the 2nd 1 point of three power divider it is defeated
Outlet is respectively connected with second clock modulate circuit, to 6 tunnel clock signals of output, respectively 5 road 100M clock signals and 1 tunnel
10M clock signals.
The clock modulate circuit includes sequentially connected low-noise amplifier, low-pass filter and attenuator.
It is additionally provided with frequency divider before the clock modulate circuit of the 1 road 10M clock signals of output.
The attenuator is π type attenuators, and the low-pass filter is elliptic function filter.
First power distribution module includes third one-to-two power divider and the second attenuator；The third
Output end one end of one-to-two power divider is connect with the second attenuator, and the other end is connect with reference clock selecting module.
The reference clock includes RF switch, and described RF switch one end connects external reference clock, the other end
It is connect with the output end of third one-to-two power divider；The external reference clock is also associated with limiter.
Further include clock switch circuit, the clock switch circuit includes energization input, power supply output end and company
It further includes control signal wire that the ON-OFF control circuit between energization input and power supply output end, which is connected on, including metal-oxide-semiconductor
The resistance and NPN type triode of upper concatenation, resistance is also parallel between the NPN type triode and energization input respectively
And capacitance.
The utility model has technical effect that：
The utility model be mainly characterized by output clock lane quantity it is more, 5 road 100MHz and 2 road 10MHz can be reached
Output；Inner/outer input reference clock switches, and meets each equipment room synchronisation requirement of user；External reference clock signal
1MHz ~ 110MHz is continuously adjustable；Output clock stability can reach ± 50ppb in full temperature range；And can individually to output when
Clock channel turn off/open.By the breakthrough of above-mentioned technical problem, solves the complexity faced in current demand signal test system
The application problems such as degree, differentiated demand, high stability.
Description of the drawings
Fig. 1 is the use principle schematic diagram that module occurs for the utility model multichannel reference clock.
Fig. 2 is that module principle block diagram occurs for the utility model multichannel reference clock.
The circuit design drawing of module occurs for Fig. 3 the utility model multichannel reference clocks.
Fig. 4 is the utility model DDS frequency synthesis module principle block diagrams.
Fig. 5 is the utility model clock modulate circuit functional block diagram.
Fig. 6 is the utility model clock switch circuit functional block diagram.
Reference numeral：1- third one-to-two power dividers, 2- the first one-to-two power dividers, 3- the second one-to-two work(
Rate distributor, the one one point of three power dividers of 4-, the 2nd 1 point of three power dividers of 5-, 6- frequency dividers, 7- low noise amplifications
Device, 8- low-pass filters, 9- attenuators, 10- limiters, the second attenuators of 11-.
Specific implementation mode
Module occurs for multichannel reference clock, includes the digital control card and clock board connected by high speed connector
Card, digital control card includes the machine frame connected by bus interface and FPGA module, and FPGA module is connect with clock integrated circuit boards；
Clock integrated circuit boards include two-way clock reference signal, respectively internal reference clock signal and external reference clock letter
Number；Wherein, internal reference clock signal is connected with the first power distribution module and clock modulate circuit in turn, to export
The internal reference clock of 10M；External reference clock signal be connected in turn reference clock selecting module, DDS frequency synthesis module,
Second power distribution module and clock modulate circuit；
The DDS frequency synthesis modules include sequentially connected phaselocked loop, voltage controlled crystal oscillator VCXO and the first one-to-two
Power divider 2, described first one-to-two power divider, 2 output end one end are connect with the second power distribution module, the other end
It is connect with phaselocked loop by DDS；Phaselocked loop can improve the limitation of the DDS output clock frequency upper limits, when completing to reference input
The locking of clock.And due to this characteristic, it can support the external reference input clock range of 1MHz ~ 110MHz.
Second power distribution module includes 3, the 1st points of three power dividers 4 of the second one-to-two power divider
And the 2nd 1 point of three power divider 5, wherein the input terminal of the second one-to-two power divider 3 and the first one-to-two power
2 output end of distributor connects；The input terminal of two the one one point three power dividers 4 and the 2nd 1 point of three power divider 5
It is separately connected the output end of the second one-to-two power divider 3, the one one point of three power divider 4 and the 2nd 1 point of three power
The output end of distributor 5 is respectively connected with second clock modulate circuit, to 6 tunnel clock signals of output, respectively 5 road 100M clocks
Signal and 1 road 10M clock signals.
The clock modulate circuit includes sequentially connected low-noise amplifier 7, low-pass filter 8 and attenuator 9.
It is additionally provided with frequency divider 6 before the clock modulate circuit of the 1 road 10M clock signals of output.
The attenuator 9 is π types attenuator 9, and the low-pass filter 8 is elliptic function filter.Power adjustment
By low-noise amplifier 7 and π types attenuator 9 so that output power reaches requirement.Spurious reduction part passes through discrete parameter
Elliptic function filter completes the inhibition to harmonic wave.
First power distribution module includes third one-to-two power divider 1 and the second attenuator 11；It is described
Output end one end of third one-to-two power divider 1 is connect with the second attenuator 11, the other end and reference clock selecting module
Connection.
The reference clock includes RF switch, and described RF switch one end connects external reference clock, the other end
It is connect with the output end of third one-to-two power divider 1；The external reference clock is also associated with limiter 10.
Further include clock switch circuit, the clock switch circuit includes energization input, power supply output end and company
It further includes control signal wire that the ON-OFF control circuit between energization input and power supply output end, which is connected on, including metal-oxide-semiconductor
The resistance and NPN type triode of upper concatenation, resistance is also parallel between the NPN type triode and energization input respectively
And capacitance.Clock switch circuit is used to complete the customization on-off function to extra clock lane.No using all defeated
Go out in the case of reference source, extra clock output can be turned off, reduce the power consumption of system as possible.
Fig. 1 is the use principle schematic diagram that module occurs for the utility model multichannel reference clock.Multichannel reference clock
Module occurs as significant components in test system, other modules by RF cable to same machine frame provide high-precision and height
Stability reference clock.
Fig. 4 is the utility model DDS frequency synthesis module principle block diagrams.Since DDS exports clock by reference clock frequency
The limitation of the upper limit, therefore DDS coordinates the mode of analog phase-locked look to reach required output frequency requirement.In the design, it presses
The 100MHz clocks of control crystal oscillator VCXO output other than being supplied to rear class output clock modulate circuit to input, also provide all the way to
DDS kernels make reference clock, export the phase demodulation input clock of rear class Analogous phase-locking loop module.The frequency of this clock is joined in inside
It is that fixed 10MHz determines the output frequency of DDS kernels according to the input of user if it is external reference when examining.The output
Frequency undergo reconstruction filter complete harmonic wave inhibition, be then passed to the analog phase-locked look of rear class, it is complete with the reference frequency of input
At phase demodulation, the 100MHz VCXO lockings of rear class are controlled.The structure take full advantage of DDS high-precision and phaselocked loop can frequency multiplication spy
Point has taken into account required precision and frequency range requirement.
Fig. 5 is that the utility model exports clock modulate circuit functional block diagram.Conditioning part is main to realize output reference clock
Filtering and power adjustment.The clock signal locked from DDS frequency synthesis modules, cannot due to the limitation of chip fan-out capability
Reach the level of requirement, so needing to carry out low noise amplification to clock signal in rear class, and coordinates π types attenuator 9 to power
Accurately adjusted.Furthermore since DDS output signals pass through multiple harmonic, thus need to increase rear class filtering device to harmonic wave and
It is spuious to be inhibited, ensure that output clock signal is in and preferably mutually makes an uproar and spuious level.The filter is realized there are many mode,
Consider cost of implementation and filter effect, the preferential filtering for selecting 7 rank elliptic filters to carry out output clock signal.
Fig. 6 is that the utility model exports clock switch circuit functional block diagram.The design share 5 road 100MHz output clock and
2 road 100MHz export clock.Cause power consumption bigger than normal simultaneously providing powerful fan-out capability.Building integrated test system
When, often need not so multichannel output clock, and when system is stringenter to power consumption requirements problem just than more prominent.
In this case, the utility model by control low-noise amplifier 7 power supply come to single channel export clock into
Row is opened or shutdown, can further decrease the overall power of system, and reduce interfering with each other for channel to the greatest extent.FPGA module
Receive the shutdown that issues of user or open instructions, control triode ON or cut-off, further come control metal-oxide-semiconductor conducting or
Person ends, and can thus control the power supply of low-noise amplifier 7, to reach the work(that control output channel is opened or turned off
Energy.
The utility model operates multichannel reference clock by Zero greeve controller and module realization signal test system occurs
Build, can to high integration, port number is more, signal of the higher system of clock request carries out high-precision measurement.
Claims (7)
1. module occurs for multichannel reference clock, it is characterised in that：Include the digital control card that is connected by high speed connector with
And clock integrated circuit boards, digital control card includes the machine frame connected by bus interface and FPGA module, FPGA module and clock board
Card connection；
Clock integrated circuit boards include two-way clock reference signal, respectively internal reference clock signal and external reference clock signal；
Wherein, internal reference clock signal is connected with the first power distribution module and clock modulate circuit in turn, to export 10M's
Internal reference clock；External reference clock signal is connected with reference clock selecting module, DDS frequency synthesis module, second in turn
Power distribution module and clock modulate circuit；
The DDS frequency synthesis modules include sequentially connected phaselocked loop, voltage controlled crystal oscillator VCXO and the first one-to-two power
Distributor（2）, the first one-to-two power divider（2）Output end one end is connect with the second power distribution module, the other end
It is connect with phaselocked loop by DDS；
Second power distribution module includes the second one-to-two power divider（3）, the one one point of three power divider（4）
And the 2nd 1 point of three power dividers（5）, wherein the second one-to-two power divider（3）Input terminal and the first one-to-two
Power divider（2）Output end connects；Two the one one point of three power dividers（4）And the 2nd 1 point of three power dividers
（5）Input terminal be separately connected the second one-to-two power divider（3）Output end, the one one point of three power dividers（4）With
And the 2nd 1 point of three power dividers（5）Output end be respectively connected with second clock modulate circuit, to 6 road clocks letter of output
Number, respectively 5 road 100M clock signals and 1 road 10M clock signals.
2. module occurs for multichannel reference clock according to claim 1, it is characterised in that：The clock modulate circuit
Including sequentially connected low-noise amplifier（7）, low-pass filter（8）And attenuator（9）.
3. module occurs for multichannel reference clock according to claim 2, it is characterised in that：When the described 1 road 10M of output
It is additionally provided with frequency divider before the clock modulate circuit of clock signal（6）.
4. module occurs for multichannel reference clock according to claim 3, it is characterised in that：The attenuator（9）For π
Type attenuator（9）, the low-pass filter（8）For elliptic function filter.
5. module occurs for multichannel reference clock according to claim 4, it is characterised in that：First power distribution
Module includes third one-to-two power divider（1）And second attenuator（11）；The third one-to-two power divider（1）
Output end one end and the second attenuator（11）Connection, the other end are connect with reference clock selecting module.
6. module occurs for multichannel reference clock according to claim 5, it is characterised in that：The reference clock includes
RF switch, described RF switch one end connect external reference clock, the other end and third one-to-two power divider（1）'s
Output end connects；The external reference clock is also associated with limiter（10）.
7. module occurs for multichannel reference clock according to claim 6, it is characterised in that：It further include clock switch electricity
Road, the clock switch circuit includes energization input, powering output end and is connected to energization input and power supply is defeated
ON-OFF control circuit between outlet further includes the resistance concatenated on control signal wire and NPN type three including metal-oxide-semiconductor
Pole pipe is also parallel with resistance and capacitance respectively between the NPN type triode and energization input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721889242.6U CN207992281U (en) | 2017-12-29 | 2017-12-29 | Module occurs for multichannel reference clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721889242.6U CN207992281U (en) | 2017-12-29 | 2017-12-29 | Module occurs for multichannel reference clock |
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| Publication Number | Publication Date |
|---|---|
| CN207992281U true CN207992281U (en) | 2018-10-19 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201721889242.6U Active CN207992281U (en) | 2017-12-29 | 2017-12-29 | Module occurs for multichannel reference clock |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112383300A (en) * | 2020-10-26 | 2021-02-19 | 深圳市儒科电子有限公司 | High-precision frequency phase micro-jump meter |
| US20220103165A1 (en) * | 2018-12-27 | 2022-03-31 | Ams International Ag | Filters for removing disturbances from signals |
-
2017
- 2017-12-29 CN CN201721889242.6U patent/CN207992281U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20220103165A1 (en) * | 2018-12-27 | 2022-03-31 | Ams International Ag | Filters for removing disturbances from signals |
| CN112383300A (en) * | 2020-10-26 | 2021-02-19 | 深圳市儒科电子有限公司 | High-precision frequency phase micro-jump meter |
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