CN101854171A - Multi-frequency point simulating phase-locked loop circuit - Google Patents
Multi-frequency point simulating phase-locked loop circuit Download PDFInfo
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- CN101854171A CN101854171A CN201010187254A CN201010187254A CN101854171A CN 101854171 A CN101854171 A CN 101854171A CN 201010187254 A CN201010187254 A CN 201010187254A CN 201010187254 A CN201010187254 A CN 201010187254A CN 101854171 A CN101854171 A CN 101854171A
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Abstract
The invention provides a multi-frequency point simulating phase-locked loop circuit which comprises a voltage-controlled oscillator module with a plurality of frequencies, a first frequency divider, a second frequency divider, a phase discriminator, a lowpass filter and a controller. The first frequency divider inputs a source reference clock signal and outputs a first frequency signal obtained after the frequency division is carried out on the source reference clock signal; the second frequency divider inputs a feedback clock signal output by the voltage-controlled oscillator module and outputs a second frequency signal obtained after the frequency division is carried out on the feedback clock signal; the phase discriminator inputs the first frequency signal and the second frequency signal and outputs a phase difference signal of the first frequency signal the second frequency signal; the lowpass filter inputs the phase difference signal and outputs an electrical signal obtained after the phase difference signal is filtered; and the controller is used for selecting the first frequency from the frequencies, controlling the voltage-controlled oscillator module to work at the first frequency and outputting the feedback clock signal with the first frequency under the control of the electrical signal. The invention can flexibly set various frequencies on line and improves the generality of hardware.
Description
Technical field
The present invention relates to a kind of phase-locked loop circuit designing technique, be meant a kind of multi-frequency point simulating phase-locked loop circuit especially.
Background technology
In the optical transmission field, the quality requirement that signal is sent reference clock is very high, and the analog phase-locked look technology is first-selected at present clock circuit implementation method.But, along with the fast development of optical communication, and the formulation of new standard, it is more and more to be linked into the type of service of transmitting in the optical-fiber network, the Equipment Market demand of supporting multi-service to insert is also increasing, and how to realize the clock circuit of multiple frequency, then is very crucial.
As shown in Figure 1, be traditional analog phase-locked look circuit, source reference clock f
RefThrough the M frequency divider fixedly behind the frequency division with feedback clock f
BackFixedly behind the frequency division, enter phase discriminator (PFD) through the Fractional-N frequency device, the UP/DOWN signal of PFD output through low pass filter (LPF) filtering after, insert the voltage-controlled end of voltage controlled oscillator (VCO), the output frequency f of adjustment VCO
TxThereby, form a phase-locked loop circuit.Device in this circuit is generally discrete device, and the adjustment of the frequency parameter of each parts can only pass through to change device, as, needs are adjusted the frequency of VCO, can only change the VCO of a required frequency; So in case hardware device comes into operation, frequency is exactly what fix, can't realize the switching of multiple frequency.
For realizing the access of multiple business, different hardware devices must be provided, obviously, the phase-locked loop of this single-frequency point lacks flexibility, and cost is higher.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of multi-frequency point simulating phase-locked loop circuit, and flexible setting that can the multiple frequency of canbe used on line has improved generality of hardware.
For solving the problems of the technologies described above, embodiments of the invention provide a kind of multi-frequency point simulating phase-locked loop circuit, comprising:
Voltage-control oscillator module with a plurality of frequencies;
First frequency divider is input as the source reference clock signal, is output as the first frequency signal that obtains behind the described source reference clock signal frequency division;
Second frequency divider is input as feedback clock signal, is output as the second frequency signal that obtains behind the described feedback clock signal frequency division;
Phase discriminator is connected with described second frequency divider with described first frequency divider respectively, is input as described first frequency signal and described second frequency signal, is output as the phase signal of described first frequency signal and described second frequency signal;
Low pass filter is connected with described phase discriminator, and is connected with described voltage-control oscillator module, is input as described phase signal, is output as the signal of telecommunication that obtains after the described phase signal filtering;
Controller, be connected with described voltage-control oscillator module, be used for selecting first frequency, and control described voltage-control oscillator module and work in described first frequency from described a plurality of frequencies, and under the control of the described signal of telecommunication, output device has the feedback clock signal of described first frequency.
Wherein, described voltage-control oscillator module comprises:
At least two voltage controlled oscillators, the frequency of each voltage controlled oscillator in described at least two voltage controlled oscillators is different;
Multiselect one chip for driving, be connected with described at least two voltage controlled oscillators, and be connected with described controller, be used under the control of described controller, from described at least two voltage controlled oscillators, select to have the voltage controlled oscillator of described first frequency, under the control of the filtered signal of telecommunication of described low pass filter, output device has the feedback clock signal of described first frequency.
Wherein, described voltage-control oscillator module also comprises:
1 drives the multicore sheet, is connected with described low pass filter, and is connected with each voltage controlled oscillator in described at least two voltage controlled oscillators, is used for the described signal of telecommunication is input to each voltage controlled oscillator respectively.
Wherein, described voltage-control oscillator module is specially: many speed voltage controlled oscillator able to programme; Described controller is controlled described many speed voltage controlled oscillator able to programme is realized described first frequency by programming setting.
Wherein, described many speed voltage controlled oscillator able to programme selects port to be connected with described controller with the I2C interface by its frequency, wherein, described frequency selects port to be used for selecting and described first frequency being set, and described I2C interface is used for regulating according to described first frequency the frequency of described many speed voltage controlled oscillator able to programme.
Wherein, described first frequency divider and described second frequency divider are the frequency divider of adjustable frequency coefficient, and all be connected with described controller, described controller also is used to regulate the coefficient of frequency of described first frequency divider and described second frequency divider, and described source reference clock signal is equated through the frequency behind described second frequency divider through described first frequency divider and described feedback clock signal with first frequency.
Wherein, described first frequency divider and described second frequency divider all adopt programmable logic controller (PLC) spare FPGA to realize that described controller is regulated the coefficient of frequency of described first frequency divider and described second frequency divider by described FPGA.
Wherein, described first frequency divider and described second frequency divider are the register that adopts described FPGA to be designed to.
Wherein, described phase discriminator adopts programmable logic controller (PLC) spare FPGA to realize.
Wherein, described controller is a central processor CPU.
The beneficial effect of technique scheme of the present invention is as follows:
In the such scheme, the voltage-control oscillator module that has a plurality of frequencies by setting, select required first frequency by controller, and the control voltage controlled oscillator works in this first frequency, this voltage controlled oscillator that works in first frequency is under the control of the signal of telecommunication of described low pass filter output, and output device has the feedback clock signal of described first frequency; In prior art, if will be set to required first frequency, must change the method for voltage controlled oscillator, the solution of the present invention need not to change voltage controlled oscillator, just can from a plurality of frequencies, select required first frequency by above-mentioned controller, realize the flexible setting and the switching of online multiple frequency, improved generality of hardware.
Description of drawings
Fig. 1 is existing analog phase-locked look circuit block diagram;
Fig. 2 is a multi-frequency point simulating phase-locked loop circuit block diagram of the present invention;
Fig. 3 is the first embodiment block diagram of circuit shown in Figure 2;
Fig. 4 is the second embodiment block diagram of circuit shown in Figure 2.
Embodiment
For making the technical problem to be solved in the present invention, technical scheme and advantage clearer, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
The phase-locked loop frequency that the present invention is directed to existing single-frequency point is fixed, and can't realize the problem of the setting of multiple frequency, provides a kind of flexible setting that can the multiple frequency of canbe used on line, the multi-frequency point simulating phase-locked loop circuit of raising generality of hardware.
As shown in Figure 2, the embodiments of the invention multi-frequency point simulating phase-locked loop circuit comprises:
Voltage-control oscillator module with a plurality of frequencies;
First frequency divider is input as the source reference clock signal, is output as the first frequency signal that obtains behind the described source reference clock signal frequency division;
Second frequency divider is input as the feedback clock signal that described voltage-control oscillator module is exported, and is output as the second frequency signal that obtains behind the described feedback clock signal frequency division;
Phase discriminator (PFD) is connected with described second frequency divider with described first frequency divider respectively, is input as described first frequency signal and described second frequency signal, is output as the phase signal of described first frequency signal and described second frequency signal;
Low pass filter (LPF) is connected with described phase discriminator, and with described voltage-control oscillator module, be input as described phase signal, be output as the signal of telecommunication that obtains after the described phase signal filtering;
Controller, be connected with described voltage-control oscillator module, be used for selecting first frequency from described a plurality of frequencies, and control described voltage-control oscillator module and work in described first frequency, this voltage controlled oscillator that works in first frequency is under the control of the described signal of telecommunication, and output device has the feedback clock signal of described first frequency.
This embodiment has the voltage-control oscillator module of a plurality of frequencies by setting, select required first frequency by controller, and the control voltage controlled oscillator works in this first frequency, this voltage controlled oscillator that works in this first frequency is under the control of the signal of telecommunication of described low pass filter output, and output has the feedback clock signal of first frequency; After clock was stable, the feedback clock signal that obtains after this adjusting can be used as the transmission reference clock of optical transmission high speed signal; In prior art, if will be set to required first frequency, must change the method for voltage controlled oscillator, embodiments of the invention need not to change voltage controlled oscillator, just can from a plurality of frequencies, select required first frequency by above-mentioned controller, realize the flexible setting of online multiple frequency, improved generality of hardware.
Above-mentioned controller can be handled and the intelligent object of control ability for central processor CPU etc. has.
As shown in Figure 3, be first embodiment of circuit shown in Figure 2, wherein, above-mentioned voltage-control oscillator module comprises:
At least two voltage controlled oscillators (VCO), the frequency of each voltage controlled oscillator in described at least two voltage controlled oscillators is different, as the VCO1 among the figure, VCO2 ..., VCOn, the frequency of this n VCO has nothing in common with each other;
Multiselect one chip for driving (selecting 1 chip for driving) as the n among the figure, be connected with each voltage controlled oscillator in described at least two voltage controlled oscillators respectively, and be connected with described controller (as the I/O of above-mentioned CPU control pin), be used under the control of described controller, from described at least two voltage controlled oscillators, select to have the voltage controlled oscillator of described first frequency, this voltage controlled oscillator with first frequency is under the control of the filtered signal of telecommunication of described low pass filter, and output device has the feedback clock signal of described first frequency; That is to say that this n selects 1 chip for driving from VCO1, VCO2 ..., select VCO to be connected among the VCOn, and under the filtered signal of telecommunication control of low pass filter, output have the feedback clock signal of first frequency with low pass filter with required first frequency.
Further, this voltage-control oscillator module also can comprise:
1 drives the multicore sheet, is connected with described low pass filter, and is connected with each voltage controlled oscillator in described at least two voltage controlled oscillators respectively, is used for the described signal of telecommunication is input to each voltage controlled oscillator respectively; Can guarantee like this from being transferred to each voltage controlled oscillator that the signal of telecommunication that low pass filter LPF comes out can't harm.
As shown in Figure 4, be second embodiment of circuit shown in Figure 2, wherein, above-mentioned voltage-control oscillator module is specially: many speed voltage controlled oscillator PVCXO able to programme; Described controller is controlled described many speed voltage controlled oscillator able to programme is realized described first frequency by programming setting;
Wherein, described many speed voltage controlled oscillator able to programme selects port to connect with described controller (as being connected with CPU) with the I2C interface by its frequency, wherein, described frequency selects port to be used for selecting and described first frequency being set, and described I2C interface is used for regulating according to described first frequency the frequency of described many speed voltage controlled oscillator able to programme.The characteristics of this PVCXO maximum can be provided with a plurality of frequencies by programming exactly, and therefore, CPU can realize the setting of required frequency or the switching between the different frequency by PVCXO; Can be implemented in the flexible setting and the switching of the multiple frequency of line too, improved generality of hardware.
In addition, above-mentioned Fig. 2, Fig. 3 and embodiment illustrated in fig. 4 in, described first frequency divider and described second frequency divider are the frequency divider of adjustable frequency coefficient, and all be connected with described controller, described controller also is used to regulate the coefficient of frequency of described first frequency divider and described second frequency divider, and described source reference clock signal is equated through the frequency behind described second frequency divider through described first frequency divider and described feedback clock signal with first frequency; That is to say, as shown in the figure, f
RefThe coefficient of frequency=f of frequency/first frequency divider
BackThe coefficient of frequency of frequency/second frequency divider; Wherein, f
RefBe source reference clock, f
BackFor having the feedback clock signal of described first frequency, described first frequency is the output frequency by the VCO of the work at present of CPU setting; As f
RefBe 150MHz, the coefficient of frequency of first frequency divider is 15, and the unit of the signal behind the frequency division is Hz, f
BackFrequency (being first frequency) be 600MHz, the coefficient of frequency of second frequency divider is 60, then 150MHz/15=600MHz/60=10MHz.
Specifically, described first frequency divider and described second frequency divider all adopt programmable logic controller (PLC) spare FPGA to realize that described controller is regulated the coefficient of frequency of described first frequency divider and described second frequency divider by described FPGA.
Further, described first frequency divider and described second frequency divider are the register that adopts described FPGA to be designed to, can read and write in real time for controller CPU, and the coefficient of frequency of real-time regulated first frequency divider second frequency divider.
That is to say, can be for as Fig. 3 and the described M frequency divider of Fig. 4 as above-mentioned first frequency divider, second frequency divider can be for as Fig. 3 and the described Fractional-N frequency device of Fig. 4, M wherein, N can become adjustable by Programming Design, but and Configuration Online;
In addition, in above-mentioned Fig. 2, Fig. 3 and the described embodiment of Fig. 4, described phase discriminator also can adopt programmable logic controller (PLC) spare FPGA to realize, with the variation of the coefficient of frequency that adapts to two frequency dividers.
The specific implementation of multi-frequency point simulating phase-locked loop circuit of the present invention is described in conjunction with Fig. 2, Fig. 3 and Fig. 4 below again:
At first explanation is: above-mentioned M frequency divider, Fractional-N frequency device and PFD are when being realized by Programmable Logic Controller, also include the accessory circuit of this Programmable Logic Controller and run on logical file on this Programmable Logic Controller, cpu controller also comprises the program file on its accessory circuit and the operation cpu system etc.;
Source reference clock signal f
RefEnter PFD, feedback clock signal f through the M frequency divider
BackEnter PFD through the Fractional-N frequency device, the clock signal of PFD after to two frequency divisions carried out phase demodulation, and exports corresponding UP/DOWN signal; Wherein, M frequency divider, Fractional-N frequency device and PFD all have programmable logic controller (PLC) to realize, wherein, can M and N be designed to adjustablely by programming, reserve cpu i/f, can realize online setting for program, to adapt to different frequency reference clock and feedback clock;
The UP/DOWN signal of PFD output through the simulation low-pass filter circuit, is converted into the voltage signal of low frequency, enters multifrequency point VCO module, and the voltage-controlled end of VCO is regulated;
The VCO module can provide necessary a plurality of frequencies, and the switching between different frequency can be implemented in line traffic control by the particular CPU interface;
VCO feeds back to PFD through the adjusted clock of voltage-controlled end, thereby forms complete phase-locked loop; After clock is stable, the output clock f of VCO module
TxPromptly can be used as optical transmission high speed signal ground and send reference clock.
In sum, above-mentioned multi-frequency point simulating phase-locked loop circuit of the present invention is by CPU and have the VCO of a plurality of frequencies and the frequency divider of the adjustable frequency coefficient that adapts with the frequency of VCO, flexible setting and switching that can the multiple frequency of canbe used on line, improve generality of hardware, can significantly reduce the overall system cost.
The above is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. a multi-frequency point simulating phase-locked loop circuit is characterized in that, comprising:
Voltage-control oscillator module with a plurality of frequencies;
First frequency divider is input as the source reference clock signal, is output as the first frequency signal that obtains behind the described source reference clock signal frequency division;
Second frequency divider is input as the feedback clock signal that described voltage-control oscillator module is exported, and is output as the second frequency signal that obtains behind the described feedback clock signal frequency division;
Phase discriminator is connected with described second frequency divider with described first frequency divider respectively, is input as described first frequency signal and described second frequency signal, is output as the phase signal of described first frequency signal and described second frequency signal;
Low pass filter is connected with described phase discriminator, and is connected with described voltage-control oscillator module, is input as described phase signal, is output as the signal of telecommunication that obtains after the described phase signal filtering;
Controller, be connected with described voltage-control oscillator module, be used for selecting first frequency, and control described voltage-control oscillator module and work in described first frequency from described a plurality of frequencies, and under the control of the described signal of telecommunication, output device has the feedback clock signal of described first frequency.
2. multi-frequency point simulating phase-locked loop circuit according to claim 1 is characterized in that, described voltage-control oscillator module comprises:
At least two voltage controlled oscillators, the frequency of each voltage controlled oscillator in described at least two voltage controlled oscillators is different;
Multiselect one chip for driving, be connected with described at least two voltage controlled oscillators, and be connected with described controller, be used under the control of described controller, from described at least two voltage controlled oscillators, select to have the voltage controlled oscillator of described first frequency, under the control of the filtered signal of telecommunication of described low pass filter, output device has the feedback clock signal of described first frequency.
3. multi-frequency point simulating phase-locked loop circuit according to claim 2 is characterized in that, described voltage-control oscillator module also comprises:
1 drives the multicore sheet, is connected with described low pass filter, and is connected with each voltage controlled oscillator in described at least two voltage controlled oscillators, is used for the described signal of telecommunication is input to each voltage controlled oscillator respectively.
4. multi-frequency point simulating phase-locked loop circuit according to claim 1 is characterized in that, described voltage-control oscillator module is specially: many speed voltage controlled oscillator able to programme; Described controller is controlled described many speed voltage controlled oscillator able to programme is realized described first frequency by programming setting.
5. multi-frequency point simulating phase-locked loop circuit according to claim 4, it is characterized in that, described many speed voltage controlled oscillator able to programme selects port to be connected with described controller with the I2C interface by its frequency, wherein, described frequency selects port to be used for selecting and described first frequency being set, and described I2C interface is used for regulating according to described first frequency the frequency of described many speed voltage controlled oscillator able to programme.
6. multi-frequency point simulating phase-locked loop circuit according to claim 1, it is characterized in that, described first frequency divider and described second frequency divider are the frequency divider of adjustable frequency coefficient, and all be connected with described controller, described controller also is used to regulate the coefficient of frequency of described first frequency divider and described second frequency divider, and described source reference clock signal is equated through the frequency behind described second frequency divider through described first frequency divider and described feedback clock signal with first frequency.
7. multi-frequency point simulating phase-locked loop circuit according to claim 6, it is characterized in that, described first frequency divider and described second frequency divider all adopt programmable logic controller (PLC) spare FPGA to realize that described controller is regulated the coefficient of frequency of described first frequency divider and described second frequency divider by described FPGA.
8. multi-frequency point simulating phase-locked loop circuit according to claim 7 is characterized in that, described first frequency divider and described second frequency divider are the register that adopts described FPGA to be designed to.
9. multi-frequency point simulating phase-locked loop circuit according to claim 1 is characterized in that, described phase discriminator adopts programmable logic controller (PLC) spare FPGA to realize.
10. according to each described multi-frequency point simulating phase-locked loop circuit of claim 1-9, it is characterized in that described controller is CPU.
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| CN102347750A (en) * | 2011-09-06 | 2012-02-08 | 迈普通信技术股份有限公司 | Clock following circuit and following method of clock circuit |
| CN103427836A (en) * | 2013-07-25 | 2013-12-04 | 京东方科技集团股份有限公司 | Frequency signal generation system and display device |
| CN104539285A (en) * | 2013-12-19 | 2015-04-22 | 复旦大学 | Data clock recovery circuit |
| CN104702279A (en) * | 2015-03-17 | 2015-06-10 | 东南大学 | Frequency synthesizer of phase-locked loop |
| CN105259535A (en) * | 2015-09-29 | 2016-01-20 | 西安知几天线技术有限公司 | Method for generating frequency source of vehicle radar radio frequency front end |
| CN106059572A (en) * | 2016-05-23 | 2016-10-26 | 北京航空航天大学 | Frequency source module of adjusting frequency output based on programmable control circuit |
| CN106656168A (en) * | 2016-12-30 | 2017-05-10 | 北京集创北方科技股份有限公司 | Clock data restoration device and method |
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| CN111541451A (en) * | 2020-06-23 | 2020-08-14 | 深圳比特微电子科技有限公司 | Method and clock circuit for up-converting a clock signal |
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| CN102347750A (en) * | 2011-09-06 | 2012-02-08 | 迈普通信技术股份有限公司 | Clock following circuit and following method of clock circuit |
| CN103427836A (en) * | 2013-07-25 | 2013-12-04 | 京东方科技集团股份有限公司 | Frequency signal generation system and display device |
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| CN104539285A (en) * | 2013-12-19 | 2015-04-22 | 复旦大学 | Data clock recovery circuit |
| CN104702279A (en) * | 2015-03-17 | 2015-06-10 | 东南大学 | Frequency synthesizer of phase-locked loop |
| CN105259535A (en) * | 2015-09-29 | 2016-01-20 | 西安知几天线技术有限公司 | Method for generating frequency source of vehicle radar radio frequency front end |
| CN106059572A (en) * | 2016-05-23 | 2016-10-26 | 北京航空航天大学 | Frequency source module of adjusting frequency output based on programmable control circuit |
| CN106656168A (en) * | 2016-12-30 | 2017-05-10 | 北京集创北方科技股份有限公司 | Clock data restoration device and method |
| CN107483048A (en) * | 2017-10-10 | 2017-12-15 | 南京冉思电子科技有限公司 | A kind of generation device of multiband local oscillation signal |
| CN109698697A (en) * | 2018-12-29 | 2019-04-30 | 西安智多晶微电子有限公司 | A kind of phase-locked loop apparatus and fpga chip applied to fpga chip |
| CN109698697B (en) * | 2018-12-29 | 2023-11-14 | 西安智多晶微电子有限公司 | Phase-locked loop device applied to FPGA chip and FPGA chip |
| CN111541451A (en) * | 2020-06-23 | 2020-08-14 | 深圳比特微电子科技有限公司 | Method and clock circuit for up-converting a clock signal |
| US11742866B2 (en) | 2020-06-23 | 2023-08-29 | Shenzhen Microbt Electronics Technology Co., Ltd. | Method for up-converting clock signal, clock circuit and digital processing device |
| CN114637370A (en) * | 2022-03-25 | 2022-06-17 | 北京中科飞鸿科技股份有限公司 | Circuit, device and method for switching internal and external different frequency reference clock signals |
| CN114637370B (en) * | 2022-03-25 | 2024-02-20 | 北京中科飞鸿科技股份有限公司 | Internal and external different frequency reference clock signal switching circuit, device and method |
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Application publication date: 20101006 |