CN104078336B - 无衬底结构的功率器件制造工艺 - Google Patents

无衬底结构的功率器件制造工艺 Download PDF

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CN104078336B
CN104078336B CN201410312421.8A CN201410312421A CN104078336B CN 104078336 B CN104078336 B CN 104078336B CN 201410312421 A CN201410312421 A CN 201410312421A CN 104078336 B CN104078336 B CN 104078336B
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hydrogen ion
layer
wafer
ion implantation
power device
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CN104078336A (zh
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杨凡力
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Shanghai Zhen Xin Microelectronics Science And Technology Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling

Abstract

本发明公开的一种无衬底结构的功率器件制造工艺，由以下步骤组成：(1)制备产品晶圆和衬底晶圆；(2)在产品晶圆上形成一氢离子注入层；(3)在衬底晶圆上形成一层多孔硅氧化层；(4)将氢离子注入层表面贴在多孔硅氧化层表面上；(5)将产品晶圆的氢离子注入层以外的部分从氢离子注入层的层底处剥离掉,然后对剥离面进行抛光处理；(6)在氢离子注入层上加工出功率器件；(7)将衬底晶圆剥离下来形成无衬底结构的功率器件。本发明与现有技术相比的优点在于：(1)两次剥离保证所有的晶圆都不浪费；剥离下来的晶圆还可以重复使用。(2)制备的功率器件真正无衬底，最大限度降低功率器件的导通电阻。

Description

无衬底结构的功率器件制造工艺
技术领域
本发明涉及功率器件制备技术领域，特别涉及一种无衬底结构的功率器件制造工艺。
背景技术
对于功率器件，特别是低压功率器件，衬底电阻占整个器件导通电阻的比重很大，所以尽可能薄的衬底对降低器件的导通电阻意义重大。通常，用机械研磨的方式来减薄。这有两个问题，其一，受设备能力的限制，不太可能减薄到几个微米；其二，研磨工艺会浪费衬底材料，不利于环保。
发明内容
本发明所要解决技术问题在于针对现有功率器件制备过程中衬底电阻较大所带来的问题而提供一种无衬底结构的功率器件制造工艺。
本发明所要解决的技术问题可以通过以下技术方案来实现：
一种无衬底结构的功率器件制造工艺，由以下步骤组成：
(1)制备产品晶圆和衬底晶圆；
(2)在所述产品晶圆的正面注入氢离子形成一氢离子注入层；
(3)将所述衬底晶圆的正面进行多孔硅化，然后进行多孔硅氧化形成一层多孔硅氧化层；所述多孔硅氧化层的厚度为1～100um；
(4)将产品晶圆的氢离子注入层表面贴在衬底晶圆的多孔硅氧化层表面上；
(5)加热将产品晶圆的氢离子注入层以外的部分从氢离子注入层的层底处剥离掉然后对剥离面进行抛光处理；
(6)在产品晶圆的氢离子注入层上加工出功率器件；
(7)采用化学方法将衬底晶圆从产品晶圆的氢离子注入层表面与衬底晶圆的多孔硅氧化层的结合面处剥离下来形成无衬底结构的功率器件。
由于采用了如上的技术方案，本发明与现有技术相比的优点在于：
(1)两次剥离保证所有的晶圆都不浪费；剥离下来的晶圆还可以重复使用。
(2)制备的功率器件真正无衬底，最大限度降低功率器件的导通电阻。
附图说明
图1为产品晶圆注入氢离子的示意图。
图2为形成有多孔硅氧化层的衬底晶圆结构示意图。
图3为将产品晶圆的氢离子注入层表面贴在衬底晶圆的多孔硅氧化层表面上的示意图。
图4为加热将产品晶圆的氢离子注入层以外的部分从氢离子注入层的层底处剥离的示意图。
图5为在产品晶圆的氢离子注入层上加工出功率器件的示意图。
图6为采用化学方法将衬底晶圆从产品晶圆的氢离子注入层表面与衬底晶圆的多孔硅氧化层的结合面处剥离下来形成无衬底结构的功率器件的示意图。
具体实施方式
参见附图，图中给出的一种无衬底结构的功率器件制造工艺，由以下步骤组成：
(1)制备产品晶圆10和衬底晶圆20；
(2)参见图1，在产品晶圆10的正面注入氢离子形成一氢离子注入层11；氢离子的注入方法为现有技术，可参见中国专利200710186310.7公开的半导体衬底的制造方法等。
(3)参见图2，将衬底晶圆20的正面进行多孔硅化，然后进行多孔硅氧化形成一层多孔硅氧化层21；多孔硅氧化层21的厚度为1～100um；在衬底晶圆上形成多孔硅氧化层的方法为现有技术。
(4)参见图3，将产品晶圆10的氢离子注入层11表面贴在衬底晶圆20的多孔硅氧化层21表面上；
(5)加热将产品晶圆10的氢离子注入层11以外的部分12从氢离子注入层11的层底处剥离掉然后对剥离面进行抛光处理；
(6)在产品晶圆10的氢离子注入层11上按常规工艺加工出功率器件13；
(7)采用化学方法将衬底晶圆20从产品晶圆10的氢离子注入层10表面与衬底晶圆20的多孔硅氧化层21的结合面处剥离下来形成无衬底结构的功率器件13。

Claims (1)

1.一种无衬底结构的功率器件制造工艺，其特征在于，由以下步骤组成：
(1)制备产品晶圆和衬底晶圆；
(2)在所述产品晶圆的正表面注入氢离子在所述产品晶圆的正表面形成一氢离子注入层；
(3)将所述衬底晶圆的正表面进行多孔硅化，然后进行多孔硅氧化在所述衬底晶圆的正表面形成一层多孔硅氧化层；所述多孔硅氧化层的厚度为1～100um；
(4)将产品晶圆的氢离子注入层正表面贴在衬底晶圆的多孔硅氧化层正表面上；
(5)加热将产品晶圆的氢离子注入层以外的部分从氢离子注入层的层底处剥离掉然后对剥离面进行抛光处理；
(6)在产品晶圆的氢离子注入层上加工出功率器件；
(7)采用化学方法将衬底晶圆从产品晶圆的氢离子注入层表面与衬底晶圆的多孔硅氧化层的结合面处剥离下来形成无衬底结构的功率器件。
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