CN104067345B - 经改善低电压写入速度位单元 - Google Patents
经改善低电压写入速度位单元 Download PDFInfo
- Publication number
- CN104067345B CN104067345B CN201380005949.4A CN201380005949A CN104067345B CN 104067345 B CN104067345 B CN 104067345B CN 201380005949 A CN201380005949 A CN 201380005949A CN 104067345 B CN104067345 B CN 104067345B
- Authority
- CN
- China
- Prior art keywords
- pfet
- nfet
- pass
- drain
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261589570P | 2012-01-23 | 2012-01-23 | |
| US61/589,570 | 2012-01-23 | ||
| US13/746,528 | 2013-01-22 | ||
| US13/746,528 US9093125B2 (en) | 2012-01-23 | 2013-01-22 | Low voltage write speed bitcell |
| PCT/US2013/022777 WO2013126172A1 (en) | 2012-01-23 | 2013-01-23 | Improved low voltage write speed bitcell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104067345A CN104067345A (zh) | 2014-09-24 |
| CN104067345B true CN104067345B (zh) | 2017-05-03 |
Family
ID=48797076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201380005949.4A Active CN104067345B (zh) | 2012-01-23 | 2013-01-23 | 经改善低电压写入速度位单元 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US9093125B2 (enExample) |
| EP (1) | EP2807649B1 (enExample) |
| JP (1) | JP6038956B2 (enExample) |
| KR (1) | KR101601827B1 (enExample) |
| CN (1) | CN104067345B (enExample) |
| IN (1) | IN2014CN04993A (enExample) |
| TW (1) | TWI537945B (enExample) |
| WO (1) | WO2013126172A1 (enExample) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9335775B2 (en) * | 2014-06-23 | 2016-05-10 | International Business Machines Corporation | Integrated circuit having regulated voltage island power system |
| US9251875B1 (en) | 2014-09-26 | 2016-02-02 | Qualcomm Incorporated | Register file circuit and method for improving the minimum operating supply voltage |
| US9384825B2 (en) * | 2014-09-26 | 2016-07-05 | Qualcomm Incorporated | Multi-port memory circuits |
| US9583180B2 (en) * | 2015-06-05 | 2017-02-28 | Cisco Technology, Inc. | Low-power row-oriented memory write assist circuit |
| US9646681B1 (en) | 2016-04-25 | 2017-05-09 | Qualcomm Incorporated | Memory cell with improved write margin |
| US10163524B2 (en) | 2016-06-22 | 2018-12-25 | Darryl G. Walker | Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor |
| US9940999B2 (en) | 2016-06-22 | 2018-04-10 | Darryl G. Walker | Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits |
| US9786364B1 (en) * | 2016-12-16 | 2017-10-10 | Stmicroelectronics International N.V. | Low voltage selftime tracking circuitry for write assist based memory operation |
| KR102021601B1 (ko) * | 2017-09-22 | 2019-09-16 | 경북대학교 산학협력단 | 초저전압 메모리 장치 및 그 동작 방법 |
| US10446223B1 (en) * | 2018-08-29 | 2019-10-15 | Bitfury Group Limited | Data storage apparatus, and related systems and methods |
| US11074966B2 (en) * | 2018-10-31 | 2021-07-27 | Taiwan Semiconductor Manufacturing Company, Ltd | Method and system to balance ground bounce |
| US11183234B2 (en) * | 2019-11-25 | 2021-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bitcell supporting bit-write-mask function |
| CN111951849A (zh) * | 2020-08-20 | 2020-11-17 | 海光信息技术有限公司 | 存储单元、随机静态存储器及寄存器堆 |
| US11955171B2 (en) | 2021-09-15 | 2024-04-09 | Mavagail Technology, LLC | Integrated circuit device including an SRAM portion having end power select circuits |
| CN116798474A (zh) * | 2022-03-17 | 2023-09-22 | 长鑫存储技术有限公司 | 电子设备及其驱动方法 |
| CN118629457A (zh) * | 2024-08-12 | 2024-09-10 | 苏州宽温电子科技有限公司 | 一种9t-sram单元、数据存取方法及芯片 |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58122693A (ja) * | 1982-01-14 | 1983-07-21 | Nippon Telegr & Teleph Corp <Ntt> | メモリ回路 |
| JPH02108297A (ja) * | 1988-10-18 | 1990-04-20 | Nippon Telegr & Teleph Corp <Ntt> | メモリセル回路 |
| US6925025B2 (en) * | 2003-11-05 | 2005-08-02 | Texas Instruments Incorporated | SRAM device and a method of powering-down the same |
| JP2006209945A (ja) * | 2005-01-31 | 2006-08-10 | Toshiba Corp | メモリセルおよびメモリセルの安定化方法 |
| JP2007172715A (ja) * | 2005-12-20 | 2007-07-05 | Fujitsu Ltd | 半導体記憶装置およびその制御方法 |
| US7460400B1 (en) * | 2007-08-22 | 2008-12-02 | Nscore Inc. | Nonvolatile memory utilizing MIS memory transistors with bit mask function |
| US7718482B2 (en) * | 2007-10-10 | 2010-05-18 | Texas Instruments Incorporated | CD gate bias reduction and differential N+ poly doping for CMOS circuits |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4198201B2 (ja) | 1995-06-02 | 2008-12-17 | 株式会社ルネサステクノロジ | 半導体装置 |
| FR2793064B1 (fr) * | 1999-04-30 | 2004-01-02 | St Microelectronics Sa | Memoire a courant de fuite reduit |
| JP5076462B2 (ja) * | 2005-12-28 | 2012-11-21 | ソニー株式会社 | 半導体メモリデバイス |
| US7269055B2 (en) | 2006-02-13 | 2007-09-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM device with reduced leakage current |
| US7324368B2 (en) | 2006-03-30 | 2008-01-29 | Arm Limited | Integrated circuit memory with write assist |
| US20070268740A1 (en) * | 2006-05-12 | 2007-11-22 | Aly Rami E | Ultra low power SRAM cell design |
| US7512030B2 (en) * | 2006-08-29 | 2009-03-31 | Texas Instruments Incorporated | Memory with low power mode for WRITE |
| US7630228B2 (en) | 2007-08-30 | 2009-12-08 | Intel Corporation | Methods and apparatuses for operating memory |
| US20090086556A1 (en) | 2007-09-27 | 2009-04-02 | Sapumal Wijeratne | Methods and apparatuses for operating memory |
| TWI346338B (en) * | 2007-10-23 | 2011-08-01 | Nat Univ Tsing Hua | Access unit for a static random accesss memory |
| US7852661B2 (en) * | 2008-10-22 | 2010-12-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Write-assist SRAM cell |
| US7839173B1 (en) | 2009-08-11 | 2010-11-23 | Xilinx, Inc. | High speed, low power signal level shifter |
| US8320203B2 (en) | 2010-03-26 | 2012-11-27 | Intel Corporation | Method and system to lower the minimum operating voltage of register files |
| JP2011248932A (ja) * | 2010-05-21 | 2011-12-08 | Panasonic Corp | 半導体記憶装置 |
| US8462542B2 (en) * | 2010-06-24 | 2013-06-11 | Texas Instruments Incorporated | Bit-by-bit write assist for solid-state memory |
| US8406077B2 (en) | 2010-07-01 | 2013-03-26 | Qualcomm Incorporated | Multi-voltage level, multi-dynamic circuit structure device |
| US8451652B2 (en) * | 2010-12-02 | 2013-05-28 | Lsi Corporation | Write assist static random access memory cell |
-
2013
- 2013-01-22 US US13/746,528 patent/US9093125B2/en active Active
- 2013-01-23 EP EP13706100.8A patent/EP2807649B1/en active Active
- 2013-01-23 TW TW102102579A patent/TWI537945B/zh not_active IP Right Cessation
- 2013-01-23 CN CN201380005949.4A patent/CN104067345B/zh active Active
- 2013-01-23 KR KR1020147023265A patent/KR101601827B1/ko not_active Expired - Fee Related
- 2013-01-23 JP JP2014553537A patent/JP6038956B2/ja active Active
- 2013-01-23 IN IN4993CHN2014 patent/IN2014CN04993A/en unknown
- 2013-01-23 WO PCT/US2013/022777 patent/WO2013126172A1/en not_active Ceased
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58122693A (ja) * | 1982-01-14 | 1983-07-21 | Nippon Telegr & Teleph Corp <Ntt> | メモリ回路 |
| JPH02108297A (ja) * | 1988-10-18 | 1990-04-20 | Nippon Telegr & Teleph Corp <Ntt> | メモリセル回路 |
| US6925025B2 (en) * | 2003-11-05 | 2005-08-02 | Texas Instruments Incorporated | SRAM device and a method of powering-down the same |
| JP2006209945A (ja) * | 2005-01-31 | 2006-08-10 | Toshiba Corp | メモリセルおよびメモリセルの安定化方法 |
| JP2007172715A (ja) * | 2005-12-20 | 2007-07-05 | Fujitsu Ltd | 半導体記憶装置およびその制御方法 |
| US7460400B1 (en) * | 2007-08-22 | 2008-12-02 | Nscore Inc. | Nonvolatile memory utilizing MIS memory transistors with bit mask function |
| US7718482B2 (en) * | 2007-10-10 | 2010-05-18 | Texas Instruments Incorporated | CD gate bias reduction and differential N+ poly doping for CMOS circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20140120919A (ko) | 2014-10-14 |
| KR101601827B1 (ko) | 2016-03-09 |
| EP2807649B1 (en) | 2020-02-19 |
| US20130188434A1 (en) | 2013-07-25 |
| US9093125B2 (en) | 2015-07-28 |
| CN104067345A (zh) | 2014-09-24 |
| IN2014CN04993A (enExample) | 2015-09-18 |
| TWI537945B (zh) | 2016-06-11 |
| JP2015504228A (ja) | 2015-02-05 |
| EP2807649A1 (en) | 2014-12-03 |
| TW201346907A (zh) | 2013-11-16 |
| WO2013126172A1 (en) | 2013-08-29 |
| JP6038956B2 (ja) | 2016-12-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104067345B (zh) | 经改善低电压写入速度位单元 | |
| US8654570B2 (en) | Low voltage write time enhanced SRAM cell and circuit extensions | |
| US9627042B2 (en) | Static random access memory cell having improved write margin for use in ultra-low power application | |
| US20120275236A1 (en) | Method and Apparatus for Power Domain Isolation during Power Down | |
| TWI601135B (zh) | 適合於fin場效應電晶體(finfet)工藝的sram單元 | |
| US10037795B2 (en) | Seven-transistor static random-access memory bitcell with reduced read disturbance | |
| Jiao et al. | Low power and robust memory circuits with asymmetrical ground gating | |
| CN106716541B (zh) | 用于改善最小工作供电电压的寄存器组电路和方法 | |
| Yang et al. | Impacts of NBTI/PBTI on timing control circuits and degradation tolerant design in nanoscale CMOS SRAM | |
| KR20110118689A (ko) | 듀얼-기술 트랜지스터들을 사용한 저누설 고성능 정적 랜덤 액세스 메모리 셀 | |
| CN103208305A (zh) | 歪斜的静态随机存取存储器单元 | |
| US8659963B2 (en) | Enhanced power savings for memory arrays | |
| Wang et al. | Charge recycling 8T SRAM design for low voltage robust operation | |
| US8942052B2 (en) | Complementary metal-oxide-semiconductor (CMOS) min/max voltage circuit for switching between multiple voltages | |
| US9496024B1 (en) | Automatic latch-up prevention in SRAM | |
| Panchal et al. | Half selection resilient energy efficient HSR11T SRAM cell at subthreshold region with 0.09 fJ/bit hold energy | |
| Kumar et al. | SRAM cell performance in deep submicron technology | |
| Bai et al. | A robust high density 7t sram bitcell for subthreshold applications | |
| Kumar | Effect of temperature & supply voltage variation on the Stability of existing 7T SRAM cell | |
| Sinangil | Ultra-dynamic voltage scalable (U-DVS) SRAM design considerations | |
| Aykenar et al. | Adapting the columns of storage components for lower static energy dissipation | |
| Rabaey | Optimizing Power@ Design Time–Memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |