CN104049203B - Pin with boundary scanning and testing function and integrated circuit with same - Google Patents
Pin with boundary scanning and testing function and integrated circuit with same Download PDFInfo
- Publication number
- CN104049203B CN104049203B CN201410171098.7A CN201410171098A CN104049203B CN 104049203 B CN104049203 B CN 104049203B CN 201410171098 A CN201410171098 A CN 201410171098A CN 104049203 B CN104049203 B CN 104049203B
- Authority
- CN
- China
- Prior art keywords
- pin
- boundary scan
- signal
- output
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a pin with a boundary scanning and testing function and an integrated circuit with the pin. The pin comprises at least one boundary scanning register, a boundary scanning signal input pin, a boundary scanning signal output pin and a TAP control signal end receiving boundary scanning control signals from a TAP controller. Due to the fact that the boundary scanning register is integrated in the pin, insertion of JTAG testing logic of the input, output and control signals of the pin outside the pin is reduced in the chip implementation process, meanwhile, negative influence caused by the position of the JTAG testing logic of the input, output and control signals of the pin on the timing sequence can be avoided in the locating and wiring process, and rapid convergence of the timing sequence is facilitated.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly, it is related to a kind of built-in pin of boundary scan register
With the integrated circuit including this pin.
Background technology
Boundary scan technique is a kind of testability construction design method being applied to digital integrated circuit device.So-called " side
Boundary " refers to that test circuit is arranged on the surrounding of IC-components logic function circuit, positioned near device input, output and
The boundary of controlling switch.So-called " scanning " refer to interface unit respectively input, export and controlling switch test circuit actually
One group of serial shift register, this serial shift register is called " scanning pattern ", along this paths can input by
The various codings that " 0 " and " 1 " forms, carry out the detection of " scanning " formula, judge whether it is correct from output result to circuit.
Fig. 1 is the schematic diagram of the top level structure illustrating the IC chip based on prior art.As shown in figure 1, every
The individual pin (PAD) that will be test for nearby is arranged with the boundary scan register (BSR being made up of register and combinational logic：
Boundary scan register), meanwhile, it is single input, single output, input and output or tri-state pin according to pin
And the quantity of the boundary scan register arranged in its vicinity is also different.For example, for as shown in Figure 2, there is input pin
The tri-state pin of input, output pin output and controlling switch control, it nearby should arrange that three boundary scans are deposited
Device.
As shown in figure 1, all of boundary scan register is all connected to integrated circuit signal internal logic (Core), and institute
Some boundary scan register being linked in sequence according to movement, thus constitute a JTAG scan chain.For JTAG/scan
Test data input (TDI) of test, test clock input (TCK), test pattern select (TMS), test reset input
(TRST) export (TDO) related signal and provided by test access port (TAP) controller or be input to TAP control with test data
Device processed, thus realized the control of JTAG scan chain by TAP controller, thus realize the input of pin, output and control signal
Test.External drive is displaced into each boundary scan register, then to tested PAD's successively by the TDI of TAP controller
Input pin applies excitation to be tested, finally by test result successively from TDO removal or parallel from tested PAD output pin
Output.By observing the output result of TDO and tested PAD output pin, to judge whether the connection of PAD goes wrong.
As described above, each boundary scan register is to be made up of register and combinational logic, combinational logic is by function
Path and test path separately, and can carry out the switching in path under functional mode and test pattern.Feature path is pipe
Access path between pin and internal logic, due to the insertion of boundary scan register, exists many between pin and internal logic
Individual boundary scan register unit, therefore feature path receive the impact of boundary scan register position.
Do not affect feature path for more preferable sequential with, it is necessary to by border during the placement-and-routing of integrated circuit
Scan register is placed on the side of each tested pin, the particularly combinational logic within boundary scan register, because group
It is logical that by handoff functionality path and test path, the position of combinational logic directly affects feature path, if Path selection
It is far apart from pin that combinational logic is placed, then feature path will be greatly affected.
Content of the invention
In view of the above-mentioned problems in the prior art, the invention provides a kind of boundary scan testing function that is integrated with
Pin and the integrated circuit including this pin.
According to an aspect of the present invention, there is provided a kind of pin for integrated circuit, described pin includes at least one
Boundary scan register, boundary scan signal input pin, boundary scan signal output pin and from test access port
(TAP) controller receives the TAP control signal end of boundary scan control signal.
Preferably, described TAP control signal end include from TAP controller receive clock signal test clock input and
The test pattern receiving test mode select signal from TAP controller selects end.
Preferably, when described pin is input pin, described pin includes the signal input pin for receipt signal,
And described at least one boundary scan register includes an input boundary scan register being connected to described input pin.
Preferably, when described pin is output pin, described pin also includes drawing for the signal output of output signal
Pin, and at least one boundary scan register described includes being connected to an output boundary scanning of described output pin and deposits
Device.
Preferably, when described pin is input/output pin, the signal that described pin is also included for receipt signal is defeated
Enter pin and the signal output pin for output signal, and at least one boundary scan register described includes being connected respectively to
The input boundary scan register of input pin and output pin and output boundary scan register.
Preferably, when described pin is tri-state pin, described pin also includes drawing for the signal input of receipt signal
Pin, the signal output pin for output signal and for receiving the control signal pin of control signal, and described at least one
Boundary scan register includes the input boundary scan being connected respectively to described input pin, output pin and control signal pin
Register, output boundary scan register and control boundary scan register.
Preferably, at least one boundary scan register described is the boundary scan register based on JTAG/scan test.
Preferably, at least one boundary scan register is believed via described boundary scan signal input pin and boundary scan
Number output pin is connected with other pins and is formed for JTAG scan chain.
According to a further aspect in the invention, there is provided a kind of integrated circuit with pin as above.
Due to being integrated with boundary scan register according in pin provided by the present invention, thus decrease chip realizing
Insertion beyond pin for the jtag test logic of the input of pin, output and control signal in journey, simultaneously in placement-and-routing,
The negative of the sequential aspect that the position of the jtag test logic of the input by pin, output and control signal brought can be avoided
Face rings, and is conducive to the Fast Convergent of sequential.
Brief description
By the description below in conjunction with the accompanying drawings embodiment being carried out, these and/or other aspect of the present invention and advantage will
Can be made apparent from and it is more readily appreciated that wherein：
Fig. 1 is the schematic diagram of the top level structure illustrating the IC chip based on prior art；
Fig. 2 is the schematic diagram illustrating tri-state supervisor；
Fig. 3 is the diagram of the pin being integrated with boundary scan register illustrating the exemplary embodiment according to the present invention；
Fig. 4 A, Fig. 4 B and Fig. 4 C are that control boundary scan register, output boundary scan register and input are shown respectively
The schematic diagram of boundary scan register；
Fig. 5 is the collection with the pin being integrated with boundary scan register illustrating the exemplary embodiment according to the present invention
Become the schematic diagram of the top level structure of circuit.
Specific embodiment
Now the embodiment of the present invention is described in detail, its example is illustrated in the accompanying drawings, wherein, identical label begins
Represent same parts eventually.Below with reference to the accompanying drawings embodiment is described to explain the present invention.
Technology according to the present invention scheme, in integrated design circuit or pin (PAD) library unit design process, by border
Scan register (BSR) is integrated in PAD, and the BSR within PAD completes local J TAG scanning connection even, therefore in core
The insensitive TAP control logic in piece design process it is only necessary to insertion position, and the BSR coherent signal of PAD is coupled together i.e.
Achievable boundary scan test circuit.
Fig. 3 is the diagram of the pin being integrated with boundary scan register illustrating the exemplary embodiment according to the present invention.
Pin PAD shown in Fig. 3 is tri-state pin, i.e. that includes input pin input, output pin output and controlling switch
control.
Additionally, the pin PAD shown in Fig. 3 is also integrated with boundary scan register, i.e. described pin PAD further comprises even
The first boundary scan register 110 being connected to controlling switch control, the second boundary scanning being connected to output pin output
Register 120 and the 3rd boundary scan register 130 being connected to input pin input.
First boundary scan register 110, the second boundary scan register 120 and the 3rd boundary scan register in Fig. 3
130 can be implemented as the output boundary scan register shown in control boundary scan register as shown in Figure 4 A, Fig. 4 B respectively
With the input boundary scan register shown in Fig. 4 C.Due to defeated shown in the control boundary scan register shown in Fig. 4 A, Fig. 4 B
Go out the input boundary scan register shown in boundary scan register and Fig. 4 C and used in prior art, control boundary scan
Register, output boundary scan register are similar with the structure of input boundary scan register, therefore will not be described here.
In addition, the pin PAD shown in Fig. 3 may also include boundary scan signal input pin SI and boundary scan signal output
Pin SO.Described boundary scan signal input pin SI and boundary scan signal output pin SO are used for other pins and carry out signal
Exchange, i.e. receive signal to pin PAD and via described from other pins via described boundary scan signal input pin SI
Signal is exported other pins from described pin PAD by boundary scan signal output pin SO.
Additionally, the pin PAD shown in Fig. 3 may also include the TAP receiving boundary scan control signal from TAP controller controlling
Signal end CLOCK/MODE.For example, described TAP control signal end CLOCK/MODE includes receiving clock letter from TAP controller
Number test clock input pin and from TAP controller receive test mode select signal test pattern select pin.
Describe above in conjunction with Fig. 3 to be integrated with the embodiment of the tri-state pin of boundary scan register.In conjunction with described by Fig. 3
Technical scheme can be applicable to only to have input pin, the pin that only there is output pin and there is input and output pin.
For example, when pin is the pin only with input pin, its can only include being connected to input pin as Fig. 3 institute
The input boundary scan register of the 3rd boundary scan register 130 shown.
For example, when pin is the pin only with output pin, its can only include being connected to output pin as Fig. 3 institute
The output boundary scan register of the second boundary scan register 120 showing.
For example, when pin is the pin with input pin and output pin, it may include and is connected to input pin
The input boundary scan register of the 3rd boundary scan register 130 as shown in Figure 3 and be connected to output pin as Fig. 3
The output boundary scan register of shown the second boundary scan register 120.
Below, in conjunction with Fig. 5 description, there is the integrated circuit being integrated with boundary scan register.Fig. 5 is to illustrate according to this
The schematic diagram with the integrated circuit being integrated with boundary scan register of bright embodiment.
As shown in figure 5, integrated circuit according to embodiments of the present invention includes internal logic CORE, test access port
(TAP) controller 200 and multiple pin, wherein, the plurality of pin include above with reference to the input pin described by Fig. 3,
Output pin, input and output pin and tri-state pin.
Here, the test input that TAP controller 200 has for JTAG/scan test inputs (TDI) pin, test clock
Input (TCK) pin, test pattern select (TMS) pin, test reset input (TRST) pin and test data output (TDO)
Pin.Due to TAP control 200 and its pin can be realized by the TAP controller of prior art and its pin, therefore omit to its
Description.
Meanwhile, as described above, described each of multiple pin PAD of the boundary scan register pin that is integrated with all wraps
Boundary scan signal input pin SI and boundary scan signal output pin SO are included.
The boundary scan register included by multiple pins of the integrated circuit shown in Fig. 5 is believed by respective boundary scan
Number input pin SI and boundary scan signal output pin SO sequential series, thus form a JTAG scan chain, i.e. define
The JTAG/scan of the TDO of TDI pin → SI → SO → SI ... .. ... → SO → SI → SO → TAP controller of TAP controller
Chain, here, SI and SO represents the scanning input to boundary scan register or the scanning output from boundary scan register respectively.
JTAG/scan technology due to prior art can be applicable to the JTAG/scan of integrated circuit as shown in Figure 5, therefore
Omit the description of the JTAG/scan scheme to the integrated circuit shown in Fig. 5.
In technology according to the present invention scheme, due to boundary scan register (BSR) being integrated into pin (PAD), because
The position of the combinational logic of this boundary scan register and its inside has been limited in inside PAD, so the layout of integrated circuit
It is not necessary to consider the placement of BSR interrelated logic in wiring process, feature path will not be subject to shadow due to the position of combinational logic
Ring, be more beneficial for sequential Fast Convergent.
Although show and describing some embodiments of the present invention, it will be understood by those skilled in the art that not taking off
In the case of the principle and spirit of the present invention being limited its scope by claim and its equivalent, can be to these embodiments
Modify.
Claims (9)
1. a kind of pin for integrated circuit is it is characterised in that include：
At least one boundary scan register；
Boundary scan signal input pin；
Boundary scan signal output pin；And
Receive the test access port control signal end of boundary scan control signal from test access port controller.
2. pin according to claim 1 is it is characterised in that described test access port control signal end is included from test
Access port controller receives the test clock input of clock signal and receives test pattern from test access port controller
The test pattern of selection signal selects end.
3. pin according to claim 1 is it is characterised in that when described pin is input pin, described pin includes
For the signal input pin of receipt signal, and at least one boundary scan register described includes being connected to described input pin
One input boundary scan register.
4. pin according to claim 1 is it is characterised in that when described pin is output pin, described pin also wraps
Include the signal output pin for output signal, and at least one boundary scan register described includes being connected to described output and draws
One output boundary scan register of pin.
5. pin according to claim 1 it is characterised in that when described pin be input/output pin when, described pin
Also include the signal input pin for receipt signal and the signal output pin for output signal, and at least one side described
Boundary's scan register includes being connected respectively to input pin and the input boundary scan register of output pin and output boundary is swept
Retouch register.
6. pin according to claim 1 is it is characterised in that when described pin is tri-state pin, described pin also wraps
Include the signal input pin for receipt signal, the signal output pin for output signal and the control for receiving control signal
Signal pins processed, and at least one boundary scan register described include being connected respectively to described input pin, output pin and
The input boundary scan register of control signal pin, output boundary scan register and control boundary scan register.
7. pin according to claim 1 is it is characterised in that at least one boundary scan register described is based on JTAG
The boundary scan register of sweep test.
8. pin according to claim 7 is it is characterised in that at least one boundary scan register is swept via described border
Retouch signal input pin to be connected with other pins with boundary scan signal output pin and formed for JTAG scan chain.
9. a kind of integrated circuit of the pin having as described in any claim in claim 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410171098.7A CN104049203B (en) | 2014-04-25 | 2014-04-25 | Pin with boundary scanning and testing function and integrated circuit with same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410171098.7A CN104049203B (en) | 2014-04-25 | 2014-04-25 | Pin with boundary scanning and testing function and integrated circuit with same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104049203A CN104049203A (en) | 2014-09-17 |
| CN104049203B true CN104049203B (en) | 2017-02-15 |
Family
ID=51502293
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410171098.7A Active CN104049203B (en) | 2014-04-25 | 2014-04-25 | Pin with boundary scanning and testing function and integrated circuit with same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104049203B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9791505B1 (en) * | 2016-04-29 | 2017-10-17 | Texas Instruments Incorporated | Full pad coverage boundary scan |
| CN106483950B (en) * | 2016-12-21 | 2019-03-29 | 中国南方航空工业(集团)有限公司 | Programmable logic device detection method and device |
| CN109192240B (en) * | 2018-08-28 | 2023-12-05 | 长鑫存储技术有限公司 | Boundary test circuit, memory and boundary test method |
| CN109387774A (en) * | 2018-12-05 | 2019-02-26 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of general-purpose circuit board suitable for boundary scan testing |
| CN113702798A (en) * | 2020-05-22 | 2021-11-26 | Oppo广东移动通信有限公司 | Boundary scan test method, device, equipment, chip and storage medium |
| CN113740710A (en) * | 2021-09-02 | 2021-12-03 | 展讯通信（上海）有限公司 | Output test circuit and chip |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6351836B1 (en) * | 1998-06-08 | 2002-02-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with boundary scanning circuit |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5379302A (en) * | 1993-04-02 | 1995-01-03 | National Semiconductor Corporation | ECL test access port with low power control |
| WO2003093843A1 (en) * | 2002-05-01 | 2003-11-13 | Logicvision(Canada), Inc | Circuit and method for adding parametric test capability to digital boundary scan |
| DE102004027860A1 (en) * | 2004-06-08 | 2006-01-05 | Siemens Ag | Test method and test device for testing an integrated circuit |
| US7928760B2 (en) * | 2004-09-27 | 2011-04-19 | Nxp B.V. | Integrated circuit with input and/or output bolton pads with integrated logic |
| US8489947B2 (en) * | 2010-02-15 | 2013-07-16 | Mentor Graphics Corporation | Circuit and method for simultaneously measuring multiple changes in delay |
| CN102305907A (en) * | 2011-05-31 | 2012-01-04 | 中国科学院深圳先进技术研究院 | Test method and system for multichip encapsulating structure |
| CN102183727B (en) * | 2011-06-01 | 2013-05-01 | 浙江大学 | Boundary scanning test method with error detection function |
| JP2013131282A (en) * | 2011-12-22 | 2013-07-04 | Elpida Memory Inc | Semiconductor device |
| CN202404207U (en) * | 2011-12-31 | 2012-08-29 | 杭州士兰微电子股份有限公司 | Testing device for plasma display panel |
| CN103675576B (en) * | 2012-09-18 | 2016-02-10 | 英业达科技有限公司 | Based on chip connecting test system and the method thereof of boundary scan |
| CN103680608A (en) * | 2012-09-18 | 2014-03-26 | 英业达科技有限公司 | System and method for improving chip burning speed of boundary scan technology |
| US8924803B2 (en) * | 2012-10-17 | 2014-12-30 | Nanya Technology Corporation | Boundary scan test interface circuit |
| CN103091627B (en) * | 2013-01-09 | 2015-02-25 | 中国科学院微电子研究所 | Configurable boundary scan register chain circuit |
-
2014
- 2014-04-25 CN CN201410171098.7A patent/CN104049203B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6351836B1 (en) * | 1998-06-08 | 2002-02-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with boundary scanning circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104049203A (en) | 2014-09-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104049203B (en) | Pin with boundary scanning and testing function and integrated circuit with same | |
| US7352169B2 (en) | Testing components of I/O paths of an integrated circuit | |
| US9903913B2 (en) | Scan or JTAG controllable capture clock generation | |
| KR101006822B1 (en) | Transparent test method and scan flip-flop | |
| CN100587508C (en) | Realize the scan chain and the method for high speed testing | |
| US9081064B2 (en) | IC scan cell coupled to TSV top and bottom contacts | |
| JP4808051B2 (en) | Semiconductor integrated circuit device and test method thereof | |
| CN104321655B (en) | The integrated circuit of the test pattern control signal for sweep test can be generated | |
| US7269770B1 (en) | AC coupled line testing using boundary scan test methodology | |
| US7401277B2 (en) | Semiconductor integrated circuit and scan test method therefor | |
| US7181705B2 (en) | Hierarchical test circuit structure for chips with multiple circuit blocks | |
| CN109406902A (en) | Scan logic aging testing system | |
| US6173428B1 (en) | Apparatus and method for testing using clocked test access port controller for level sensitive scan designs | |
| US20030159124A1 (en) | System and method for generating integrated circuit boundary register description data | |
| US8914689B2 (en) | Controlled toggle rate of non-test signals during modular scan testing of an integrated circuit | |
| CN104903736B (en) | For dynamically distributing the circuit and method of sweep test resource | |
| CN103487747B (en) | The scanning subchain type test structure of coincidence boundary scanning standard and method of testing | |
| US7607057B2 (en) | Test wrapper including integrated scan chain for testing embedded hard macro in an integrated circuit chip | |
| CN103091627B (en) | Configurable boundary scan register chain circuit | |
| KR100694315B1 (en) | At-speed interconnect test controller for system on chip using multiple system clock and having heterogeneous cores | |
| US7702979B2 (en) | Semiconductor integrated circuit incorporating test configuration and test method for the same | |
| JPH0763821A (en) | Test circuit | |
| CN110717307B (en) | SIP device testability method based on boundary scanning circuit | |
| US7552372B2 (en) | Semiconductor device and test method thereof | |
| US6865703B2 (en) | Scan test system for semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |