CN103680608A - System and method for improving chip burning speed of boundary scan technology - Google Patents
System and method for improving chip burning speed of boundary scan technology Download PDFInfo
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- CN103680608A CN103680608A CN201210349566.6A CN201210349566A CN103680608A CN 103680608 A CN103680608 A CN 103680608A CN 201210349566 A CN201210349566 A CN 201210349566A CN 103680608 A CN103680608 A CN 103680608A
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Abstract
The invention relates to a system and a method for improving the chip burning speed of a boundary scan technology. The electric potential of a pin of a chip is captured to a boundary scan unit according to the boundary scan technology, so that the frequency of pushing the electric potential by a boundary scan chain can be reduced, and the technical effects of improving the chip burning speed and efficiency of the boundary scan technology can be achieved.
Description
Technical field
The present invention relates to system and the method thereof of a kind of chip (chip) burning (programming), relate in particular to a kind of boundary scan technique that improves to the system of burning chip speed and method thereof.
Background technology
Burning/recording chip (EEPROM or the Flash of tradition and current trend ... Deng, at this only for illustrating, with this, do not limit to application category of the present invention) mode is: chip is put in the fixture of cd-rom recorder, then use cd-rom recorder to carry out burning, this mode burning efficiency is high, and is used in a large number.
But, if will carry out burning for the chip on circuit board, need so chip to weld from circuit board, then burning, finally weldering is got back to circuit board and is got on again, this method complicated operation that chip soldering is got off, circuit board is had to damage, and may cause other problem.
Therefore, a kind of boundary scan (Boundary Scan) technology has been proposed, it uses JTAG hardware interface, test data input pin (Test Data Input by chip, TDI) push current potential, utilize boundary scan cell (Boundary Scan Cell) the control chip pin in chip, analogy goes out the needed agreement of burning/recording chip, and then burning/recording chip is controlled, complete read-write operation.
And often push a current potential forward for boundary scan chain (Boundary Scan Chain), all at least need the one-period time, so the control rate of boundary scan technique to pin, the boundary scan cell corresponding with pin is relevant in the position of whole boundary scan chain, from test data input pin more away from, need the current potential of propelling movement more, so corresponding recordable time can be longer, and also just lower for the efficiency of burning chip.
In sum, since known prior art is medium-term and long-term, exist boundary scan technique to pass for a long time and the problem of inefficiency the burning chip time always, be therefore necessary to propose improved technological means, solve this problem.
Summary of the invention
Because prior art exists boundary scan technique to pass for a long time and the problem of inefficiency the burning chip time, the present invention discloses a kind of boundary scan technique that improves then to the system of burning chip speed and method thereof, wherein:
The system of the disclosed raising boundary scan technique of the present invention to burning chip speed, it comprises: chip and chip, and chip and chip are to be all electrically connected on circuit board, wherein, chip is supported JTAG1149.1 standard, and chip also comprises: a plurality of pins and a plurality of boundary scan cell.
It is the pin that in the pin of chip, definition has JTAG, the pin of JTAG is respectively test data input pin, test data output pin (Test Data Output, TDO), TCK pin and TMS pin, in the pin of chip, definition has at least one data input pin and at least one data output pin; And a plurality of boundary scan cells of chip are electrically connected each other mutually, wherein: N to N+A boundary scan cell and the electric connection of data output pin, and N-B to N-B+A boundary scan cell with the electric connection of data input pin and in order to capture the current potential of (capture) data input pin, wherein: N, A and B are that positive integer and N are greater than B and B is greater than A; And test data input pin is electrically connected to the 1st boundary scan cell, and test data output pin is electrically connected to last boundary scan cell, to be combined into boundary scan chain.
N-B is upgraded the current potential of storage data input pin by data input pin to N-B+A boundary scan cell, then N-B is pushed by boundary scan chain to N-B+A the stored current potential of boundary scan cell, when N-B is pushed to respectively to N to N+A boundary scan cell to N-B+A the stored current potential of boundary scan cell, be updated to data output pin to N+A the stored current potential of boundary scan cell by N is individual.
Controlling pin for the A of chip is electrically connected with data output pin respectively, it is individual during to N+A boundary scan cell when N-B is pushed to N to N-B+A the stored current potential of boundary scan cell, N is updated to data output pin to N+A the stored current potential of boundary scan cell, chip according to the current potential of data output pin so that chip is carried out to burning.
The method of the disclosed raising boundary scan technique of the present invention to burning chip speed, it comprises the following step:
First, be fixed on circuit board and there are a plurality of pins and support in the chip of JTAG1149.1 standard, definition test data input pin, test data output pin, TCK pin and TMS pin, in the pin of chip, definition has at least one data input pin and at least one data output pin, then, in chip, there are a plurality of boundary scan cells, boundary scan cell is electrically connected each other mutually, wherein: N to N+A boundary scan cell and the electric connection of data output pin, and N-B is to N-B+A boundary scan cell and the electric connection of data input pin and in order to the current potential of acquisition data input pin, wherein: N, A and B are that positive integer and N are greater than B and B is greater than A, and test data input pin is electrically connected to the 1st boundary scan cell, and test data output pin is electrically connected to last boundary scan cell, to be combined into boundary scan chain, then, N-B is upgraded the current potential of storage data input pin by data input pin to N-B+A boundary scan cell, N-B is pushed by boundary scan chain to N-B+A the stored current potential of boundary scan cell, it is individual during to N+A boundary scan cell when N-B is pushed to respectively to N to N-B+A the stored current potential of boundary scan cell, N is updated to data output pin to N+A the stored current potential of boundary scan cell, and N-B can again be passed through data input pin to N-B+A boundary scan cell and upgrade storage current potential, finally, A the control pin that is fixed on the chip on circuit board is electrically connected with data output pin respectively, it is individual during to N+A boundary scan cell when N-B is pushed to N to N-B+A the stored current potential of boundary scan cell, N is updated to data output pin to N+A the stored current potential of boundary scan cell, chip according to the current potential of data output pin so that chip is carried out to burning.
The disclosed System and method for of the present invention as above, and the difference between prior art is that the N in chip of the present invention is individual to N+A boundary scan cell and the electric connection of data output pin, and N-B is to N-B+A boundary scan cell and the electric connection of data input pin and in order to the current potential of acquisition data input pin, by boundary scan chain, by N-B, to N-B+A the stored current potential of boundary scan cell, push to respectively N individual to N+A boundary scan cell, then N is updated to data output pin to N+A the stored current potential of boundary scan cell, chip according to the current potential of data output pin so that chip is carried out to burning.
By above-mentioned technological means, the present invention can reach and improve the technique effect of boundary scan technique to burning chip speed and efficiency.
Accompanying drawing explanation
Figure 1 shows that the system block diagrams of the disclosed raising boundary scan technique of the present invention to burning chip speed.
Figure 2 shows that the method flow diagram of the disclosed raising boundary scan technique of the present invention to burning chip speed.
Figure 3 shows that the configuration diagram of the disclosed raising boundary scan technique of the present invention to burning chip speed.
Critical piece Reference numeral:
10 chips
11 pins
111 test data input pins
112 test data output pins
113 data input pins
1131 data input pins
1132 data input pins
114 data output pins
12 boundary scan cells
121 boundary scan cells
122 boundary scan cells
123 boundary scan cells
20 chips
21 control pin
30 circuit boards
In step 120 chip, there are a plurality of boundary scan cells, boundary scan cell is electrically connected each other mutually, wherein: N is electrically connected to N+A boundary scan cell and data output pin, and N-B is individual to N-B+A boundary scan cell and the electric connection of data input pin and in order to the current potential of acquisition data input pin
A the control pin that step 150 is fixed on the chip on circuit board is electrically connected with data output pin respectively, it is individual during to N+A boundary scan cell when N-B is pushed to N to N-B+A the stored current potential of boundary scan cell, N is updated to data output pin to N+A the stored current potential of boundary scan cell, chip according to the current potential of data output pin so that chip is carried out to burning
Embodiment
Below with reference to drawings and Examples, describe embodiments of the present invention in detail, thus the present invention's implementation procedure how application technology means solve technical matters and reach technique effect can be fully understood and be implemented according to this.
First the system of the disclosed raising boundary scan technique of the present invention to burning chip speed below to be described, and please refer to shown in Fig. 1, Figure 1 shows that the system block diagrams of the disclosed raising boundary scan technique of the present invention to burning chip speed.
The system of the disclosed raising boundary scan technique of the present invention to burning chip speed, it comprises: chip 10 and chip 20, and chip 10 and chip 20 are to be all electrically connected on circuit board 30, circuit board 30 can be motherboard, video card, sound card, expansion board ... Deng, at this, only for illustrating, with this, do not limit to application category of the present invention.
And in a plurality of pins 11 of chip 10, defining test data input pin 111, test data output pin 112, TCK pin (not shown) and TMS pin (not shown), in the pin of chip, definition has at least one data input pin 113 and at least one data output pin 114.
And N in boundary scan cell 12 to N+A boundary scan cell 12 and 114 electric connections of data output pin, in boundary scan technique, support the pin of chip 10 11 current potentials to capture in boundary scan cell 12, therefore N-B is individual individual to the current potential of N-B+A boundary scan cell 12 in order to acquisition data input pin 113 with 113 electric connections of data input pin and N-B to N-B+A boundary scan cell 12.
And being positive integer and N, above-mentioned N, A and B be greater than B and B is greater than A, and above-mentioned current potential is 0(and is expressed as electronegative potential) or 1(be expressed as noble potential), the current potential that N-B captures to N-B+A boundary scan cell 12 is 0 or 1 potential value.
Particularly, suppose that the 500th (being that N is 500) boundary scan cell 12 and the 501st (being that A is 1) boundary scan cell 12 are electrically connected with data output pin 114, and the 464th (being that B is 36) boundary scan cell 12 and the 465th boundary scan cell 12 are electrically connected with data input pin 113, at this, only for illustrating, with this, do not limit to application category of the present invention.
Then, test data input pin 111 is electrically connected to the 1st boundary scan cell, and test data output pin 112 is electrically connected to last boundary scan cell, to be combined into boundary scan chain, and controlling pin 21 for the A of chip 20 is electrically connected with data output pin 114 respectively, above-mentioned chip 20 can be the writable ROM (read-only memory) of electric erasable (Electrically-Erasable Programmable Read-Only Memory, EEPROM) or flash memory (Flash Memory), at this only for illustrating, with this, do not limit to application category of the present invention.
In boundary scan technique except supporting that the pin of chip 10 11 current potentials are captured in boundary scan cell 12, also support boundary scan cell 12 current potentials to push in boundary scan chain forward, the 1st current potential can first capture to the 1st boundary scan cell 12, then again the 2nd current potential captured to the 1st boundary scan cell 12, and the current potential that was originally stored in the 1st boundary scan cell 12 can be pushed to the 2nd boundary scan cell 12, the rest may be inferred below, at this, no longer repeat, and the current potential that can support boundary scan cell 12 outputs on the pin 11 of chip 10, and the every propelling movement of boundary scan chain is the current potential in described boundary scan cell once, need a time cycle.
Therefore when needs are simulated burning to chip 20, can first from test data input pin 111, current potential be pushed to boundary scan cell 12 one by one, when current potential is pushed to N to N+A boundary scan cell 12, it is the individual current potential to N+A boundary scan cell 12 of exportable N, by repeatedly, to being electrically connected to the control of control pin 21 potential change of chip 20, and then analogy goes out the needed sequential of burning/recording chip 20 and agreement.
But because N-B is to the direct current potential of acquisition data input pin 113 of N-B+A boundary scan cell, therefore when needs are simulated burning to chip 20, from test data input pin 111, current potential is pushed to N one by one to N+A boundary scan cell 12, only need the individual current potential to N-B+A boundary scan cell 12 of N-B to push to respectively N to N+A boundary scan cell 12, be that renewable N is individual to N+A the current potential that boundary scan cell 12 is stored, by repeatedly to being electrically connected to the control of control pin 21 potential change of chip 20, and then analogy goes out the needed sequential of burning/recording chip 20 and agreement, be chip 20 can by control N-B to the stored current potential of N-B+A boundary scan cell and push to N individual to N+A boundary scan cell 12 so that chip 20 is carried out to burning.
And that the present invention only needs current potential to push to respectively from N-B to N-B+A boundary scan cell 12 N is individual to N+A boundary scan cell 12, be that renewable N is individual to N+A the current potential that boundary scan cell 12 is stored, by repeatedly to being electrically connected to the control of control pin 21 potential change of chip 20, and then analogy goes out the needed sequential of burning/recording chip 20 and agreement, be chip 20 can by control N-B to the stored current potential of N-B+A boundary scan cell and push to N individual to N+A boundary scan cell 12 so that chip 20 is carried out to burning.
With respect to from test data input pin 111, current potential being pushed to N one by one to N+A boundary scan cell 12, when current potential is pushed to N to N+A boundary scan cell 12, be renewable and N the current potential to N+A boundary scan cell 12, by repeatedly to being electrically connected to the control of control pin 21 potential change of chip 20, and then analogy goes out the needed sequential of burning/recording chip 20 and agreement, be chip 20 can by control N-B to the stored current potential of N-B+A boundary scan cell and push to N individual to N+A boundary scan cell 12 chip 20 is carried out to burning, the cycle length of expending can effectively be saved, so that effectively improve for chip 20 burning efficiency.
Then, below will explain orally function mode of the present invention and flow process with an embodiment, following embodiment explanation describes the while shown in Fig. 1 and Fig. 2, Figure 2 shows that the present invention improves the method flow diagram of boundary scan technique to burning chip speed.
Please refer to shown in Fig. 3, Figure 3 shows that the present invention improves the configuration diagram of boundary scan technique to burning chip speed.
And suppose that the control pin 21(with the 501st boundary scan cell 121 and chip 20 is the CLK of chip 20) be electrically connected, and the control pin 21 of chip 20 first need to be set to noble potential (being 1), the control pin 21 of chip 20 is set to electronegative potential (being 0) again, and the time cycle is set as Ti.
The boundary scan technique of establishing criteria, first needs first by test data input pin 111, to be first set as noble potential (being 1), and the current potential of the 1st boundary scan cell 12 meeting acquisition test data input pins 111 is " 1 ".
Then, through cycle T i, again test data input pin 111 is first set as to electronegative potential (being 0), and the current potential that the 1st boundary scan cell 12 can capture test data input pin 111 is again " 0 ", and the 1st current potential that boundary scan cell 12 is previous pushed to the 2nd boundary scan cell 12(step 140 for " 1 ").
Then, through cycle T i, the current potential that the 1st boundary scan cell 12 can capture test data input pin 111 is again " 0 ", and the 1st current potential that boundary scan cell 12 is previous pushed to the 2nd boundary scan cell 12 for " 0 ", and the 2nd current potential that boundary scan cell 12 is previous pushed to the 3rd boundary scan cell 12(step 140 for " 1 ").
Then, the rest may be inferred until current potential is pushed to the 501st boundary scan cell 121 for " 1 ", take that to control control pin 21 potential change that are electrically connected to chip 20 be " 1 ", the CLK of chip 20 can be set as to noble potential (step 150).
Then, test data input pin 111 resets as electronegative potential (being 0), and the current potential of the 1st boundary scan cell 12 meeting acquisition test data input pins 111 is " 0 ".
Then, through cycle setting Ti, again test data input pin 111 is first set as to electronegative potential (being 0), and the current potential that the 1st boundary scan cell 12 can capture test data input pin 111 is again " 0 ", and the 1st current potential that boundary scan cell 12 is previous pushed to the 2nd boundary scan cell 12(step 140 for " 0 ").
Then, through cycle setting Ti, the current potential that the 1st boundary scan cell 12 can capture test data input pin 111 is again " 0 ", and the 1st current potential that boundary scan cell 12 is previous pushed to the 2nd boundary scan cell 12 for " 0 ", and the 2nd current potential that boundary scan cell 12 is previous pushed to the 3rd boundary scan cell 12(step 140 for " 0 ").
Then, the rest may be inferred, and to current potential being pushed to the 501st boundary scan cell 121 for " 0 ", take, to control control pin 21 potential change that are electrically connected to chip 20 be " 0 ", the CLK of chip 20 can be set as to electronegative potential (step 150).
And be Ti owing to pushing the time cycle of a current potential, therefore the CLK of chip 20 need to be set as to noble potential, reset as being needed T.T. of electronegative potential: 501 * Ti+501 * Ti=1002Ti.
And the present invention supposes that the 464th boundary scan cell 122 and the 465th boundary scan cell 123 are electrically connected with data input pin 1131 and data input pin 1132 respectively, and data input pin 1131 is always set as electronegative potential and data input pin 1132 is always set as noble potential, the current potential that the current potential of the 464th boundary scan cell 122 is always " 0 " and the 465th boundary scan cell 123 is thus always " 1 ".
The current potential of test data input pin 111 only needs the current potential " 1 " of the 465th boundary scan cell 123 to push to the 501st boundary scan cell 121, control pin 21 potential change that the control of take is electrically connected to chip 20 are " 1 ", the CLK of chip 20 can be set as to noble potential.
Then, the current potential of test data input pin 111 only needs the current potential " 0 " of the 464th boundary scan cell 123 to push to the 501st boundary scan cell 121, control pin 21 potential change that the control of take is electrically connected to chip 20 are " 0 ", the CLK of chip 20 can be set as to electronegative potential.
And be Ti owing to pushing the time cycle of a current potential, therefore the CLK of chip 20 need to be set as to noble potential, reset as being needed T.T. of electronegative potential: 36 * Ti+37 * Ti=73Ti.
Thus, can obtain method proposed by the invention and can effectively save the cycle length of expending with respect to the boundary scan technique of standard, by 1002Ti, be significantly reduced to 73Ti, and the present invention significantly promotes and is about 13(1002Ti ÷ 73Ti=13.726 with respect to the boundary scan technique efficiency of standard ...) doubly.
In sum, difference between known the present invention and prior art is that the N in chip of the present invention is individual to N+A boundary scan cell and the electric connection of data output pin, and N-B is to N-B+A boundary scan cell and the electric connection of data input pin and in order to the current potential of acquisition data input pin, by boundary scan chain, by N-B, to N-B+A the stored current potential of boundary scan cell, push to respectively N individual to N+A boundary scan cell, with chip according to N-B to the stored current potential of N-B+A boundary scan cell so that chip is carried out to burning.
By this technological means, can solve the existing boundary scan technique of prior art the burning chip time is pass for a long time and the problem of inefficiency, and then reach and improve the technique effect of boundary scan technique to burning chip speed and efficiency.
Although the disclosed embodiment of the present invention as above, yet described content is not in order to direct restriction scope of patent protection of the present invention.Any those skilled in the art are not departing under the prerequisite of the disclosed spirit and scope of the present invention, can do some changes what implement in form and in details.Scope of patent protection of the present invention, still must be as the criterion with the content that appending claims was limited.
Claims (10)
1. improve the system of boundary scan technique to burning chip speed, it is characterized in that, comprise:
Chip, described chip is electrically connected on circuit board, and described chip also comprises:
A plurality of pins, define test data input pin, test data output pin, at least one data input pin and at least one data output pin in described pin; And
A plurality of boundary scan cells, described boundary scan cell is electrically connected each other mutually, wherein:
N to N+A boundary scan cell and the electric connection of described data output pin, and N-B is to N-B+A boundary scan cell and the electric connection of described data input pin and in order to capture the current potential of described data input pin, wherein: N, A and B are that positive integer and N are greater than B and B is greater than A; And
Described test data input pin is electrically connected to the 1st boundary scan cell, and described test data output pin is electrically connected to last boundary scan cell, to be combined into boundary scan chain;
Wherein, N-B is upgraded the current potential of storage data input pin by data input pin to N-B+A boundary scan cell, N-B is pushed by described boundary scan chain to N-B+A the stored current potential of boundary scan cell, when N-B is pushed to respectively to N during to N+A boundary scan cell to N-B+A the stored current potential of boundary scan cell, be updated to data output pin to N+A the stored current potential of boundary scan cell by N is individual; And
Chip, described chip is fixed on circuit board, controlling pin for the A of described chip is electrically connected with described data output pin respectively, it is individual during to N+A boundary scan cell when N-B is pushed to N to N-B+A the stored current potential of boundary scan cell, N is updated to data output pin to N+A the stored current potential of boundary scan cell, described chip according to the current potential of data output pin so that described chip is carried out to burning.
2. the system of raising boundary scan technique as claimed in claim 1 to burning chip speed, it is characterized in that, after the current potential of N-B to N-B+A the corresponding described data input pin of boundary scan cell acquisition, N-B is pushed by described boundary scan chain to N-B+A the stored current potential of boundary scan cell, every through a time cycle, respectively N-B is pushed to next boundary scan cell forward to N-B+A the stored current potential of boundary scan cell, until it is individual to N+A boundary scan cell to push to N by N-B to N-B+A the stored current potential of boundary scan cell, as N-B, to N-B+A the stored current potential of boundary scan cell, to push to N individual during to N+A boundary scan cell, N is updated to data output pin to N+A the stored current potential of boundary scan cell, to complete the once control to data output pin.
3. the system of raising boundary scan technique as claimed in claim 1 to burning chip speed, it is characterized in that, as N-B, to N-B+A the stored current potential of boundary scan cell, to push to N individual during to N+A boundary scan cell, N is updated to after data output pin to N+A the stored current potential of boundary scan cell, select new or maintain original N-B to N-B+A boundary scan cell and capture the current potential of corresponding described data input pin, N-B is pushed by described boundary scan chain to N-B+A the stored current potential of boundary scan cell, individual to N+A boundary scan cell to push to N by N-B to N-B+A the stored current potential of boundary scan cell, as N-B, to N-B+A the stored current potential of boundary scan cell, to push to N individual during to N+A boundary scan cell, N is updated to data output pin to N+A the stored current potential of boundary scan cell, by the repeatedly control to data output pin, with analogy, go out the needed agreement of burning/recording chip.
4. the system of raising boundary scan technique as claimed in claim 1 to burning chip speed, it is characterized in that, the every propelling movement of described boundary scan chain is the current potential in described boundary scan cell once, need a time cycle, N-B pushes to N-B+A the stored current potential of boundary scan cell that N is individual needs B time cycle to N+A boundary scan cell.
5. the system of raising boundary scan technique as claimed in claim 1 to burning chip speed, is characterized in that, described current potential is 0, wherein 0 is expressed as electronegative potential, or current potential is 1, wherein 1 is expressed as noble potential.
6. improve the method for boundary scan technique to burning chip speed, it is characterized in that, comprise the following step:
Be fixed on circuit board and have in the chip of a plurality of pins, definition test data input pin, test data output pin, at least one data input pin and at least one data output pin;
In described chip, have a plurality of boundary scan cells, described boundary scan cell is electrically connected each other mutually, wherein:
N to N+A boundary scan cell and the electric connection of described data output pin, and N-B is to N-B+A boundary scan cell and the electric connection of described data input pin and in order to capture the current potential of described data input pin, wherein: N, A and B are that positive integer and N are greater than B and B is greater than A; And
Described test data input pin is electrically connected to the 1st boundary scan cell, and described test data output pin is electrically connected to last boundary scan cell, to be combined into boundary scan chain;
N-B is upgraded the current potential of storage data input pin by data input pin to N-B+A boundary scan cell, N-B is pushed by described boundary scan chain to N-B+A the stored current potential of boundary scan cell, it is individual during to N+A boundary scan cell when N-B is pushed to respectively to N to N-B+A the stored current potential of boundary scan cell, N is updated to data output pin to N+A the stored current potential of boundary scan cell, and N-B to N-B+A boundary scan cell can be again by described data input pin renewal storage current potential, and
A the control pin that is fixed on the chip on circuit board is electrically connected with described data output pin respectively, it is individual during to N+A boundary scan cell when N-B is pushed to N to N-B+A the stored current potential of boundary scan cell, N is updated to data output pin to N+A the stored current potential of boundary scan cell, described chip according to the current potential of data output pin so that described chip is carried out to burning.
7. the method for raising boundary scan technique as claimed in claim 6 to burning chip speed, it is characterized in that, after the current potential of N-B to N-B+A the corresponding described data input pin of boundary scan cell acquisition, N-B is pushed by described boundary scan chain to N-B+A the stored current potential of boundary scan cell, every through a time cycle, respectively N-B is pushed to next boundary scan cell forward to N-B+A the stored current potential of boundary scan cell, until it is individual to N+A boundary scan cell to push to N by N-B to N-B+A the stored current potential of boundary scan cell, as N-B, to N-B+A the stored current potential of boundary scan cell, to push to N individual during to N+A boundary scan cell, N is updated to data output pin to N+A the stored current potential of boundary scan cell, to complete the once control to data output pin.
8. the method for raising boundary scan technique as claimed in claim 6 to burning chip speed, it is characterized in that, as N-B, to N-B+A the stored current potential of boundary scan cell, to push to N individual during to N+A boundary scan cell, N is updated to after data output pin to N+A the stored current potential of boundary scan cell, select new or maintain original N-B to N-B+A boundary scan cell and capture the current potential of corresponding described data input pin, N-B is pushed by described boundary scan chain to N-B+A the stored current potential of boundary scan cell, individual to N+A boundary scan cell to push to N by N-B to N-B+A the stored current potential of boundary scan cell, as N-B, to N-B+A the stored current potential of boundary scan cell, to push to N individual during to N+A boundary scan cell, N is updated to data output pin to N+A the stored current potential of boundary scan cell, by the repeatedly control to data output pin, with analogy, go out the needed agreement of burning/recording chip.
9. the method for raising boundary scan technique as claimed in claim 6 to burning chip speed, it is characterized in that, in the step that current potential is pushed by described boundary scan chain by described test data input pin, the every propelling movement of described boundary scan chain is the current potential in described boundary scan cell once, need a time cycle, N-B pushes to N-B+A the stored current potential of boundary scan cell that N is individual needs B time cycle to N+A boundary scan cell.
10. the method for raising boundary scan technique as claimed in claim 6 to burning chip speed, it is characterized in that, N-B is to N-B+A boundary scan cell and the electric connection of described data input pin and in order to capture in the step of current potential of described data input pin, described current potential is 0, wherein 0 be expressed as electronegative potential, or current potential is 1, wherein 1 be expressed as noble potential.
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| CN104049203A (en) * | 2014-04-25 | 2014-09-17 | 三星半导体(中国)研究开发有限公司 | Pin with boundary scanning and testing function and integrated circuit with same |
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