CN109192240B - Boundary test circuit, memory and boundary test method - Google Patents
Boundary test circuit, memory and boundary test method Download PDFInfo
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- CN109192240B CN109192240B CN201810986092.3A CN201810986092A CN109192240B CN 109192240 B CN109192240 B CN 109192240B CN 201810986092 A CN201810986092 A CN 201810986092A CN 109192240 B CN109192240 B CN 109192240B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
Abstract
The boundary test circuit in the embodiment of the disclosure comprises a plurality of boundary register circuits, wherein one end of each boundary register circuit receives an initial test signal, and the other end of each boundary register circuit transmits the initial test signal to a next-stage boundary register circuit; the input ends of the state control circuits receive initial test signals stored in the boundary register circuit, the control ends of the state control circuits receive a state control signal, and the output ends of the state control circuits send real-time test signals to the integrated circuits to be tested; wherein the real-time test signal is a signal having the same phase or opposite phase to the initial test signal. The boundary test circuit provided by the embodiment of the disclosure can improve the test efficiency and the test flexibility.
Description
Technical Field
The disclosure relates to the field of electrical technology, and in particular relates to a boundary test circuit, a memory and a boundary test method.
Background
In modern electronic application systems, along with the advent of large-scale integrated circuits, the printed circuit board manufacturing process has been developed to be small, micro and thin, the pin count and pin density of components have been continuously improved, and the conventional "probe" test method using a multimeter and an oscilloscope to test chips has failed to meet the requirements.
In this context, boundary scan testing has evolved. Boundary scan testing is accomplished by attaching a boundary scan cell (Boundary Scan Cell, abbreviated BSC) to each I/O pin of the chip, and some additional test control logic, the BSC consisting essentially of registers. Each I/O pin of the chip has one BSC, and each BSC has two data channels: one is a Test Data channel, which includes a Test Data Input (TDI), a Test Data Output (TDO); the other is a normal data channel, which includes a normal data input (Normal Data Input, NDI for short) and a normal data output (normal data output, NDO for short).
In the conventional boundary test circuit, in a test mode, test data is transmitted according to the sequence of each clock cycle, and then data of each boundary scan cell is output to an integrated circuit to be tested through an I/O pin. Different test vectors need to be input to all boundary scan cells at each time and then output to an integrated circuit to be tested, and the problems of low test efficiency and poor flexibility are generally existed.
Therefore, a new boundary testing circuit and method are needed to overcome the defects in the related art.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The disclosure aims to provide a boundary test circuit, a memory and a boundary test method, so as to overcome the technical problems of low test efficiency and poor flexibility caused by the limitations and defects of the related art at least to a certain extent.
According to one aspect of the present disclosure, there is provided a boundary test circuit for testing an integrated circuit, characterized in that the boundary test circuit includes:
a plurality of boundary register circuits, one end of each boundary register circuit receives an initial test signal, and the other end of each boundary register circuit transmits the initial test signal to a next-stage boundary register circuit;
the input ends of the state control circuits receive initial test signals stored in the boundary register circuits, the control ends of the state control circuits receive a state control signal, and the output ends of the state control circuits send real-time test signals to the integrated circuits to be tested;
wherein the real-time test signal is a signal having the same phase or opposite phase to the initial test signal.
In an exemplary embodiment of the present disclosure, the state control signal is used to control phase switching of the real-time test signal.
In one exemplary embodiment of the present disclosure, the state control circuit includes:
an NOT element, wherein the input end of the NOT element receives an initial test signal stored in the boundary register circuit;
and one input end of the first data selector receives the initial test signal, the other input end of the first data selector is connected with the output end of the NOT element, the control end of the first data selector receives the state control signal, and the output end of the first data selector transmits the real-time test signal.
In one exemplary embodiment of the present disclosure, the state control circuit includes:
the input end of the first register receives an initial test signal stored in the boundary register circuit;
an or gate element, one input end of which is connected with the output end of the first register, and the other input end of which receives the state control signal;
an exclusive-or gate element, one input end of which is connected to the output end of the first register, and the other input end of which receives the state control signal;
and one input end of the second data selector is connected with the output end of the OR gate element, the other input end of the second data selector is connected with the output end of the exclusive OR gate element, the control end of the second data selector receives the state control signal, and the output end of the second data selector sends out the real-time test signal.
In an exemplary embodiment of the present disclosure, the state control circuit issues the real-time test signal under control of a clock signal.
In one exemplary embodiment of the present disclosure, the boundary register circuit includes:
a third data selector, one input end of the third data selector receives the initial test signal, and a control end of the third data selector receives a holding signal;
the input end of the second register is connected with the output end of the third data selector, and the output end of the second register outputs the initial test signal stored in the second register;
and one input end of the fourth data selector receives a normal input signal, the other input end of the fourth data selector is connected with the output end of the second register, the control end of the fourth data selector receives a scanning signal, the output end of the fourth data selector sends out a normal output signal, and the output end of the fourth data selector is connected with the other input end of the third data selector.
In one exemplary embodiment of the present disclosure, the boundary register circuit issues the initial test signal under control of a clock signal.
According to one aspect of the present disclosure, there is provided a memory comprising an integrated circuit, characterized in that it further comprises a boundary test circuit as described in any one of the above, said boundary test circuit being for testing said integrated circuit.
According to one aspect of the present disclosure, there is provided a boundary testing method for testing an integrated circuit, the method comprising:
the boundary register circuit receives an initial test signal and transmits the initial test signal to a next-stage boundary register circuit;
the state control circuit receives an initial test signal stored in the boundary register circuit and sends a real-time test signal to the integrated circuit to be tested according to the state control signal;
wherein the real-time test signal is a signal having the same phase or opposite phase to the initial test signal.
In an exemplary embodiment of the present disclosure, the state control signal is used to control phase switching of the real-time test signal.
In the boundary test circuit provided by the embodiment of the disclosure, the state control circuit is added on the basis of the boundary register circuits, so that the state switching control can be performed on the real-time test signals output by each boundary register circuit, and forward or reverse signals can be output to the integrated circuit to be tested according to different clock cycles under the triggering of the related control signals, thereby improving the test efficiency and the test flexibility of the boundary test circuit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.
Fig. 1 is a schematic diagram of a boundary test circuit composition in an exemplary manner of the present disclosure.
Fig. 2 is a schematic diagram of a portion of the composition of a boundary test circuit in an exemplary manner of the present disclosure.
Fig. 3 is a schematic diagram of a portion of a boundary test circuit in another exemplary manner of the present disclosure.
FIG. 4 is a flow chart of the boundary testing method steps in an exemplary manner of the present disclosure.
Reference numerals illustrate:
110-a boundary register circuit;
120-state control circuitry;
210-not gate element;
220-a first data selector;
230-a third data selector;
240-a second register;
250-a fourth data selector;
310-a first register;
320-or gate elements;
330-exclusive-or gate elements;
340-a second data selector.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.
Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and do not limit the number of their objects.
In an exemplary embodiment of the present disclosure, a boundary test circuit is first provided for testing an integrated circuit. The integrated circuit to be tested can be an independent chip to be tested after packaging, or can be a part of circuit units which are not packaged into chips. When the integrated circuit to be tested is an independent chip to be tested, the boundary test circuit can be connected with the I/O pin of the chip and perform data transmission. When the integrated circuit to be tested is a circuit unit which is not packaged yet, the boundary test circuit can be connected with a data channel of the circuit unit or a node for transmitting data and can transmit data. The present disclosure is not particularly limited in this regard.
Referring to fig. 1, the boundary test Circuit provided in the present exemplary embodiment may mainly include a plurality of boundary register circuits 110 and a plurality of state control circuits 120, wherein the boundary register circuits 110 (Wrapper Boundary Register, abbreviated as WBR) are mainly composed of registers, and the state control circuits 120 (Toggle circuits, abbreviated as TC) are used to implement state control of test signals.
In the present exemplary embodiment, each of the boundary register circuits 110 and the state control circuit 120 are sequentially arranged at intervals and serially connected in series step by step to form one complete test circuit. The number of the border register circuits 110 is the same as the number of the state control circuits 120, and each border register circuit 110 and each state control circuit 120 form a one-to-one connection relationship. In other exemplary embodiments, each of the boundary register circuits 110 and each of the state control circuits 120 may be connected in any other manner, and the number of boundary register circuits 110 and the number of state control circuits 120 may not be identical. The connection relationship and the number relationship between the boundary register circuit 110 and the state control circuit 120 may be arbitrarily set according to the characteristics of the integrated circuit to be tested and the actual test requirements, which are not particularly limited in the present exemplary embodiment.
One end of the boundary register circuit 110 is a Test signal Input end Test Input, and the other end of the boundary register circuit 110 is a Test signal Output end Test Output. The Test signal Input terminal Test Input is used for receiving an initial Test signal, and the Test signal Output terminal Test Output is used for transmitting the received initial Test signal to the next-stage boundary register circuit 110. The Test signal input terminal TestInput of the first-stage boundary register circuit 110 at the initial end of the boundary Test circuit may be connected to a Test instrument that emits an initial Test signal, and the Test signal Output terminal testoutput of the last-stage boundary register circuit 110 at the final end of the boundary Test circuit may be connected to an external Test instrument that emits an initial Test signal, thereby forming a completed Test loop. When the previous stage boundary register circuit 110 transmits the initial test signal to the next stage boundary register circuit 110, signal transmission may be directly completed through a data channel between the previous stage boundary register circuit 110 and the next stage boundary register circuit, or signal transmission may be indirectly completed after transferring through a state control circuit between the previous stage boundary register circuit and the next stage boundary register circuit, which is not particularly limited in this exemplary embodiment.
The input terminal of the state control circuit 120 receives the initial test signal stored in the corresponding boundary register circuit 110, the control terminal of the state control circuit 120 receives a state control signal Toggle, and the output terminal of the state control circuit 120 sends real-time test signals to the integrated circuit to be tested, i.e. Q0, Q1, Q2, Q3, etc. as shown in fig. 1. The real-time test signal may be the same as the initial test signal in phase or may be the opposite of the initial test signal in phase. The real-time test signal can be phase switched under the control of the received state control signal, so that two states with the same phase or opposite phases with the initial test signal are obtained. In addition, the implementation test signal sent by the state control circuit 120 may be phase switched under the control of a clock signal or any other trigger signal, which is not particularly limited in the present exemplary embodiment.
In the boundary test circuit provided in this exemplary embodiment, by adding the state control circuit on the basis of the boundary register circuits, the state switching control can be performed on the real-time test signal output by each boundary register circuit, and the forward or reverse signals can be output to the integrated circuit to be tested according to different clock cycles under the triggering of the related control signals, so that the test efficiency and the test flexibility of the boundary test circuit are improved.
The constituent elements and test principles of the boundary register circuit 110 and the state control circuit 120 are described below with reference to fig. 2 and 3.
Referring to fig. 2, in an exemplary embodiment of the present disclosure, the state control circuit 120 may mainly include: a not gate element 210 and a first data selector 220.
Wherein the input of the not-gate element 210 is used for receiving the initial test signal stored in the boundary register circuit 110.
The first data selector 220 includes two inputs, a control terminal and an output terminal, wherein the input terminal of one of the input terminal and the input terminal of the nand gate element 210 is connected to the same node, and is also used for receiving the initial test signal stored in the boundary register circuit 110. The other input is connected to the output of the nand gate element 210 for receiving the output signal of the nor gate element 210. The control terminal is configured to receive a state control signal Toggle, where the state control signal Toggle may control a strobe state of the first data selector 220. The output end is used for sending a real-time test signal which is gated and output based on the control of the state control signal Toggle received by the control end. When the state control signal Toggle is a first signal (e.g., a high signal), the first data selector 220 gates the input terminal located below, and the real-time test signal output by the output terminal is opposite to the initial test signal. When the state control signal Toggle is the second signal (e.g., a low signal), the first data selector 220 gates the input terminal located above, and the real-time test signal output by the output terminal is the same in phase as the initial test signal.
It should be noted that the component composition of the state control circuit 120 provided in the present exemplary embodiment is merely exemplary, and any other alternative circuit may be adopted under the condition of achieving the same effect.
With continued reference to FIG. 2, the boundary register circuit 110 may include, in principle: a third data selector 230, a second register 240, and a fourth data selector 250.
One input terminal of the third data selector 230 is used for receiving an initial test signal, which may be directly sent by an external test instrument (in the case that the current border register circuit 110 is a first-stage border register circuit located at the initial end of the border test circuit), may be directly sent to the first-stage border register circuit by a previous-stage border register circuit through a data transmission channel, or may be indirectly sent to the first-stage border register circuit through a state control circuit located in the middle of the first-stage border register circuit and the second-stage border register circuit. The control terminal of the third data selector 230 is configured to receive a Hold signal Hold, which is used to control the boundary register circuit 110 to enter or exit a Hold mode, i.e. to control the third data selector 230 to gate the input signals transmitted on the different input terminals.
An input terminal of the second register 240 is connected to an output terminal of the third data selector 230, and receives a signal output after the strobe control of the third data selector 230. The output of the second register 240 is used to output an initial test signal stored thereon, which may be output to the state control circuit 120 as shown in fig. 2, and may be directly transmitted to a next-stage boundary register circuit using a data transmission channel. In addition, the second register 240 may receive a clock signal CLK to externally transmit the initial test signal under the control of the clock signal CLK.
An input terminal of the fourth data selector 250 is for receiving a normal input signal normaliput. The other input terminal of the fourth data selector 250 is connected to the output terminal of the second register 240, and is configured to receive the signal output from the second register 240. The control terminal of the fourth data selector 250 is configured to receive a Scan signal Scan, which controls the boundary register circuit 110 to enter or exit a Scan mode, i.e. controls the fourth data selector 250 to gate the input signals transmitted on different input terminals. The Output terminal of the fourth data selector 250 sends a Normal Output signal Normal Output, and the Output terminal of the fourth data selector 250 is further connected to the other input terminal of the third data selector 230, so that the Normal Output signal Normal Output is transmitted to the third data selector 230 for gating.
It should be noted that the component composition of the boundary register circuit 110 provided in the present exemplary embodiment is merely exemplary, and any other alternative circuit may be adopted under the condition of achieving the same effect.
Referring to fig. 3, in another exemplary embodiment of the present disclosure, the state control circuit 120 may mainly include: a first register 310, an or gate element 320, an exclusive or gate element 330, and a second data selector 340.
The input terminal of the first register 310 is used for receiving the initial test signal stored in the boundary register circuit 110. In addition, the first register 310 may receive a clock signal CLK to externally transmit the initial test signal under the control of the clock signal CLK. In the present exemplary embodiment, the state control circuit 120 shares the same clock signal CLK with the boundary register circuit 110, as shown by a broken line portion connected between the clock signal CLK and the state control circuit 120 in fig. 1. In other embodiments, different clock signals may be set for the state control circuit 120 and the boundary register circuit 110, which is not particularly limited in this disclosure.
An input of the or-gate element 320 is connected to an output of the first register 310 for receiving the initial test signal stored in the first register 310. The other input terminal of the or gate element 320 is for receiving the state control signal Toggle.
An input of the exclusive or gate element 330 is coupled to an output of the first register 310 for receiving the initial test signal stored in the first register 310. The other input of the exclusive-or gate element 330 is for receiving the state control signal Toggle.
An input of the second data selector 340 is connected to an output of the or-gate element 320 for receiving the signal output by the or-gate element 320. The other input terminal of the second data selector 340 is connected to the output terminal of the exclusive-or gate element 330, and is configured to receive the signal output by the exclusive-or gate element 330. The control terminal of the second data selector 340 receives a state control signal Toggle, which may control the strobe state of the second data selector 340. The output terminal of the second data selector 340 is configured to transmit a real-time test signal, which is gated and output based on the control of the state control signal Toggle received by the control terminal. When the state control signal Toggle is the first signal (e.g., a high signal), the second data selector 340 gates the input terminal located below, and the real-time test signal output by the output terminal is opposite to the initial test signal. When the state control signal Toggle is the second signal (e.g., a low level signal), the second data selector 340 gates the input terminal located above, and the real-time test signal output by the output terminal is in the same phase as the initial test signal.
In the present exemplary embodiment, the component components of the boundary register circuit 110 have been described in detail in the previous embodiment, and will not be described here again.
It should be noted that the component composition of the state control circuit 120 provided in the present exemplary embodiment is merely exemplary, and any other alternative circuit may be adopted under the condition of achieving the same effect.
In another exemplary embodiment of the present disclosure, a memory is provided. The memory includes an integrated circuit and additionally includes a boundary test circuit as in any of the above exemplary embodiments for testing the integrated circuit packaged within the memory. The relevant components and test principles of the boundary test circuit are described in detail in the above exemplary embodiments, and are not repeated here.
In another exemplary implementation of the present disclosure, a boundary testing method based on the boundary testing circuit or memory in the above embodiments is provided for testing an integrated circuit.
Referring to fig. 4, the method may mainly include the steps of:
step S410, the boundary register circuit receives the initial test signal and transmits the initial test signal to the next boundary register circuit.
In this step, the boundary test circuit is set in the Scan mode by using the Scan signal Scan, and the input initial test signal is transmitted to each boundary register circuit WBR step by using the cooperative control of a plurality of signals. The boundary test circuit is then set to Hold mode using Hold signal Hold.
S420, the state control circuit receives an initial test signal stored in the boundary register circuit and sends a real-time test signal to the integrated circuit to be tested according to the state control signal; wherein the real-time test signal is a signal having the same phase or opposite phase to the initial test signal.
In this step, the state control circuit may send a real-time test signal to the integrated circuit to be tested, where the real-time test signal is a signal having the same phase or opposite phase to the initial test signal, by controlling the state control signal Toggle. In other words, the state control circuit may send either a forward signal or a reverse signal to the integrated circuit under test according to different clock cycles. For example, when the state control signal Toggle is a first signal (e.g., a high-level signal), a signal having the same phase as the initial test signal is sent to the integrated circuit to be tested; when the state control signal Toggle is a second signal (for example, a low-level signal), a signal with the opposite phase to the initial test signal is sent to the integrated circuit to be tested.
In the boundary test method provided in this exemplary embodiment, under the control of the state control signal, the state control circuit can perform state switching control on the real-time test signal output by each boundary register circuit, and under the trigger of the related control signal, the forward or reverse signal can be output to the integrated circuit to be tested according to different clock cycles, so that the test efficiency and the test flexibility of the boundary test circuit are improved.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (8)
1. A boundary test circuit for testing an integrated circuit, the boundary test circuit comprising:
a plurality of boundary register circuits, one end of each boundary register circuit receives an initial test signal, and the other end of each boundary register circuit transmits the initial test signal to a next-stage boundary register circuit;
the input ends of the state control circuits receive initial test signals stored in the boundary register circuits, the control ends of the state control circuits receive a state control signal, and the output ends of the state control circuits send real-time test signals to the integrated circuits to be tested; the state control signal is used for controlling the phase switching of the real-time test signal;
wherein the real-time test signal is a signal having the same phase or opposite phase to the initial test signal;
the state control circuit includes:
the input end of the first register receives an initial test signal stored in the boundary register circuit;
an or gate element, one input end of which is connected with the output end of the first register, and the other input end of which receives the state control signal;
an exclusive-or gate element, one input end of which is connected to the output end of the first register, and the other input end of which receives the state control signal;
and one input end of the second data selector is connected with the output end of the OR gate element, the other input end of the second data selector is connected with the output end of the exclusive OR gate element, the control end of the second data selector receives the state control signal, and the output end of the second data selector sends out the real-time test signal.
2. The boundary testing circuit of claim 1, wherein the state control circuit comprises:
an NOT element, wherein the input end of the NOT element receives an initial test signal stored in the boundary register circuit;
and one input end of the first data selector receives the initial test signal, the other input end of the first data selector is connected with the output end of the NOT element, the control end of the first data selector receives the state control signal, and the output end of the first data selector transmits the real-time test signal.
3. The boundary test circuit of claim 1, wherein the state control circuit issues the real-time test signal under control of a clock signal.
4. The boundary test circuit of claim 1, wherein the boundary register circuit comprises:
a third data selector, one input end of the third data selector receives the initial test signal, and a control end of the third data selector receives a holding signal;
the input end of the second register is connected with the output end of the third data selector, and the output end of the second register outputs the initial test signal stored in the second register;
and one input end of the fourth data selector receives a normal input signal, the other input end of the fourth data selector is connected with the output end of the second register, the control end of the fourth data selector receives a scanning signal, the output end of the fourth data selector sends out a normal output signal, and the output end of the fourth data selector is connected with the other input end of the third data selector.
5. The boundary test circuit of claim 4, wherein the boundary register circuit issues the initial test signal under control of a clock signal.
6. A memory comprising an integrated circuit, further comprising a boundary test circuit as claimed in any one of claims 1-5, the boundary test circuit being configured to test the integrated circuit.
7. A boundary testing method for testing an integrated circuit, the method comprising:
the boundary register circuit receives an initial test signal and transmits the initial test signal to a next-stage boundary register circuit;
the state control circuit receives an initial test signal stored in the boundary register circuit and sends a real-time test signal to the integrated circuit to be tested according to the state control signal;
wherein the real-time test signal is a signal having the same phase or opposite phase to the initial test signal;
the state control circuit includes:
the input end of the first register receives an initial test signal stored in the boundary register circuit;
an or gate element, one input end of which is connected with the output end of the first register, and the other input end of which receives the state control signal;
an exclusive-or gate element, one input end of which is connected to the output end of the first register, and the other input end of which receives the state control signal;
and one input end of the second data selector is connected with the output end of the OR gate element, the other input end of the second data selector is connected with the output end of the exclusive OR gate element, the control end of the second data selector receives the state control signal, and the output end of the second data selector sends out the real-time test signal.
8. The boundary testing method of claim 7, wherein the state control signal is used to control phase switching of the real-time test signal.
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| CN201810986092.3A CN109192240B (en) | 2018-08-28 | 2018-08-28 | Boundary test circuit, memory and boundary test method |
| PCT/CN2019/102123 WO2020043014A1 (en) | 2018-08-28 | 2019-08-23 | Boundary test circuit, memory and boundary test method |
| US17/165,831 US11340294B2 (en) | 2018-08-28 | 2021-02-02 | Boundary test circuit, memory and boundary test method |
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| JPH11281710A (en) * | 1998-03-30 | 1999-10-15 | Kawasaki Steel Corp | Boundary scan register |
| US6314539B1 (en) * | 1998-10-21 | 2001-11-06 | Xilinx, Inc. | Boundary-scan register cell with bypass circuit |
| US6539511B1 (en) * | 1999-05-06 | 2003-03-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit devices with test circuit |
| CN1489156A (en) * | 2002-08-30 | 2004-04-14 | 恩益禧电子股份有限公司 | Storage test circuit |
| CN101297208A (en) * | 2005-10-24 | 2008-10-29 | Nxp股份有限公司 | IC testing methods and apparatus |
| CN104049203A (en) * | 2014-04-25 | 2014-09-17 | 三星半导体(中国)研究开发有限公司 | Pin with boundary scanning and testing function and integrated circuit with same |
| CN208596549U (en) * | 2018-08-28 | 2019-03-12 | 长鑫存储技术有限公司 | Marginal testing circuit and memory |
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|---|---|
| CN109192240A (en) | 2019-01-11 |
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