CN104025454B - Semiconductor device and the driving method of high lateral circuit - Google Patents
Semiconductor device and the driving method of high lateral circuit Download PDFInfo
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- CN104025454B CN104025454B CN201280062352.9A CN201280062352A CN104025454B CN 104025454 B CN104025454 B CN 104025454B CN 201280062352 A CN201280062352 A CN 201280062352A CN 104025454 B CN104025454 B CN 104025454B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
- H03K17/0412—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
- H03K17/04123—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
- H03K17/08122—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/26—Modifications for temporary blocking after receipt of control pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
- H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/013—Modifications of generator to prevent operation by noise or interference
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/538—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a push-pull configuration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0063—High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0081—Power supply means, e.g. to the switch driver
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Power Conversion In General (AREA)
- Inverter Devices (AREA)
Abstract
In order to reduce for preventing the delay causing the signal in the circuit of misoperation to transmit because of the dV/dt noise of the hot side switch element (XD1) of composition half-bridge, in output for driving the set signal of hot side switch element, in the impulse generating unit (40) of reset signal, as either one period connected in the set signal or reset signal of the main bang that makes hot side switch element be conducting state or nonconducting state, connect from the signal being raised after certain time making the opposing party of this main bang, generate the state making set signal and reset signal both sides be turned on.
Description
Technical field
The present invention relates to the semiconductor device of half-bridge drive circuit etc..In particular, the present invention relates to that there is level shift
The semiconductor device of circuit and the driving method of high lateral circuit, this level shift circuit is using the electronegative potential of the system as primary side
The input signal of system sends the system as secondary side carrying out action using the current potential different from the action potential of primary side to
High potential system.
Background technology
In the past, in applying the half-bridge drive circuit etc. of supply voltage of high potential system power supply, in order to drive high potential
Side switch element, uses the level shift circuit that the control signal of electronegative potential system sends to high potential system.
Hereinafter, utilize Figure 10 that existing half-bridge drive circuit 90 is illustrated.
In Figure 10, between power supply potential E with earthing potential GND, totem pole (totem pole) is connected switches such as there being IGBT
Element XD1, XD2, constitute half-bridge circuit (output circuit 10).Additionally, for switch element XD1, XD2, inverse parallel connects two
Pole pipe DH, DL.And, using the junction point P3 to switch element XD1 and switch element XD2 to be connected has inductive load L1's
Structure.
In Figure 10, switch element XD1 be on the basis of the current potential with the junction point P3 of switch element XD2 current potential, at this base
The element of switch motion is carried out between the power supply potential E that quasi-current potential and power ps are provided.In explanation later, by this switch
Element XD1 is referred to as hot side switch element.
Additionally, switch element XD2 be on the basis of earthing potential current potential, this reference potential and junction point P3 current potential it
Between carry out the element of switch motion.In explanation later, this switch element XD2 is referred to as low potential side switch element.
Existing half-bridge drive circuit 90 includes having the output circuit 10 of switch element XD1, XD2, drive hot side
The high lateral circuit 99 of switch element XD1, the low-side circuitry 30 of driving low potential side switch element XD2.The present invention relates to high side electricity
Road, therefore omits the explanation of low-side circuitry.
High lateral circuit 99 includes pulse-generating circuit 40, this pulse-generating circuit 40 according to not shown from Figure 10, set
Input signal Hdrv of the electronegative potential system of the offers such as outside microcomputer is provided, produces for hot side switch element XD1
Carry out set signal (set) and the reset signal (reset) of the pulse type of on-off control.High lateral circuit 99 also includes: will be from arteries and veins
The set signal of punching generation circuit 40 output, reset signal are converted into the level shift circuit of the signal level of high potential system
24、25；Set signal after level shift, reset signal are carried out the latch cicuit 23 being made up of rest-set flip-flop etc. latched；
And utilize the signal after latching to generate the high-side driver 21 of signal of hot side switch element.
This latch cicuit 23 is setting in the case of input signal is positive logic as negative logic, output signal, the electricity inputted
It is that low level (effectively), level shift terminate reset signal when being high level (invalid) that translational shifting terminates set signal, output height
Level, by high-side driver 21, makes hot side switch element XD1 conducting form conducting state.Additionally, latch cicuit 23 exists
It is that to terminate reset signal be low level (effectively) for high level (invalid), level shift that the level shift inputted terminates set signal
Time, output low level, by high-side driver 21, make hot side switch element XD1 cut-off form nonconducting state.
If driving switch element XD1, XD2, power to inductive load L1, then the current potential Vs variation of junction point P3, sometimes
Noise can be produced over time because of voltage.In explanation later, this noise is referred to as dV/dt noise.
In the past, proposed there is the circuit tackling the misoperation that this dV/dt noise is caused.Such as, in patent documentation 1, in order to
Preventing the misoperation of latch cicuit, the prime at latch cicuit is provided with and prevents the latch misoperation of circuit from protecting as misoperation
22。
This misoperation prevents circuit to have the circuit structure shown in Figure 11, the set signal that terminates at level shift, reset
When signal is low level (effectively), the set signal of high level (invalid), reset signal are for latch cicuit 23 output.
Thus, the output of latch cicuit 23 is kept, accordingly, it is capable to prevent the set signal cause level shift because of dV/dt noise after,
Reset signal is misoperation during low level (effectively) transiently.
Prior art literature
Patent documentation
Patent documentation 1: No. 3429937 publications of Japanese Patent No.
Summary of the invention
Invent technical problem to be solved
But, switch element XD1 is generally being switched to conducting and by switch element from cut-off by the current potential Vs of junction point P3
XD2 rose when conducting is switched to cut-off, now produced dV/dt noise.Or, in addition, such as switch element XD1,
In the Dead Time that XD2 is turned off, current potential Vs the most also rises.This Dead Time is to run through electric current to prevent from flowing through and set
's.
That is, switch element XD2 turns on, and electric current is flowed into the output circuit 10 of the structural element as commutator from load L1
In, switch element XD2 becomes electric current and sucks element, in this case, if making switch element XD2 end, then in Dead Time,
The electric current flowed into from load L1 does not has path.Therefore, the parasitic capacitance of the circuit of the current potential Vs being connected with junction point P3 is because of this electricity
Flowing and be electrically charged, current potential Vs steeply rises.If current potential Vs rises to the diode DH conducting making to be connected in parallel with switch element XD1
Voltage, then this diode DH conducting, electric current flows to power ps from load L1 via diode DH, thus produces power consumption.It addition,
Make the forward voltage sum of the output voltage E that voltage is power ps and the diode DH that diode DH turns on.
Dead Time shown in Figure 12, the output time of set signal and output signal HO from high-side driver 21
Relation between time delay.
In Figure 12 (d), after the rising of the current potential Vs caused at Dead Time etc. terminates, set signal (set-3) becomes
In the case of high level, the latch misoperation defencive function latching misoperation protection circuit 22 is inoperative, in this case, puts
Position signal (set-3) becomes high level.Therefore, after output signal HO-3 of high-side driver 21 postpones ta intrinsic time delay
Rising, Simultaneous Switching element XD1 turns on.Rising preamble bit signal (set-1) at current potential Vs and become high electricity shown in Figure 12 (b)
In the case of Ping, it may have same ta time delay.
But, as shown in Figure 12 (c), the set signal (set-when causing current potential Vs to rise because of Dead Time etc.
2) moment becoming high level during becoming the rising of the situation of high level, i.e. current potential Vs with set signal (set-2) is overlapping
In the case of, produce than intrinsic interregnum tb long for ta time delay.
The dV/dt noise produced due to the rising with current potential Vs shown in Figure 12 (c), each level shift terminates set letter
Number (setdrn-2) and level shift terminate reset signal (resdrn) and all become low level, latch misoperation protection circuit 22
Defencive function works, and in this case, set signal (set-2) becomes high level.Therefore, the period of dV/dt noise is produced
Terminate.Then, before terminating during latching the protection act of misoperation protection circuit 22, set signal (set-2) does not transmits
To latch cicuit 23.Therefore, output signal HO-2 of high-side driver 21 is through longer interregnum (tb (> ta)) after on
Rise.
As it has been described above, in the case of during Dead Time, isoelectric level Vs rises, due to above-mentioned interregnum tb, switch unit
The turn-on action of part XD1 postpones.Therefore, the power consumption of the diode DH being connected in parallel with switch element XD1 becomes problem.Thus,
Expect to have the technology that switch element XD1 can be made as early as possible to turn on.
The present invention completes in view of the foregoing, its object is to provide a kind of semiconductor device and the driving of high lateral circuit
Method, can reduce misoperation for preventing the dV/dt noise of the hot side switch element because constituting half-bridge etc. from being caused
The delay that signal in circuit transmits.
Solve the technical scheme that technical problem is used
In order to achieve the above object, the semiconductor device of the present invention input signal of primary side positioning system is sent to
The secondary side positioning system that this primary side positioning system is different, it is characterised in that there is the hot side switch being connected in series first
Part and low potential side switch element and with described hot side switch element and the junction point of described low potential side switch element
Current potential on the basis of power subsystem, this hot side switch element action under the control signal of secondary side positioning system, should
The action under the control signal of primary side positioning system of low potential side switch element, this semiconductor device has: pulses generation list
Unit, this impulse generating unit, based on described input signal, produces and is used for making described hot side switch element be set to turn on shape
The set signal of the pulse type of state and for making described hot side switch element be set to the answering of pulse type of nonconducting state
Position signal；1st electrical level shift units, the 1st electrical level shift units secondary side positioning system hot side power supply potential with
Between the low potential side power supply potential of primary side positioning system, the 1st resistance and the 1st switch elements in series are connected, as described the
The signal of 1 switch element, it is provided that described set signal, from described 1st resistance and junction point that is the 1st of the 1st switch element
Junction point obtains the level shift of secondary side positioning system and terminates set signal；2nd electrical level shift units, the 2nd level shift
Unit is between the hot side power supply potential and the low potential side power supply potential of primary side positioning system of secondary side positioning system
2nd resistance and the 2nd switch elements in series are connected, as the signal of described 2nd switch element, it is provided that described reset is believed
Number, the level shift of secondary side positioning system is obtained from junction point that is the 2nd junction point of described 2nd resistance and the 2nd switch element
Terminate reset signal；Control signal output unit, this control signal output unit terminates set signal based on described level shift
And described level shift terminates reset signal, described hot side switch element is held in conducting state or non-conduction shape by output
The control signal of state；And protected location, this protected location is arranged at the prime of described control signal output unit, connects at the same time
Receive described level shift and terminate set signal and in the case of described level shift terminates reset signal, defeated to described control signal
Going out unit and provide the signal of regulation, the described control signal before making described control signal output unit continue to put out, this is partly led
Body device has: the 3rd switch element, and the 4th switch element is connected with described 1st resistor coupled in parallel；And the 4th switch element, should
4th switch element is connected with described 2nd resistor coupled in parallel；And logic gate, this logic gate is at secondary side positioning system
Middle action, inputs described 1st junction point, the current potential of the 2nd junction point, and described logic gate is in described 1st junction point, the 2nd company
In the case of the current potential of contact is all low than the input threshold voltage of described logic gate, make described 3rd switch element, the 4th
Switch element is conducting state.
In the present invention, by utilizing logic gate to monitor the output of electrical level shift units, thus detect protected location
The state worked.And, when protected location works, by making the 3rd, the 4th switching elements conductive, thus shorten protection merit
The action time of energy, high speed motion can be realized.
Additionally, the semiconductor device of the present invention is characterised by, including feedback unit, this feedback unit is at described high potential
When side switch element is in the conduction state, by drop-down for described 1st junction point, and by described 2nd junction point pull-up, at described high electricity
When side, position switch element is in nonconducting state, by described 1st junction point pull-up, and by drop-down for described 2nd junction point.
By arranging the feedback unit of the present invention, operating stably when dV/dt noise produces and high speed motion can be realized.
Additionally, the semiconductor device of the present invention is characterised by, impulse generating unit is as being used for making described high potential
Side switch element be set in the set signal of the main pulse of conducting state or nonconducting state or reset signal either one connect
Logical period, from this main pulse begin to ramp up make the signal of the opposing party connect after certain time, generation makes set signal
And the state that reset signal both sides are turned on.
According to the present invention, in spite of producing dV/dt noise, make defencive function be in the state worked all the time, make the
3, the 4th switch motion, it is thus possible to realize the high speed motion of semiconductor device.
Additionally, in the driving method of the high lateral circuit of the present invention, send the input signal of electronegative potential system to high potential
System, this high lateral circuit includes: pulse-generating circuit, and this pulse-generating circuit is according to the electronegative potential system control signal inputted
Rising edge, generate as the set signal of main differentiated pulse, according to the trailing edge of described electronegative potential system control signal, generate
Reset signal as main differentiated pulse；1st level shift circuit, the 1st level shift circuit will be entered by described set signal
N-channel type switch element and the resistance components in series of row switch connect and constitute；2nd level shift circuit, the 2nd level shift
The N-channel type switch element being carried out switching by described reset signal and resistance components in series are connected and constitute by circuit；Latch electricity
Road, this latch cicuit is for the output valve according to described 1st level shift circuit and the output of described 2nd level shift circuit
Value, keeps the state that high lateral circuit exports；Drive circuit, the output based on this latch cicuit of this drive circuit, generate and drive height
The signal of current potential side switch element；And latching misoperation protection circuit, this latch misoperation protection circuit makes described 1st level move
The specified states of the output valve of position circuit and the 2nd level shift circuit is not transferred to latch input, the driving side of this high lateral circuit
Method is characterised by, arranges using the output valve of described 1st level shift circuit and the 2nd level shift circuit as input
Logic or circuit, source terminal be connected with the hot side power supply potential of high lateral circuit and drain terminal and the 1st level shift electricity
The first P-channel type semiconductor element and the hot side power supply potential of source terminal and high lateral circuit that the output on road connects connect
Connect and the second P-channel type semiconductor element that the output of drain terminal and the 2nd level shift circuit connects, by a described P ditch
The gate terminal of channel type semiconductor element and the second P-channel type semiconductor element connects with the lead-out terminal of described logic or circuit
Connecing, when described pulse-generating circuit produces the main differentiated pulse of a side, the output of the opposing party produces from described main differentiated pulse
Play the secondary differentiated pulse of output after certain time, thus within certain period, make the set signal of this pulse-generating circuit and multiple
Position signal is high level.
In the present invention, at the differentiated pulse of the control signal produced for hot side switch element being carried out on-off control
Pulse-generating circuit in, be used in drive this hot side switch element differentiated pulse be main pulse.From an output
Terminal exports this main differentiated pulse and rises after certain time, from the secondary differentiated pulse of another lead-out terminal output.This pair differential arteries and veins
Punching does not directly carry out on-off control to hot side switch element.Set signal after i.e., secondary differentiated pulse makes level shift,
Reset signal is restored ahead of time.Thus, the high speed motion of hot side switch element can be realized.
By adjusting the output time of this pair differentiated pulse, thus the output signal of described logic or circuit is utilized to control
Described first P-channel type semiconductor element and the grid voltage of the second P-channel type semiconductor element, adjust described pulses generation electricity
The differentiated pulse output on road is the pulse output time of high level, and by described first P-channel type semiconductor element and the 2nd P
The grid voltage of channel-type semiconductor element is adjusted so that exceeding described first P-channel type semiconductor element and the 2nd P
The action threshold voltage of channel-type semiconductor element.
Invention effect
As it has been described above, according to the present invention, owing to the hot side switch constituting the semiconductor device of half-bridge etc. can be suppressed first
The delay of the turn-on action during Dead Time of part etc., accordingly, it is capable to reduce and diode that above-mentioned switch element is connected in parallel
Power consumption.
Accompanying drawing explanation
Fig. 1 is the circuit of the semiconductor device (half-bridge drive circuit) using high lateral circuit of embodiments of the present invention 1
Structure chart.
Fig. 2 is the sequential chart of the action of the high lateral circuit for explanatory diagram 1.
Fig. 3 is the circuit of the semiconductor device (half-bridge drive circuit) using high lateral circuit of embodiments of the present invention 2
Structure chart.
Fig. 4 is the circuit structure diagram of the pulse-generating circuit 40 of embodiments of the present invention 3.
Fig. 5 is the sequential chart of the action of the pulse-generating circuit for explanatory diagram 4.
Fig. 6 is the set signal that terminates of the level shift in the method for generating pulse of embodiments of the present invention 3 and reset
Set signal that level shift in the explanatory diagram (Fig. 6 (a)) of signal and conventional method for generating pulse terminates and reset signal
Explanatory diagram (Fig. 6 (b)).
Fig. 7 is the figure of the simulation result of each main signal during pulse-generating circuit action representing and making Fig. 4.(interpulse
It is divided into the situation of 50ns)
Fig. 8 is the figure of the simulation result of each main signal during pulse-generating circuit action representing and making Fig. 4.(interpulse
It is divided into the situation of 30ns)
Fig. 9 is the figure of the simulation result of each main signal during pulse-generating circuit action representing and making Fig. 4.(interpulse
It is divided into the situation of 10ns)
Figure 10 is the circuit structure diagram of conventional half-bridge drive circuit 90.
The misoperation that Figure 11 is conventional prevents the circuit diagram of circuit.
Figure 12 is the sequential chart of the action of the high lateral circuit for Figure 10 is described.
Detailed description of the invention
Hereinafter, referring to the drawings the semiconductor device of embodiments of the present invention and the driving method of high lateral circuit are said
Bright.It addition, embodiment described below is the preferred embodiment of the driving method of the semiconductor device of the present invention and high lateral circuit,
Add preferred various restriction the most technically.As long as no being particularly limited to the record of the present invention, the technology model of the present invention
Enclose and be just not limited to these modes.Additionally, the structural element in embodiment shown below can be wanted with suitable existing structure
Element etc. is replaced, and can have the various deformation comprising the combination with other existing structure key elements.Therefore, shown below
The record of embodiment do not limit the content of the invention described in claims.
(embodiment 1)
Figure 1 illustrates the circuit structure of half-bridge drive circuit, as an embodiment of the semiconductor device of the present invention.
Half-bridge drive circuit 1 is made up of high lateral circuit 20 and low-side circuitry 30.But, the present invention relates to high lateral circuit 20, with downside electricity
Road 30 relation is little, therefore, omits the explanation of low-side circuitry 30.
In Fig. 1, output circuit 10 includes constituting switch element XD1, XD2 that the totem pole of half-bridge connects, and executes its two ends
The output voltage E of high voltage power ps.For the switch element XD1 of hot side (high side), use such as N-channel or P ditch
The IGBT etc. of the MOS transistor in road, p-type or N-type.For the switch element XD2 of low potential side (downside), use such as N-channel
MOS transistor, the IGBT etc. of N-type.Herein, as switch element XD1, XD2, it is suitable for the IGBT of N-channel MOS transistor or N-type.
For each switch element XD1, XD2, inverse parallel connects respectively diode DH, DL.This diode DH, DL are rectification diodes
Or parasitic diode.
High lateral circuit 20 includes: pulse-generating circuit 40, and it is based on the instruction Hdrv from microprocessor (not shown), defeated
Set signal (set) and the reset making hot side switch element XD1 end of the hot side switch element XD1 that sends as an envoy to conducting are believed
Number (reset)；Level shift circuit 24,25, its signal i.e. set of electronegative potential system that will export from pulse-generating circuit 40
Signal (set), the level of reset signal (reset) send high potential system to；High-side driver 21, it receives this level shift
The output of circuit 24,25 also carries out on-off control to switch element XD1；And power ps 1.
Level shift circuit 24,25 includes: Continuity signal side level shift circuit 24, it is by resistance LSR1a and N-channel
MOS transistor HVN1 is constituted, and is carried out to the signal of high potential system by the set signal (set) exported from pulse-generating circuit 40
Level conversion；And pick-off signal side level shift circuit 25, it is made up of resistance LSR2a and N-channel MOS transistor HVN2,
The reset signal (reset) exported from pulse-generating circuit 40 is carried out level conversion to the signal of high potential system.
Additionally, the input terminal latching misoperation protection circuit 22 is connected to Continuity signal side level shift circuit 24
Be connected in series a little be the 1st junction point P1.Another input terminal is connected to the series connection of pick-off signal side level shift circuit 25 even
Contact that is the 2nd junction point P2.
Output signal SH of latch cicuit 23 as the signal after level shift and is input to high side and drives by high lateral circuit 20
Dynamic device 21.The lead-out terminal of high-side driver 21 is connected to the gate terminal of hot side switch element XD1.
Additionally, latch misoperation protection circuit 22, latch cicuit 23, high-side driver 21 and the low potential side of power ps 1
It is a little the 3rd junction point P3 that power supply terminal is connected to being connected in series of switch element XD1, XD2.Latch misoperation protection circuit 22,
Latch cicuit 23 and high-side driver 21 constitute control signal output unit 28.Each circuit 21～23 is applied the defeated of power ps 1
Go out voltage E1.
The Continuity signal side level shift circuit 24 that is made up of resistance LSR1a and transistor HVN1 and by resistance LSR2a and
The pick-off signal side level shift circuit 25 that transistor HVN2 is constituted is connected to the hot side power supply potential E1 of power ps 1
And between ground connection (GND) current potential.
Input the gate terminal of N-channel MOS transistor HVN1, HVN2 respectively to level shift circuit 24,25 is defeated
Enter signal i.e. set signal (set), reset signal (reset).This set signal (set) and reset signal (reset) are low electricity
The signal of position system.
Set signal (set) be instruction hot side switch element XD1 conducting during start or end during end
The signal in moment.Additionally, reset signal (reset) be instruction this switch element XD1 cut-off during start or turn on during knot
The signal in the moment of bundle.
The anode of diode D1, D2 is commonly connected to the 3rd junction point P3, negative electrode be connected respectively to the 1st junction point P1, the 2nd
Junction point P2.This diode D1, D2 carry out clamper so that terminate set from the level shift of the 1st, the 2nd junction point P1, P2 output
Signal (setdrn) and level shift terminate reset signal (resdrn) not at below the current potential Vs of the 3rd junction point P3.That is, two
Pole pipe D1, D2 are to arrange based on avoiding latch misoperation protection circuit 22 is inputted the purpose of overvoltage.
Low-side circuitry 30 includes that low potential side switchs negative electrode XD2 carries out the low side driver 31 of on-off control and to this
Low side driver 31 applies the power ps 2 of supply voltage E2.Input signal is amplified by low side driver 31, and is input to out
Close the gate terminal of element XD2.Switch element XD2 turns on when being high level to the input signal of low side driver 31, is giving
End when the input signal of low side driver 31 is low level.
Under the defencive function non-operational state latching misoperation protection circuit 22, terminating set letter from level shift
Number (setdrn) becomes the low level moment and terminates reset signal (resdrn) becomes the low level moment to level shift
Period in, latch cicuit 23 latches high level.From the signal HO of high-side driver 21 output in utilizing during this latch, make
Switch element XD1 turns on.
Switch element XD1, XD2 complementally turn on outside the Dead Time both ended, end.That is, switch element
XD1, XD2 are when side's conducting, and the opposing party ends.Additionally, the current potential Vs of the 3rd junction point P3 base when switch element XD2 turns on
This is earthing potential.Thus, current potential Vs is substantially equal to the output voltage E of high-voltage power supply PS when switch element XD1 turns on.
Inductive load L1 is connected between the 3rd junction point P3 and ground connection, by the electric power institute exported from this junction point P3
Drive.
Latch misoperation protection circuit 22 and be suitable for prior art.Herein, utilize Figure 11 to latching misoperation protection circuit 22
Structure illustrate.
In the latch misoperation protection circuit 22 of Figure 11, input has level shift to terminate the one of set signal (setdrn)
Individual input terminal is connected to an input terminal of NOR circuit G1, and is connected to the one of NAND circuit G3 via NOT circuit G2
Individual input terminal.Additionally, another input terminal that input has level shift to terminate reset signal (resdrn) is connected to NOR circuit
Another input terminal of G1, and an input terminal of NAND circuit G5 it is connected to via NOT circuit G4.Additionally, NOR circuit
The lead-out terminal of G1 is connected to another input terminal and another input of NAND circuit G5 of NAND circuit G3 via NOT circuit G6
Terminal.
Returning Fig. 1, the high lateral circuit 20 of present embodiment has the high lateral circuit 99 to the conventional example shown in Figure 10 and chases after
Add P channel MOS transistor PM1a, PM2a and as two input logics of logic gates or the structure of circuit OR1.
Transistor PM1a, PM2a are connected in parallel with resistance LSR1a, LSR2a respectively.Logic or an input of circuit OR1
Terminal is connected to the above-mentioned 1st and is connected to P1, and another input terminal is connected to above-mentioned 2nd junction point P2.Additionally, logic or circuit
The lead-out terminal of OR1 is connected to the gate terminal of MOS transistor PM1a, PM2a.Additionally, the input threshold of this logic or circuit OR1
Threshold voltage is set as latching below the threshold voltage of misoperation protection circuit 22.
Hereinafter, with reference to Fig. 2 corresponding with Figure 12, the action to the half-bridge drive circuit of present embodiment illustrates.
As in figure 2 it is shown, when set signal (set-1) becomes high level, N-channel MOS transistor HVN1 turns on.Then,
Set signal (setdrn-1) is terminated from the level shift of junction point P1 output low level.In the case, latch malfunction to go bail for
The latch misoperation defencive function of protection circuit 22 is inoperative.Therefore, latch cicuit 23 carries out latching action.As a result of which it is, it is high
Output signal HO-1 of side driver 21 postpones intrinsic time delay and rises after ta, the switch element XD1 conducting of hot side.
If switch element XD1 turns on, then the dV/dt noise produced due to the rising with current potential Vs, level shift terminates
The current potential of reset signal (resdrn) declines.Then, terminate at level shift the current potential of reset signal (resdrn) in logic or
Time below the threshold voltage of circuit OR1, the level shift as another input to logic or circuit OR1 terminates set signal
(setdrn-1) from the most just becoming low level, therefore, output signal OR_OUT of this logic or circuit OR1 becomes low level.
Thus, MOS transistor PM1a, PM2a turn on, and the impedance between the source-leakage of these MOS transistors PM1a, PM2a declines.This impedance
Decline compensate for level shift and terminate set signal (setdrn-1) and level shift terminates the electricity of reset signal (resdrn)
Drops.Therefore, this level shift terminates set signal (setdrn-1) and level shift terminates reset signal (resdrn)
Current potential rises.It addition, Fig. 2 is expressed as follows situation: the conducting resistance of N-channel MOS transistor HVN1, HVN2 is set to the least
In the conducting resistance of MOS transistor PM1a, PM2a, when utilizing set signal (set-1) to make N-channel MOS transistor HVN1 turn on
Level shift terminate set signal (setdrn-1) and do not vibrate, and keep low level.
Set signal (setdrn-1) is terminated and level shift terminates the current potential of reset signal (resdrn) at level shift
Rising, when exceeding the threshold voltage of logic or circuit OR1, the lead-out terminal of this logic or circuit OR1 becomes high level.Its result
It is that the grid cut-off of MOS transistor PM1a, PM2a, the impedance between their source and drain increases.Therefore, level shift terminates set
Signal (setdrn-1) and level shift terminate the current potential of reset signal (resdrn) and decline.
In the period producing dV/dt noise, repeat above-mentioned action, therefore, logic or the output signal of circuit OR1 and
Level shift terminates set signal (setdrn-1) and level shift terminates reset signal (resdrn) and becomes the waveform of vibration.Separately
Outward, as it has been described above, when N-channel MOS transistor HVN1 turns on, level shift terminates the vibration of set signal (setdrn-1) and stops
Only.
It follows that the set signal (set-2) when causing current potential Vs to rise because of above-mentioned Dead Time etc. is become
Become moment of high level overlapping situation during the rising of the situation of high level, i.e. current potential Vs to enter with set signal (set-2)
Row explanation.Herein, before set signal (set-2) becomes high level, 2 level shift end signals (setdrn-1,
Resdrn) it is low level or is high level, therefore, latch cicuit 23 being not changed in.That is, if being low level, then by
Latching misoperation protection circuit 22 and stop the input to latch cicuit 23, if being high level, then the input of latch cicuit 23 is
Negative logic, therefore, latch cicuit 23 does not changes.
In the case, when producing dV/dt noise in the rising along with above-mentioned current potential Vs, i.e. at logic or circuit OR1
Output signal and 2 level shift end signals (setdrn-2, resdrn) waveform of presenting vibration state under, set
Signal (set-2) becomes high level.When set signal (set-2) becomes high level, the source ground constituting set side amplifies
The N-channel MOS transistor HVN1 conducting of circuit.Then, level shift terminates set signal (setdrn-2) and becomes low level.Cause
This, when level shift terminate reset signal (resdrn) become high level because of vibration when, even if produce dV/dt noise
In the case of, utilize latch misoperation protection circuit 22 also cannot stop the input to latch cicuit 23.Thus, set can be believed
Number (set-2) sends latch cicuit 23 to.
It addition, set signal (set-3) becomes high electricity after the rising of the current potential Vs caused at Dead Time etc. terminates
In the case of Ping, the latch misoperation defencive function latching misoperation protection circuit 22 is inoperative.Therefore, high-side driver 21
Output signal HO-3 postpone above-mentioned intrinsic time delay and rise after ta, Simultaneous Switching element XD1 turns on.
In above-mentioned embodiment, aaset bit signal becomes the situation of high level and is illustrated, but in reset signal
(reset), when becoming high level, this reset signal (reset) is sent to latch cicuit 23 too.
Above, according to present embodiment, from output signal HO-2 shown in Fig. 2 and output signal HO-2 shown in Figure 12
Relatively it is recognised that when current potential Vs rises, set signal (set-2) becomes under high level state, output letter can be suppressed
The delay of number HO-2.Thus, the delay of the turn-on action of switch element XD1 can be suppressed, reduce connect in parallel with this switch element XD1
The power consumption of the diode DH connect.
Additionally, in the present embodiment, as latching misoperation protection circuit 22, the electricity of the structure shown in Figure 11 is used
Road, as combined latch cicuit 23, can use set-reset-flip-flop circuit.
Additionally, as long as logic or circuit OR1 realize the circuit of above-mentioned action, however it is not limited to simple logic or electricity
Road (OR gate circuit).This is the most also same.
(embodiment 2)
It follows that explanation embodiments of the present invention 2.
The circuit structure of the half-bridge drive circuit comprising high lateral circuit of present embodiment shown in Fig. 3.Different from Fig. 1
Point is to have added P channel MOS transistor PM1, PM2, resistance LSR1b, LSR2b and NOT circuit 26.In addition same with Fig. 1
Sample, therefore, marks same label to same key element and omits the description.
MOS transistor PM1, PM2 are connected in parallel with resistance LSR1a, LSR2a respectively, and their gate terminal connects respectively
Receive junction point P2, P1.
One end of resistance LSR1b is connected to junction point P1, and the other end is connected to the lead-out terminal of NOT circuit 26.Additionally, it is electric
One end of resistance LSR2b is connected to junction point P2, and the other end is connected to the lead-out terminal of latch cicuit 23.The output of latch cicuit 23
Terminal also connects with the input terminal being connected NOT circuit 26.
Above-mentioned resistance LSR1b, LSR2b, NOT circuit 26, transistor PM1, PM2 constitute feedback circuit.It addition, resistance
LSR1a and resistance LSR2a has identical resistance value, and resistance LSR1b and resistance LSR2b has identical resistance value.
It follows that resistance LSR1b, LSR2b are illustrated.
In Fig. 3, the current potential of the terminal of NOT circuit 26 side of resistance LSR1b, LSR2b, according to the output of latch cicuit 23
The logic level of signal, if a side is high level, then the opposing party is low level.
Herein, if latch cicuit 23 be output into low level.Now, NOT circuit 26 be output into high level.So
After, terminate the current potential of set signal (setdrn) and the electricity on the basis of current potential Vs from the level shift of the 1st junction point P1 output
E1 is equal for pressure, becomes high level.On the other hand, the level shift from the 2nd junction point P2 output terminates reset signal (resdrn)
Current potential become, by resistance LSR2a, LSR2b, voltage E1 carried out the value (=E1 LSR2b/ (LSR2a+LSR2b)) after dividing potential drop.
Now, it is set such that this partial pressure value becomes the high level latching misoperation protection circuit 22.That is, predetermined electric
The intrinsic standoff ratio of resistance LSR2a, LSR2b so that the voltage after voltage E1 being carried out dividing potential drop by resistance LSR2a, LSR2b is higher than latching by mistake
The threshold voltage of action protection circuit 22.
Be output as high level at latch cicuit 23, to be output as low level situation be also same to NOT circuit 26.
That is, the intrinsic standoff ratio of resistance LSR1a, LSR1b is predefined so that after voltage E1 being carried out dividing potential drop by resistance LSR1a, LSR1b
Voltage becomes the high level latching misoperation protection circuit 22.
By the intrinsic standoff ratio of dividing potential drop when resistance LSR2a, LSR2b of the most predetermined resistance LSR1a, LSR1b, thus
Only the level shift to high lateral circuit 20 terminates set signal (setdrn) or level shift terminates in reset signal (resdrn)
The input signal of side's input low level time dV/dt noise tolerance improve, stable action can be realized.
It follows that to the feedback being made up of resistance LSR1b, LSR2b, NOT circuit 26 and P channel MOS transistor PM1, PM2
Circuit illustrates.
If the resistance value of resistance LSR1a, LSR2a is equal, the resistance value of resistance LSR1b, LSR2b is equal, and P-channel MOS
The conducting resistance of transistor PM1, PM2 is sufficiently small.Then, its grid and the junction point of the high level in junction point P1, P2 are (at it
After explanation in, this junction point is called " H junction point ") gate-source voltage of P channel MOS transistor that connects is zero.Additionally, its
Grid connects with the low level junction point (in explanation later, this junction point is called " L junction point ") in junction point P1, P2
The gate-source voltage of P channel MOS transistor be E1 Ra/ (Ra+Rb).It addition, resistance Ra is equivalent to resistance LSR1a or resistance
LSR2a, resistance Rb are equivalent to resistance LSR1b or resistance LSR2b.
The value of above-mentioned gate-source voltage E1 Ra/ (Ra+Rb) is set as than P channel MOS transistor PM1, the threshold value electricity of PM2
Pressure wants slightly larger magnitude of voltage.Thus, the MOS transistor that grid is connected with L junction point become have limited conducting resistance Ron,
The structure that this conducting resistance Ron is connected in parallel with resistance LSR1a or resistance LSR2a.Such as, if setting E1=15V, P-channel MOS is brilliant
The threshold voltage of body pipe PM1, PM2 is 2.5V, LSR1a=LSR2a=Ra=10k Ω, LSR1b=R5=Rb=45k Ω, then go up
State gate-source voltage 0.2V bigger than threshold voltage, for E1 Ra/ (Ra+Rb)=2.7V.
So, in the present embodiment, above-mentioned conducting resistance Ron is not zero, and is limited value.Therefore, in this enforcement
In mode, though N-channel MOS transistor HVN1 or the HVN2 conducting being connected with H junction point, it is possible to prevent current potential E1 and ground connection
Perforation electric current is had to flow through between current potential.
Additionally, there is parasitic capacitance Cds1, Cds2 between the source and drain of N-channel MOS transistor HVN1, HVN2.Therefore, above-mentioned
Turning circuit Ron causes the time constant for H junction point different from the time constant for L junction point, makes the former time
Constant is less than the time constant of the latter.
As a result of which it is, in the case of causing the potential change of H junction point and L junction point because of dV/dt noise, H connects
The current potential of point to change as rapidly than the current potential of L junction point.Thus, when both current potentials rise, the current potential of H junction point reaches lock
The current potential of time and the L junction point of depositing the input threshold voltage of misoperation protection circuit 22 reach same threshold voltage time it
Between produce difference.As a result of which it is, latch cicuit 23 set or reset to keep original value because of this time difference.
Therefore, according to present embodiment, the misoperation that dV/dt noise causes can be more reliably prevented from.
As it has been described above, the feedback being made up of resistance LSR1b, LSR2b, NOT circuit 26 and P channel MOS transistor PM1, PM2
A side in 1st junction point P1 and the 2nd junction point P2, according to the output signal of latch cicuit 23, is pulled upward to 2 side electricity by circuit
The hot side power supply potential of position system, and the opposing party is pulled down to the low potential side power supply potential of 2 side positioning system, thus
It is more reliably prevented from the misoperation that dV/dt noise causes.
It addition, in the high lateral circuit of present embodiment, also as the high lateral circuit shown in Fig. 1, suppress hot side
The delay of the turn-on action of switch element XD1, can obtain the effect reducing power consumption.
(embodiment 3)
It follows that explanation embodiments of the present invention 3.
The half-bridge drive circuit 1 of present embodiment is in the high lateral circuit 0 shown in Fig. 1 and Fig. 3 so that from pulses generation electricity
Road 40 exports the signal from the most different output waveforms.
Fig. 4 is the circuit structure diagram of the pulse-generating circuit 40 of present embodiment.In Fig. 4, from outside input signal
Hdrv is input to the D input terminal of the D flip-flop 50 of pulse-generating circuit 40.System clock CLK is input to D flip-flop 50
CLK terminal.
Additionally, Q output of D flip-flop 50 is connected to the inversing input terminal of AND circuit 51, and it is connected to AND
The non-inverting input terminal of circuit 52.Input signal Hdrv is connected to non-inverting input terminal and the AND circuit 52 of AND circuit 51
Inversing input terminal.It addition, inversing input terminal can come real by inserting NOT circuit in the prime of non-inverting input terminal
Existing.
The lead-out terminal of AND circuit 51 is connected to the S input terminal of rest-set flip-flop 56.The lead-out terminal of AND circuit 52 is even
Receive R input of rest-set flip-flop 56.
The output Q of rest-set flip-flop 56 is connected to the selection terminal S of multiplexer circuit (MUX) 54,55.This multiplexing
Device circuit 54,55 utilizes and selects signal (Select), selects terminal defeated of one party in input terminal 0 or input terminal 1
Enter signal and export.
AND circuit 51, the output of AND circuit 52 are connected respectively to the input terminal of OR circuit 53.The output of OR circuit 53
Terminal is connected to the clearing terminal of counter circuit (CNT) 57.Additionally, when the clock input terminal of counter circuit 57 and system
Clock CLK connects.This lead-out terminal (in explanation later, is referred to as " the 1st output by one lead-out terminal of counter circuit 57
Terminal ") it is connected to the input terminal 1 of multiplexer circuit 54 and the input terminal 0 of multiplexer circuit 55.Enumerator electricity
It is multiple that another lead-out terminal (in explanation later, this lead-out terminal being referred to as " the 2nd lead-out terminal ") on road 57 is connected to multichannel
With input terminal 0 and the input terminal 1 of multiplexer circuit 55 of device circuit 54.
It addition, in the present embodiment, the 1st lead-out terminal of counter circuit 57 is because of the clock signal after reset signal
It is continuously turned on state, the signal that output disconnects after " 8 " till " 1 " starts to count up to " 7 " successively.Counter circuit
2nd lead-out terminal of 57 is continuously turned off state from " 1 " to " 5 ", becomes connection between " 6 " " 7 ", and output becomes the most again
The signal disconnected.
That is, the 2nd lead-out terminal of counter circuit 57 for become after postponing 5 clocks than the 1st lead-out terminal connection and
1st lead-out terminal exports the signal of disconnection simultaneously.This time delay, adjustment became the following time: this time makes i.e. to be allowed to
Afterwards by connecting data side level shift circuit 24, cut-off signal side level shift circuit 25, latching misoperation protection circuit 22,
The output signal from the 1st lead-out terminal is the most reliably made (this output signal, in explanation later, to be referred to as " the 1st output letter
Number ") earlier it is input to latch cicuit 23.Additionally, from the 2nd lead-out terminal output signal (in explanation later, should
Output signal be referred to as " the 2nd output signal ") become connection time adjust become P channel MOS transistor PM1a, PM2a reliably
The time of conducting.
The moment of disconnection is become about the 2nd output signal, as the circuit diagram of Fig. 4, as the signal Tong Bu with clock,
Become disconnection the most no problem with the 1st output signal simultaneously.Or, P-channel MOS can be substantially ensured that if pulse width can be taken into
The ON time of transistor PM1a, PM2a, then can also earlier become disconnection than the 1st output signal.In a word, it is important that
Carry out level shift, by latching misoperation protection circuit and being input to the signal of latch cicuit in which kind of moment on-off.
Thus, even if the moment of the 1st, the 2nd output signal be slightly offset, it is possible to realize above-mentioned counter circuit 57.
Systematic reset signal ZRST is connected to each trigger 50,56 and the reseting terminal of counter circuit 57.
There is shown in Fig. 5 the action waveforms of the pulse-generating circuit 40 of said structure.
The signal PreHdrv postponing 1 clock than input signal Hdrv is exported by D flip-flop 50.Pass through AND circuit
51,52 input signal Hdrv and the difference of signal PreHdrv are obtained, when rising, the decline of input signal Hdrv, respectively
Output rise (rising) signal of 1 clock, fall (decline) signal, become the reset signal of counter circuit 57.
Additionally, when input signal Hdrv rises, utilize rise signal by rest-set flip-flop 56 set, its output Q becomes high
Level.When input signal Hdrv declines, utilizing rise signal to be resetted by rest-set flip-flop 56, its output Q becomes low level.
In multiplexer circuit 54,55, the signal selected when rising, the decline of input signal Hdrv is different.
Therefore, when rising, export the 1st output signal as set signal from multiplexer circuit 54, from multiplexer electricity
Road 55 exports the 2nd output signal as reset signal.On the other hand, when the decline of input signal Hdrv, multiple from multichannel
Export the 2nd output signal as set signal with device circuit 54, export the 1st output signal conduct from multiplexer circuit 55
Reset signal.
It follows that utilize Fig. 6, by the waveform of present embodiment give latch misoperation protection circuit 22 input signal,
It is compared to explanation with the input signal latching misoperation protection circuit 22 of giving of the waveform of a upper embodiment.
From the signal of pulse-generating circuit 40 output as Fig. 6 (a), when set, reset signal prolongs than set signal
Rise after stipulated time late, become disconnection the most simultaneously.During reset, first reset signal rises, set after delay stipulated time
Signal rises, and becomes disconnection the most simultaneously.
More specifically, during set, first set signal rises, and now reset signal is also in off-state.As electricity
The setdrn signal of the signal after translational shifting, resdrn signal (negative logic) respectively become low level, high level, latch cicuit 23
Becoming SM set mode, its output becomes connection.Thus, the output of high-side driver 21 also becomes connection, and hot side switch is first
Part XD1 becomes conducting state.Now, latch misoperation protection circuit 22 not work.
Afterwards, when delay stipulated time (being 5 clocks in the example of fig. 4) reset signal afterwards rises, for latching
Misoperation protection circuit 22 input as level shift after the setdrn signal of signal, resdrn signal (negative logic), they
It is low level (effectively).Therefore, defencive function works, and latches the output of misoperation protection circuit 22 in set side, reset
Side all becomes high level.If being entered into latch cicuit 23, then the value before keeping, the output before maintenance.Therefore, high side
The output of driver 21 becomes high level, and hot side switch element XD1 maintains conducting state.
Now, the output of logic or circuit OR1 becomes low level, and therefore, P-channel type MOS transistor PM1a, PM2a become
Conducting state.Thus, the output impedance step-down of two level shift circuits 24,25, therefore, parasitic capacitance Cds1, the charging of Cds2
Time shortens, and can restore quickly.
It addition, by latching misoperation protection circuit 22, according to the state of output signal HO of high-side driver 21, level
The impedance of shift circuit is different.That is, under output signal HO is low level state, the impedance of setdrn side is relatively low.Therefore,
Setdrn signal earlier returns to high level.Thus, stable action can be realized, and, set signal becomes connection afterwards
Time, can promptly respond.On the other hand, when output signal HO is high level, the impedance of resdrn side is relatively low.
Therefore, resdrn signal earlier returns to high level.Thus, stable action can be realized, and, reset signal becomes afterwards
Become and can promptly carry out response when connecting, hot side switch element XD1 can be driven rapidly.
On the other hand, according to existing pulse-generating circuit, as shown in Fig. 6 (b), at the P-channel MOS that misoperation prevents
Under the effect of transistor (PM1, PM2), resdrn signal becomes low level while, setdrn signal returns to high level, but
Delay can be produced.During this period, the latch misoperation protection circuit 22 of rear class works, and output signal does not changes, thus exports sound
Delay should be produced.
In embodiment 2, when producing dV/dt noise, additional logic or circuit OR1 action, make P-channel MOS brilliant
Body pipe (PM1, PM2) becomes conducting state, has relaxed delay when dV/dt noise produces.But, in the present embodiment, logical
Cross and make overlapping certain period between the high period of set signal, reset signal, thus be temporarily forming P channel MOS transistor
Conducting state while (PM1a, PM2a), reduces the impedance of the output of two level shift circuits.Thus, can be in next control of input
Before signal processed, the output state of level shift circuit is returned to steady statue.Therefore, in the present embodiment, no matter with or without
Produce dV/dt noise, delay can be relaxed all the time.
When the pulse spacing of set signal and reset signal being set to 50ns, 30ns, 10ns shown in Fig. 7～Fig. 9
The simulation result of main signal.
As main signal, record the output signal (out) from high-side driver 21, pulse-generating circuit 40 defeated
Go out i.e. set signal (set) and reset signal (reset), the output signal (dvdten) from logic or circuit OR1, displacement knot
Bundle set signal (setdrn), end-of-shift reset signal (resdrn).The pulse-generating circuit of present embodiment will be utilized
In the case of waveform solid line represent, represent utilizing the waveform dotted line in the case of existing pulse-generating circuit.
Such as, in the example (pulse spacing is 50ns) of Fig. 7, by utilizing the pulse-generating circuit of present embodiment,
Compared with the situation utilizing existing pulse-generating circuit, produce the delay alleviation effects of 2ns when rising, produce when declining
The delay alleviation effects of 5.8ns.Pulse spacing is the shortest, and this effect is the biggest, in the example (pulse spacing is 10ns) of Fig. 9,
Produce the delay alleviation effects of 15ns during rising, produce the delay alleviation effects of 17ns when declining.
Label declaration
1 half-bridge drive circuit
10 output circuits
20 high lateral circuits
21 high-side driver
22 latch misoperation protection circuit (protected location)
23 latch cicuits
24 connect data side level shift circuit (the 1st electrical level shift units)
25 cut-off signal side level shift circuits (the 2nd electrical level shift units)
26 NOT circuit
28 control signal output units
30 low-side circuitry
31 low side driver
40 pulse-generating circuits (impulse generating unit)
50,56 D flip-flop
51,52,53 logic circuit
54,55 multiplexer circuit
57 counter circuits
90 existing half-bridge drive circuits
99 existing high lateral circuits
OR1 logic or circuit (logic gate)
DH, DL diode
PS, PS1, PS2 power supply (power subsystem)
Claims (5)
1. a semiconductor device, the input signal of primary side positioning system is sent to and this primary side electricity by this semiconductor device
The secondary side positioning system that position system is different, it is characterised in that
There is the hot side switch element and low potential side switch element being connected in series and switch unit with described hot side
Power subsystem on the basis of the current potential of the junction point of part and described low potential side switch element, this hot side switch element is two
Action under the control signal of secondary side positioning system, this low potential side switch element is dynamic under the control signal of primary side positioning system
Make,
This semiconductor device has:
Impulse generating unit, this impulse generating unit, based on described input signal, produces and is used for making described hot side switch first
Part is set to the set signal of the pulse type of conducting state and for making described hot side switch element be set to non-conduction shape
The reset signal of the pulse type of state；
1st electrical level shift units, the 1st electrical level shift units secondary side positioning system hot side power supply potential with once
Between the low potential side power supply potential of side positioning system, the 1st resistance and the 1st switch elements in series are connected, open as the described 1st
Close the signal of element, it is provided that described set signal, connect from the junction point that is the 1st of described 1st resistance and the 1st switch element
Point obtains the level shift of secondary side positioning system and terminates set signal；
2nd electrical level shift units, the 2nd electrical level shift units secondary side positioning system hot side power supply potential with once
Between the low potential side power supply potential of side positioning system, the 2nd resistance and the 2nd switch elements in series are connected, open as the described 2nd
Close the signal of element, it is provided that described reset signal, connect from the junction point that is the 2nd of described 2nd resistance and the 2nd switch element
Point obtains the level shift of secondary side positioning system and terminates reset signal；
Control signal output unit, this control signal output unit terminates set signal and described level based on described level shift
End-of-shift reset signal, described hot side switch element is held in the control letter of conducting state or nonconducting state by output
Number；And
Protected location, this protected location is arranged at the prime of described control signal output unit, receives described level at the same time
In the case of end-of-shift set signal and described level shift terminate reset signal, provide to described control signal output unit
The signal of regulation, the described control signal before making described control signal output unit continue to put out,
This semiconductor device has:
3rd switch element, the 3rd switch element is connected with described 1st resistor coupled in parallel；
4th switch element, the 4th switch element is connected with described 2nd resistor coupled in parallel；And
Logic gate, the action in secondary side positioning system of this logic gate is, and input and have described 1st junction point, the 2nd even
The current potential of contact,
Described logic gate described 1st junction point, the 2nd junction point current potential all than the input threshold value of described logic gate
Voltage will low in the case of, making described 3rd switch element, the 4th switch element is conducting state.
2. semiconductor device as claimed in claim 1, it is characterised in that
Including feedback unit, this feedback unit, when described hot side switch element is in the conduction state, connects the described 1st
Point is drop-down, and by described 2nd junction point pull-up, when described hot side switch element is in nonconducting state, by the described 1st
Junction point pulls up, and by drop-down for described 2nd junction point.
3. semiconductor device as claimed in claim 1 or 2, it is characterised in that
Described impulse generating unit is as being used for making described hot side switch element be set to conducting state or non-conduction shape
The period that either one in the set signal of the main bang of state or reset signal is connected, begin to ramp up from this main bang
Rising makes the signal of the opposing party connect after certain time, generates the state making set signal and reset signal both sides be turned on.
4. a driving method for high lateral circuit, the input signal of electronegative potential system is sent to by the driving method of this high lateral circuit
High potential system, this high lateral circuit includes:
Pulse-generating circuit, this pulse-generating circuit, according to the rising edge of the electronegative potential system control signal inputted, generates and makees
It is the set signal of main differentiated pulse, according to the trailing edge of described electronegative potential system control signal, generates as main differentiated pulse
Reset signal；
1st level shift circuit, the 1st level shift circuit is by first for the N-channel type switch being carried out switching by described set signal
Part and resistance components in series connect and constitute；
2nd level shift circuit, the 2nd level shift circuit is by first for the N-channel type switch being carried out switching by described reset signal
Part and resistance components in series connect and constitute；
Latch cicuit, this latch cicuit is for the output valve according to described 1st level shift circuit and described 2nd level shift electricity
The output valve on road, keeps the state that high lateral circuit exports；
Drive circuit, the output based on this latch cicuit of this drive circuit, generate the signal driving hot side switch element；And
Latching misoperation protection circuit, this latch misoperation protection circuit makes described 1st level shift circuit and the 2nd level shift
The specified states of the output valve of circuit is not transferred to latch input,
The driving method of this high lateral circuit is characterised by,
Logic using the output valve of described 1st level shift circuit and the 2nd level shift circuit as input or electricity are set
Road, source terminal are connected with the hot side power supply potential of high lateral circuit and drain terminal and the output of the 1st level shift circuit
The the first P-channel type semiconductor element and the source terminal that connect are connected with the hot side power supply potential of high lateral circuit and drain
The second P-channel type semiconductor element that the output of terminal and the 2nd level shift circuit connects,
By the gate terminal of described first P-channel type semiconductor element and the second P-channel type semiconductor element and described logic or
The lead-out terminal of circuit connects,
When described pulse-generating circuit produces the main differentiated pulse of a side, the output of the opposing party produces from described main differentiated pulse
Play the secondary differentiated pulse of output after certain time, thus within certain period, make the set signal of this pulse-generating circuit and multiple
Position signal is high level.
The driving method of high lateral circuit the most as claimed in claim 4, it is characterised in that
By adjusting the output time of secondary differentiated pulse, thus utilize the output signal of described logic or circuit to control described the
One P-channel type semiconductor element and the grid voltage of the second P-channel type semiconductor element, adjust the micro-of described pulse-generating circuit
Sectors punching output is the pulse output time of high level, and by described first P-channel type semiconductor element and the second P-channel type
The grid voltage of semiconductor element is adjusted so that exceeding described first P-channel type semiconductor element and the second P-channel type
The action threshold voltage of semiconductor element, and adjust pulse application time.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012042568A JP5825144B2 (en) | 2012-02-28 | 2012-02-28 | Semiconductor device and high-side circuit driving method |
| JP2012-042568 | 2012-02-28 | ||
| PCT/JP2012/081414 WO2013128746A1 (en) | 2012-02-28 | 2012-12-04 | Semiconductor device and method for driving high-side circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104025454A CN104025454A (en) | 2014-09-03 |
| CN104025454B true CN104025454B (en) | 2016-12-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201280062352.9A Active CN104025454B (en) | 2012-02-28 | 2012-12-04 | Semiconductor device and the driving method of high lateral circuit |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US9325317B2 (en) |
| EP (1) | EP2822180B1 (en) |
| JP (1) | JP5825144B2 (en) |
| CN (1) | CN104025454B (en) |
| WO (1) | WO2013128746A1 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20160197614A1 (en) | 2016-07-07 |
| EP2822180A1 (en) | 2015-01-07 |
| EP2822180B1 (en) | 2018-09-12 |
| EP2822180A4 (en) | 2016-11-16 |
| US9325317B2 (en) | 2016-04-26 |
| JP5825144B2 (en) | 2015-12-02 |
| JP2013179501A (en) | 2013-09-09 |
| US9722610B2 (en) | 2017-08-01 |
| WO2013128746A1 (en) | 2013-09-06 |
| CN104025454A (en) | 2014-09-03 |
| US20140292392A1 (en) | 2014-10-02 |
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