CN113472330B

CN113472330B - Noise suppression circuit

Info

Publication number: CN113472330B
Application number: CN202110644574.2A
Authority: CN
Inventors: 刘利书
Original assignee: Midea Group Co Ltd; Guangdong Midea White Goods Technology Innovation Center Co Ltd; Midea Group Shanghai Co Ltd
Current assignee: Midea Group Co Ltd; Guangdong Midea White Goods Technology Innovation Center Co Ltd; Midea Group Shanghai Co Ltd
Priority date: 2021-06-09
Filing date: 2021-06-09
Publication date: 2023-11-03
Anticipated expiration: 2041-06-09
Also published as: CN113472330A

Abstract

The application discloses a circuit for suppressing noise. The circuit includes a pulse generation module and a level shift module. The output end of the pulse generating module is connected with the input end of the level shifting module, and the output end of the level shifting module outputs a level shifting signal. The level shift module includes a first branch and a second branch. The first branch includes a first switch. The control end of the first switch is connected to the first input end of the level shift module. The first channel end of the first switch is connected to the working voltage through the first impedance switching module. The second branch includes a second switch. The control end of the second switch is connected to the first input end of the level shift module through the first delay module. The first path end of the second switch is also connected to the control end of the first impedance switching module. The first path end of the first switch is connected to the first output end of the level shift module. The second switch controls the first impedance switching module to switch between a first impedance state and a second impedance state.

Description

Noise suppression circuit

Technical Field

The application relates to the electronic circuit technology, in particular to a circuit for inhibiting dVs/dt noise.

Background

In a gate drive circuit such as an IGBT drive chip, voltage variation often occurs with on-off of a switch in the circuit or lightning surge, noise of associated devices, or the like, resulting in dVs/dt noise. Where Vs is the high side floating return voltage or the common voltage between the high side and the low side in the gate drive circuit. To achieve level shifting of, for example, a low voltage signal to a high voltage signal, the gate drive circuit typically includes a level shift circuit using pulses. dVs/dt noise can cause a displacement current in the level shifting circuit. This displacement current may cause a logic inversion of the output of the level shift circuit and eventually may cause erroneous output of the entire circuit.

The influence of the displacement current is generally reduced by adding a filter circuit after the level shift circuit. However, the filter width of the filter circuit is limited, and a sufficient dVs/dt noise suppression capability cannot be obtained.

Disclosure of Invention

The application provides a circuit for suppressing noise, which is used for solving the problem of insufficient dVs/dt noise suppression capability of a grid driving circuit in the prior art.

In order to solve the problems, the application adopts a technical scheme that: a circuit for suppressing noise is provided. The circuit includes a pulse generation module and a level shift module. The output end of the pulse generating module is connected with the input end of the level shifting module, and the output end of the level shifting module outputs a level shifting signal. The level shift module includes a first branch and a second branch. The first branch is connected between an operating voltage and a ground voltage. The first branch includes a first switch. The control end of the first switch is connected to the first input end of the level shift module. The first channel end of the first switch is connected to the working voltage through the first impedance switching module. The second path terminal of the first switch is connected to the ground voltage. The second branch is connected between the operating voltage and the ground voltage. The second branch includes a second switch. The control end of the second switch is connected to the first input end of the level shift module through the first delay module. The first path end and the second path end of the second switch are respectively connected with the working voltage and the ground voltage. The first path end of the second switch is also connected to the control end of the first impedance switching module. The first path end of the first switch is connected to the first output end of the level shift module. . The second switch controls the first impedance switching module to switch between a first impedance state and a second impedance state. In the first impedance state, the first impedance switching module has a first impedance. In the second impedance state, the first impedance switching module has a second impedance. The modulus of the first impedance is greater than the modulus of the second impedance.

Compared with the prior art, the application reduces the time length and voltage fluctuation of the influence of dVs/dt noise in the first branch by arranging the first branch comprising the first impedance switching module and the second branch for controlling the on-off of the first impedance switching module, and enhances the dVs/dt noise suppression capability of the circuit.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 is a schematic circuit diagram according to one embodiment of the application.

FIG. 2 is a schematic diagram of the time variation of the Set signal according to one embodiment of the application.

Fig. 3 is a schematic circuit diagram according to a further embodiment of the application.

Fig. 4 is a schematic circuit diagram according to another embodiment of the application.

Fig. 5 is a schematic circuit diagram according to another embodiment of the application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Referring specifically to fig. 1, fig. 1 is a schematic circuit diagram illustrating a gate drive circuit 10 according to one embodiment of the present application.

As shown in fig. 1, the gate driving circuit 10 includes a high-voltage side driving portion 20 and a low-voltage side driving portion 30. The high-side driver 240 of the high-side driving part 20 outputs a high-side driving output HO to control the high-side switching element T ₁ . The low side driver 260 of the low side driving part 30 outputs a low side driving output LO to control the low side switching element T ₂ 。

Alternatively, the high-side switching element T ₁ And low pressureSide switching element T ₂ Is connected in series between the bus voltage VH and the ground voltage GND. High-side switching element T ₁ And a low-voltage side switching element T ₂ The voltage at the connection point between them is the high-voltage side floating return voltage Vs. Alternatively, the high-side switching element T ₁ And a low-voltage side switching element T ₂ Alternately conducting. When the high-voltage side switch element T ₁ On-and-low-side switching element T ₂ At the time of the off, the high-voltage side floating return voltage Vs is substantially equal to the bus voltage VH, that is, vs is at a high potential. While the high-side switching element T ₁ Turn-off and low-voltage side switching element T ₂ When turned on, the high-voltage side floating return voltage Vs is substantially equal to the ground voltage GND.

Alternatively, a load (not shown in the drawing) is connected between the high-voltage side floating return voltage Vs and the ground voltage GND.

Optionally, the high side floating voltage VB (also referred to as the operating voltage VB) is passed through the bootstrap diode D _{Bootstrapping} Is connected to a power supply voltage VCC. Optionally, the high side floating voltage VB passes through the bootstrap capacitor C _{Bootstrapping} Connected to the high-voltage side floating return voltage Vs. When the high-voltage side floating return voltage Vs varies between the bus voltage VH and the ground voltage GND, the dv/dt noise is generated in the high-voltage side floating return voltage Vs. The dVs/dt noise passes through the bootstrap capacitor C _{Bootstrapping} To the high side floating voltage VB, thereby generating the same dv s/dt noise in VB.

The high-pressure side driving portion 20 is described in detail below with continued reference to fig. 1. The present application is not limited to the specific implementation form of the low pressure side driving portion 30.

As shown in fig. 1, the high-side driving part 20 includes a pulse generating module 210, a level shifting module 220, an RS flip-flop 230, and a high-side driver 240, which are connected in steps. Specifically, the pulse generation module 210 receives a logic input IN from the outside, and outputs a first pulse signal and a second pulse signal. The level shift module 220 receives the above-described first pulse signal and second pulse signal from the pulse generation module 110, and outputs a level shift signal. The level shift signal includes a Set signal and a Reset signal. RS flip-flop 230 slave level shift module 220 receives the Set signal and the Reset signal and outputs a trigger signal SQ. The high side driver 240 receives the trigger signal SQ from the RS trigger 230 and outputs a high side drive output HO. When the high-side drive output HO is at the high level (H), the high-side switching element T ₁ Conducting. When the high-side drive output HO is at a low level (L), the high-side switching element T ₁ And (5) switching off.

Alternatively, the level shift module 220 is connected between the high-side floating voltage VB and the ground voltage GND. The RS flip-flop 230 and the high-side driver 240 are each connected between the high-side floating voltage VB and the high-side floating return voltage Vs to obtain electric power required for operation.

The respective modules of the high-pressure side driving portion 20 are described in detail below.

As shown in fig. 1, the pulse generation module 210 includes an input 2100 and at least two outputs. The at least two output terminals are a first output terminal Set and a second output terminal Reset respectively. The pulse generation module 210 receives a logic input IN from the outside from the input terminal 2100. The logic input IN is used for controlling the high-side switching element T through the high-side driving section 20 ₁ . The pulse generation module 210 generates a corresponding first pulse signal and a corresponding second pulse signal according to the logic input IN. Wherein, the first pulse signal is output from the first output terminal Set, and the second pulse signal is output from the second output terminal Reset. Optionally, the pulse width of the first pulse signal and the second pulse signal is 100ns-600ns. Alternatively, the first pulse signal and the second pulse signal are both square wave signals. Optionally, the high level portions of the first pulse signal and the second pulse signal do not overlap in time to prevent the RS flip-flop 230 from an unknown state.

As shown in fig. 1, the level shift module 220 is disposed at a next stage of the pulse generation module 210. The level shift module 220 includes a first input terminal N1 and a second input terminal N2. The first input terminal N1 is connected to the first output terminal Set of the pulse generating module 210, and is configured to receive a first pulse signal. The second input terminal N2 is connected to the second output terminal Reset of the pulse generating module 210, and is configured to receive a second pulse signal.

The level shift module 220 further includes a first branch and a second branch for outputting a Set signal.

The first branch is connected between the high-side floating voltage VB and the ground voltage GND. The first branch includes a first switch LD1. The control terminal of the first switch LD1 is directly connected to the first input terminal N1 of the level shift module 220. The first path end of the first switch LD1 is connected to the operating voltage VB via the first impedance switching module RR1, and the second path end of the first switch LD1 opposite to the first path end is connected to the ground voltage GND. Optionally, the first switch LD1 is a Laterally Diffused Metal Oxide Semiconductor (LDMOS) switch. The first switch LD1 may be other types of switches, which the present application is not limited to. Optionally, the first path terminal of the first switch LD1 is a drain. Optionally, the first switch LD1 further includes a drain capacitor C _d1 。

Optionally, the first impedance switching module RR1 includes a first capacitor C1, a first voltage drop switch MP1, and a first zener diode D1 connected in parallel between the first path end of the first switch LD1 and the high-side floating voltage VB. Optionally, the first zener diode D1 is a zener diode. Optionally, the first voltage drop switch MP1 is a PMOS tube. Optionally, a first path end of the first voltage drop switch MP1 is connected to the operating voltage VB, and a second path end of the first voltage drop switch MP1 is connected to a first path end of the first switch LD1. Alternatively, both ends of the first capacitor C1 are connected to the first path end of the first switch LD1 and the high-side floating voltage VB, respectively. Optionally, an anode of the first zener diode D1 is connected to the first path end of the first switch LD1, and a cathode of the first zener diode D1 is connected to the high-side floating voltage VB. Optionally, the clamping voltage of the first zener diode D1 is 15V, which is not limited in the present application.

Alternatively, when the first voltage drop switch MP1 is turned off, the first impedance switching module RR1 is in the first impedance state and has a first impedance between the first path end of the first switch LD1 and the high-side floating voltage VB. When the first voltage drop switch MP1 is turned on, the first impedance switching module RR1 is in the second impedance state, and has a second impedance between the first path end of the first switch LD1 and the high-side floating voltage VB. Optionally, the modulus of the first impedance is greater than the modulus of the second impedance. Those skilled in the art will readily appreciate that the impedance generally includes three types of resistance, capacitive reactance and inductive reactance. In this embodiment, the impedance of the first impedance switching module RR1 includes a resistance and a capacitance.

Referring to fig. 1, when the first voltage drop switch MP1 is turned off, a first impedance between the first path end of the first switch LD1 and the high-side floating voltage VB isWherein C1 is the capacitance value of the first capacitor C1.ω is the frequency of the voltage across the first capacitor C1. Since the voltage across the first capacitor C1 is typically a direct voltage, i.e. ω is zero. Thus, the modulus of the first impedance may be considered infinite. When the first voltage drop switch MP1 is turned on, the second impedance between the first path end of the first switch LD1 and the high voltage side floating voltage VB is ∈>. Obviously, the modulus of the second impedance is smaller than the modulus of the first impedance. The second branch is connected between the high-side floating voltage VB and the ground voltage GND. The second branch comprises a second switch LD2. Optionally, the second switch LD2 is an LDMOS switch. The control terminal of the second switch LD2 is connected to the first input terminal N1 of the level shift module 220 via the first delay unit DU 1. The first path terminal of the second switch LD2 is connected to the high-side floating voltage VB via a first resistor R1. The second path terminal of the second switch LD2 is connected to the ground voltage GND. Optionally, the first path terminal of the second switch LD2 is further connected to the control terminal of the first voltage drop switch MP1, for controlling the on and off of the first voltage drop switch MP 1. The control end of the first voltage drop switch MP1 is the control end of the first impedance switching module RR 1. Optionally, when the second switch LD2 is turned off, the first voltage drop switch MP1 is turned off, and the first impedance switching module RR1 is in the first impedance state. Optionally, when the second switch LD2 is turned on, the first voltage drop switch MP1 is turned on, and the first impedance switching module RR1 is in the second impedance state.

Optionally, the first delay unit DU1 is configured to convert the first pulse signal into a first delayed pulse signal with a certain delay with respect to the first pulse signal. Optionally, the first pulse signal and the first delayed pulse signal have the same waveform. The length of the delay is, for example, 100ns-600ns, as the application is not limited in this regard. Optionally, the length of time of the delay is greater than the pulse width of the first pulse signal. The first pulse signal is input to the control terminal of the first switch LD1 to control the on and off of the first switch LD1, and the first delay pulse signal is input to the control terminal of the second switch LD2 to control the on and off of the second switch LD2.

Optionally, the first output terminal Set of the level shift module 220 is connected to the first output terminal of the first switch LD1 to output a Set signal. Optionally, the Set signal is used to control the high-side driving output HO to be high level, so that the high-side switching element T ₁ Conducting.

The level shift module 220 further includes a third branch and a fourth branch for outputting a Reset signal.

The third branch is connected between the high-side floating voltage VB and the ground voltage GND. The third branch comprises a third switch LD3. The control terminal of the third switch LD3 is directly connected to the second input terminal N2 of the level shift module 220. The first path end of the third switch LD3 is connected to the operating voltage VB via the second impedance switching module RR2, and the second path end of the third switch LD3 opposite to the first path end is connected to the ground voltage GND. Optionally, the third switch LD3 is an LDMOS switch. The third switch LD3 may be another type of switch, which is not limited in the present application. Optionally, the first path terminal of the third switch LD3 is a drain. Optionally, the third switch LD3 further comprises a drain capacitor C _d2 。

Optionally, the second impedance switching module RR2 includes a second capacitor C2, a second voltage drop switch MP2, and a second zener diode D2 connected in parallel between the first path end of the third switch LD3 and the high-side floating voltage VB. Optionally, the second zener diode D2 is a zener diode. Optionally, the second voltage drop switch MP2 is a PMOS tube. Optionally, a first path terminal of the second voltage drop switch MP2 is connected to the operating voltage VB, and a second path terminal of the second voltage drop switch MP2 is connected to a first path terminal of the third switch LD3. Alternatively, both ends of the second capacitor C2 are connected to the first path end of the third switch LD3 and the high-side floating voltage VB, respectively. Optionally, an anode of the second zener diode D2 is connected to the first path terminal of the third switch LD3, and a cathode of the second zener diode D2 is connected to the high-side floating voltage VB. Optionally, the clamping voltage of the second zener diode D2 is 15V, which is not limited in the present application.

Alternatively, when the second voltage drop switch MP2 is turned off, the second impedance switching module RR2 is in the third impedance state and has a third impedance between the first path end of the third switch LD3 and the high-side floating voltage VB. When the second voltage drop switch MP2 is turned on, the second impedance switching module RR2 is in the fourth impedance state, and has a fourth impedance between the first pass terminal of the third switch LD3 and the high side floating voltage VB. Optionally, the third impedance has a mode that is greater than the mode of the fourth impedance.

Referring to fig. 1, when the second voltage drop switch MP2 is turned off, a third impedance between the first path end of the third switch LD3 and the high-side floating voltage VB is. Wherein C2 is the capacitance value of the second capacitor C2.ω is the frequency of the voltage across the second capacitor C2. Since the voltage across the second capacitor C2 is typically a direct voltage, i.e. ω is zero. Therefore, the modulus of the third impedance can be regarded as infinity. When the second voltage drop switch MP2 is turned on, the fourth impedance between the first path end of the third switch LD3 and the high-side floating voltage VB is +.>. Obviously, the modulus of the fourth impedance is smaller than the modulus of the third impedance.

The fourth branch is connected between the high-side floating voltage VB and the ground voltage GND. The fourth branch includes a fourth switch LD4. Optionally, the fourth switch LD4 is an LDMOS switch. The control terminal of the fourth switch LD4 is connected to the second input terminal N2 of the level shift module 220 via the second delay unit DU 2. The first path terminal of the fourth switch LD4 is connected to the high-side floating voltage VB via a second resistor R2. The second path terminal of the fourth switch LD4 is connected to the ground voltage GND. Optionally, the first path terminal of the fourth switch LD4 is further connected to the control terminal of the second voltage drop switch MP2, for controlling the on and off of the second voltage drop switch MP 2. The control end of the second voltage drop switch MP2 is the control end of the second impedance switching module RR2.

Optionally, the second delay unit DU2 is configured to convert the second pulse signal into a second delayed pulse signal with a certain delay with respect to the second pulse signal. Optionally, the second pulse signal has the same waveform as the second delayed pulse signal. The length of the delay is, for example, 100ns-600ns, as the application is not limited in this regard. Optionally, the length of time of the delay is greater than the pulse width of the second pulse signal. Accordingly, the second pulse signal is input to the control terminal of the third switch LD3 to control the on and off of the third switch LD3, and the second delayed pulse signal is input to the control terminal of the fourth switch LD4 to control the on and off of the fourth switch LD4.

Optionally, a second output terminal Reset of the level shift module 220 is connected to a first output terminal of the second switch LD2 to output a Reset signal. Alternatively, the Reset signal is used to control the high side drive output HO to a low level to cause the high side switching element T to ₁ And (5) switching off.

Optionally, the electrical parameters of the first switch LD1 and the second switch LD2 are the same. The electrical parameters of the first capacitor C1 and the second capacitor C2 are the same. The electrical parameters of the first step-down switch MP1 and the second step-down switch MP2 are the same. The first delay unit DU1 and the second delay unit DU2 have the same electrical parameters. The electrical parameters of the first resistor R1 and the second resistor R2 are the same. The electrical parameters of the first zener diode D1 and the second zener diode D2 are the same. Here, the electrical parameter refers to a parameter affecting the electrical property of the element, for example, all of a resistance, a capacitance, an inductance, a material, and the like, which can affect the electrical property of the element.

Optionally, the electrical parameters of the first branch and the third branch are identical, and the electrical parameters of the second branch and the fourth branch are identical. This helps to prevent fluctuations or noise due to asymmetry in current or voltage etc. between the branches.

Referring to fig. 1, the rs flip-flop 230 is disposed at the next stage of the level shift module 220. Optionally, the RS flip-flop 230 is an active low flip-flop, and includes a first trigger terminal S, a second trigger terminal R, and a flip-flop output terminal Q. Optionally, the first trigger terminal S receives the Set signal and changes its level state. The second trigger terminal R receives the Reset signal and changes its level state. The flip-flop output terminal Q outputs a driver control signal according to the level state of the first flip-flop terminal S and the level state of the second flip-flop terminal R. The present application is not limited to the relationship between the level states of the first trigger terminal S and the second trigger terminal R and the driver control signal.

As shown in fig. 1, optionally, a pulse filter 250 is further provided between the RS flip-flop 230 and the level shifting module 220. The pulse filter 250 serves to filter noise in the Set signal and the Reset signal and transmit the filtered Set signal and Reset signal to the RS flip-flop 230.

Referring to fig. 1, the high side driver 240 is disposed at the next stage of the RS flip-flop 230. Optionally, the high-side driver 240 receives the driver control signal and outputs a corresponding high-side driving output HO to control the high-side switching element T ₁ Is turned on and off. The present application is not described in detail herein.

Referring now to fig. 1 and 2, the operation of the level shift module 220 is illustrated with the first leg and the second leg. Fig. 2 shows a relationship of time change of the Set signal output from the level shift module 220. As shown in fig. 1, when the first switch LD1 is turned off, the first branch is turned off, and the first output terminal Set of the level shift module 220 is connected to the high-side floating voltage VB via the first capacitor C1. At this time, the potential of the first output terminal Set of the level shift module 220 is equal to the high-side floating voltage VB. As shown in fig. 2, at time 0, the first switch LD1 receives the first pulse signal and the first pulse signal is at a high level, and the first switch LD1 is turned on. The first capacitor C1 starts to charge rapidly until the potential of the first capacitor C1 away from the first switch LD1 is equal to the high-side floating voltage VB and the second end of the first capacitor C1 is at the low potential VL near the ground voltage GND. Alternatively, the low potential VL is slightly larger than the ground voltage GND due to the influence of the first switch LD1. The potential of the first output terminal Set of the level shift module 220 or the potential of the Set signal is equal to the second terminal of the first capacitor C1, and the floating voltage VB also drops from the high voltage side to the low potential VL.

Alternatively, the above 0 time is only used to refer to a time, and does not constitute a limitation on a specific time.

Optionally, during the charging process, the first zener diode D1 may prevent the voltage difference across the first capacitor C1 from being too large, so as to protect the first capacitor C1.

Optionally, the duration of the first pulse signal is te. Then, as shown in fig. 2, at the time te, the first pulse signal ends and the first switch LD1 is turned off. Since the first capacitor C1 has no discharge path at this time, the potential across the first capacitor C1 remains unchanged. Therefore, as shown in fig. 2, the potential of the first output terminal Set of the level shift module 220 or the potential of the Set signal remains unchanged.

The delay time generated by the first delay unit DU1 is defined as td. Therefore, at time td, the first delay unit DU1 converts the first pulse signal into the first delay pulse signal and inputs the control terminal of the second switch LD2, and the second switch LD2 is turned on. A current starts to be generated in the second branch, which current generates a voltage drop across the first resistor R1. The voltage drop makes the control terminal of the first voltage drop switch MP1 connected to the second branch be at a high potential, and the first voltage drop switch MP1 is turned on. At this time, the first capacitor C1 starts to discharge until the second end of the first capacitor C1 is at the high potential VG near the high side floating voltage VB. Alternatively, the high potential VG may be equal to the high side floating voltage VB. Alternatively, the high potential VG may be slightly smaller than the high side floating voltage VB due to the influence of the first voltage drop switch MP1 and the influence of noise that may be present in the circuit. The potential of the first output terminal Set of the level shift module 220 or the potential of the Set signal is also increased from the low potential VL to the high potential VG as is the second terminal of the first capacitor C1.

Optionally, the duration te of the first pulse signal is smaller than the delay time td generated by the first delay unit DU 1.

Thus, through the above-described process, an active low Set signal as shown in fig. 2 is formed. The Set signal includes a rising edge and a falling edge and a low level segment therebetween. The low level segment is at a low potential VL, and the duration of the low potential VL is equal to the delay time td generated by the first delay unit DU1 minus the charging time of the first capacitor C1. The third and fourth branches generate an active low Reset signal in a manner similar to the active low Set signal generated by the first and second branches described above. And will not be described in detail herein.

The effect of the dVs/dt noise described above will be described below with reference to FIG. 1, taking the first and second branches as examples. The effect of the dVs/dt noise in the third and fourth branches is similar to that in the first and second branches and is therefore not described in detail herein.

First case: when the first switch LD1 is on and the second switch LD2 is off, i.e. in the period between 0 and te shown in fig. 2, the first voltage drop switch MP1 of the first branch is not on either. At this time, the dVs/dt noise generated in the high-side floating voltage VB generates a charging current or a discharging current in the first capacitor C1. However, the first output terminal Set of the level shift module 220 is always stabilized near the low potential VL. Therefore, the dVs/dt noise generated in the high-side floating voltage VB at this time does not affect the Set signal and even the operation of the high-side driver 240 by the level shifting module 220.

Second case: when both the first switch LD1 and the second switch LD2 are turned off, i.e., in the period between te to td shown in fig. 2, both the first branch and the second branch are turned off. At this time, the Set signal terminal is disconnected from the high-side floating voltage VB, and the Set signal terminal in the level shift block 220 is kept near the low potential VL. Therefore, the dVs/dt noise generated in the high-side floating voltage VB at this time does not affect the Set signal and even the operation of the high-side driver 240 by the level shifting module 220.

Third case: when the first switch LD1 is turned off and the second switch LD2 is turned on, i.e., in a portion after td shown in fig. 2, the first voltage drop switch MP1 of the first branch is turned on. At this time, level shiftThe first output terminal Set of the bit module 220 is connected to the high-side floating voltage VB through the turned-on first voltage drop switch MP 1. The dVs/dt noise generated in the high-side floating voltage VB may be conducted to the first output terminal Set of the level shifting block 220. The dVs/dt noise is coupled with the capacitance C of the first switch LD1 _d1 The coupling, the displacement current generated in the first branch is:

(1.1）

the displacement current I ₁ The voltage drop generated on the first voltage drop switch MP1 is

(1.2）

Wherein, the liquid crystal display device comprises a liquid crystal display device,the on-resistance after the first voltage drop switch MP1 is turned on.

Accordingly, in this case, a Set signal of the size ofVoltage fluctuations of (a).

To prevent the logic inversion of the Set signal and thereby cause the high-side switching element T ₁ Is not capable of exceeding the first voltage threshold V _T 。V _T Can be set by the user according to the actual situation, and the present application is not limited thereto. Then:

(1.3）

then it can be seen from equation (1.3):

……(1.4）

on-resistance R of switch MP1 due to first voltage drop _MP1 Is very small, therefore, equation (1.4)The right-hand value in the middle is relatively large. That is to say,the safety upper limit of (2) is greatly improved compared with the prior art.

As apparent from the above description, with the circuit of the present application,the noise affects the output of the Set signal only for a period around td shown in fig. 2. I.e.)>Noise affects the output of the Set signal only in a period in which the first pulse signal is low and the first delayed pulse signal is high. />The influence time of (2) becomes smaller and +.>The upper safety limit of (2) is greatly improved. Therefore, by adopting the first impedance switching module RR1, the present application reduces +.>Fluctuations in the Set signal caused by noise.

Similarly, for the third and fourth branches, similar to the first and second branches described above, we can also obtain,

……(1.5）

wherein, the liquid crystal display device comprises a liquid crystal display device,is the on-resistance of the second voltage drop switch MP2, C _d2 Is the capacitance of the second switch.

Likewise, for the third and fourth branches,noiseThe output of the Reset signal is affected only during a period in which the second pulse signal is low and the second delayed pulse signal is high. />The influence time of (2) becomes smaller, and +.>The upper safety limit of (2) is greatly improved. Therefore, by adopting the second impedance switching module RR2, the application reduces +.>Fluctuations in the Reset signal caused by noise.

Referring to fig. 3, fig. 3 shows a schematic circuit diagram according to a further embodiment of the application. Fig. 3 is substantially identical to the circuit of fig. 1, with the main differences: in fig. 3, one end of a first capacitor C1 is connected to a first path end of the first switch LD1, and the other end of the first capacitor C1 is connected to the high-side floating voltage VB via a third resistor R3; one end of the second capacitor C2 is connected to the first path end of the third switch LD3, and the other end of the second capacitor C2 is connected to the high-side floating voltage VB through the fourth resistor R4. In other words, the first capacitor C1 and the third resistor R3 are connected in series between the first path end and the second path end of the first voltage drop switch MP1, and the second capacitor C2 and the fourth resistor R4 are connected in series between the first path end and the second path end of the second voltage drop switch MP 2. By adding the third resistor R3 connected in series between the first capacitor C1 and the high-voltage side floating voltage VB in the first impedance switching module RR1, the application can increase the charge and discharge time of the first capacitor C1 and the second capacitor C2, the discharge curves of the first capacitor C1 and the second capacitor C2 are more gentle, and the total voltage change rate when the discharge process of the first capacitor C1 and the second capacitor C2 is overlapped with dV/dt noise is reduced, so that the noise reduction effect of the first impedance switching module RR1 and the second impedance switching module RR2 is improved.

Referring to fig. 3, when the first voltage drop switch MP1 is turned off, a first impedance between the first path end of the first switch LD1 and the high-side floating voltage VB. Wherein C1 is a capacitance value of the first capacitor C1, and R3 is a resistance value of the third resistor R3. ω is the frequency of the voltage across the first capacitor C1. The voltage across the first capacitor C1 is typically a dc voltage, i.e. ω is 0. Thus, the modulus of the first impedance may be considered infinite. When the first voltage drop switch MP1 is turned on, the second impedance between the first path end of the first switch LD1 and the high voltage side floating voltage VB is ∈>. Obviously, the modulus of the second impedance is smaller than the modulus of the first impedance.

Referring to fig. 3, when the second voltage drop switch MP2 is turned off, the fourth impedance between the first path end of the third switch LD3 and the high-side floating voltage VB is. Wherein C2 is the capacitance value of the second capacitor C2, and R4 is the resistance value of the fourth resistor R4. ω is the frequency of the voltage across the second capacitor C2. Since the voltage across the second capacitor C2 is typically a dc voltage, i.e. ω is 0. Therefore, the modulus of the third impedance can be regarded as infinity. When the second voltage drop switch MP2 is turned on, the fourth impedance between the first path end of the third switch LD3 and the high-side floating voltage VB is +.>. Obviously, the modulus of the fourth impedance is smaller than the modulus of the third impedance.

Referring to fig. 4, fig. 4 shows a schematic circuit diagram according to a further embodiment of the application. Fig. 4 is substantially identical to the circuit of fig. 1, with the main differences: in fig. 4, the first capacitor C1 in fig. 1 is replaced with a fifth resistor R5, and the second capacitor C2 in fig. 1 is replaced with a sixth resistor R6. Specifically, one end of the fifth resistor R5 is connected to the first path end of the first switch LD1, and the other end of the fifth resistor R5 is connected to the high-side floating voltage VB. One end of the sixth resistor R6 is connected to the first path end of the third switch LD3, and the other end of the sixth resistor R6 is connected to the high-side floating voltage VB. In other words, the fifth resistor R5 is connected between the first path end and the second path end of the first voltage drop switch MP1, and the sixth resistor R6 is connected between the first path end and the second path end of the second voltage drop switch MP 2. In general, replacing the first capacitor C1 with the fifth resistor R5 and replacing the second capacitor C2 with the sixth resistor R6 allows to configure the corresponding first and second impedance switching modules RR1 and RR2 in a lower cost manner. Meanwhile, the power consumption of the first and second impedance switching modules RR1 and RR2 is lower.

Referring to fig. 4, when the first voltage drop switch MP1 is turned off, a first impedance between the first path end of the first switch LD1 and the high-side floating voltage VB. Wherein, R5 is the resistance value of the fifth resistor R5. When the first voltage drop switch MP1 is turned on, the second impedance between the first path end of the first switch LD1 and the high voltage side floating voltage VB is ∈>. Obviously, the modulus of the second impedance is smaller than the modulus of the first impedance.

Referring to fig. 4, when the second voltage drop switch MP2 is turned off, the third impedance between the first path end of the third switch LD3 and the high-side floating voltage VB is. When the second voltage drop switch MP2 is turned on, the fourth impedance between the first path end of the third switch LD3 and the high-side floating voltage VB is +.>. Obviously, the modulus of the fourth impedance is smaller than the modulus of the third impedance.

Referring to fig. 5, fig. 5 shows a schematic circuit diagram according to a further embodiment of the application. Fig. 5 is substantially identical to the circuit of fig. 4, with the main differences: in fig. 5, the first path of the first voltage drop switch MP1 is connected to the operating voltage VB through a seventh resistor R7, and the first path of the second voltage drop switch MP2 is connected to the operating voltage VB through an eighth resistor R8. Similar to that described above with reference to fig. 4, for the embodiment of fig. 5, the modulus of the second impedance is less than the modulus of the first impedance, and the modulus of the fourth impedance is less than the modulus of the third impedance.

The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.

Claims

1. A circuit (10) for suppressing noise, the circuit (10) comprising a pulse generating module (210) and a level shifting module (220), an output (2102, 2104) of the pulse generating module (210) being connected to an input (N1, N2) of the level shifting module (220), an output (Set, reset) of the level shifting module (220) outputting a level shifted signal (Set, reset), the level shifting module (220) comprising:

the first branch circuit is connected between the working Voltage (VB) and the ground voltage (GND), the first branch circuit comprises a first switch (LD 1), the control end of the first switch (LD 1) is connected with a first input end (N1) of the level shifting module (220), a first channel end of the first switch (LD 1) is connected with the working Voltage (VB) through a first impedance switching module (RR 1), and a second channel end of the first switch (LD 1) is connected with the ground voltage (GND); and

a second branch circuit, the second branch circuit comprises a second switch (LD 2), the control end of the second switch (LD 2) is connected with the first input end (N1) of the level shift module (220) through a first delay module (DU 1), the first path end and the second path end of the second switch (LD 2) are respectively connected with the working Voltage (VB) and the ground voltage (GND),

wherein the first path end of the second switch (LD 2) is also connected with the control end of the first impedance switching module (RR 1),

wherein a first path end of the first switch (LD 1) is connected with a first output end (Set) of the level shift module (220),

wherein the second switch (LD 2) controls the first impedance switching module (RR 1) to switch between a first impedance state in which the first impedance switching module (RR 1) has a first impedance and a second impedance state in which the first impedance switching module (RR 1) has a second impedance,

wherein the modulus of the first impedance is greater than the modulus of the second impedance.

2. The circuit (10) of claim 1, wherein the first impedance switching module (RR 1) is in the first impedance state when the second switch (LD 2) is off, and wherein the first impedance switching module (RR 1) is in the second impedance state when the second switch (LD 2) is on.

3. The circuit (10) of claim 1, wherein the first impedance switching module (RR 1) comprises a first voltage drop switch (MP 1) and a first capacitor (C1) connected between a first path terminal and a second path terminal of the first voltage drop switch (MP 1), the first path terminal of the first voltage drop switch (MP 1) is connected to the operating Voltage (VB), the second path terminal of the first voltage drop switch (MP 1) is connected to the first path terminal of the first switch (LD 1), and the control terminal of the first impedance switching module (RR 1) is the control terminal of the first voltage drop switch (MP 1).

4. The circuit (10) of claim 1, wherein the first impedance switching module (RR 1) comprises a first voltage drop switch (MP 1) and a fifth resistor (R5) connected between a first path terminal and a second path terminal of the first voltage drop switch (MP 1), the second path terminal of the first voltage drop switch (MP 1) is connected to the first path terminal of the first switch (LD 1), and the control terminal of the first impedance switching module (RR 1) is the control terminal of the first voltage drop switch (MP 1).

5. The circuit (10) according to claim 4, wherein the first pass terminal of the first voltage drop switch (MP 1) is connected to the operating Voltage (VB) via a seventh resistor (R7).

6. A circuit (10) according to claim 3, wherein the first impedance switching module (RR 1) further comprises a third resistor (R3), the first capacitor (C1) and the third resistor (R3) being connected in series between the first and second path terminals of the first voltage drop switch (MP 1).

7. The circuit (10) according to claim 1, wherein the first path terminal of the second switch (LD 2) is connected to the operating Voltage (VB) via a first resistor (R1).

8. A circuit (10) according to claim 3, characterized in that the first capacitance (C1) is connected in parallel with the first zener diode (D1).

9. The circuit (10) of claim 1, wherein the first switch (LD 1) and the second switch (LD 2) are laterally diffused metal oxide semiconductor switches.

10. A circuit (10) according to claim 3, wherein the first voltage drop switch (MP 1) is a PMOS tube.

11. The circuit (10) of claim 3, wherein the level shifting module (220) further comprises:

a third branch connected between the operating Voltage (VB) and the ground voltage (GND), the third branch including a third switch (LD 3), a control end of the third switch (LD 3) being connected to the second input end (N2) of the level shift module (220), a first path end of the third switch (LD 3) being connected to the operating Voltage (VB) via a second impedance switching module (RR 2), a second path end of the third switch (LD 3) being connected to the ground voltage (GND), and

a fourth branch circuit, the fourth branch circuit comprises a fourth switch (LD 4), the control end of the fourth switch (LD 4) is connected with the second input end (N2) of the level shift module (220) through a second delay module (DU 2), the first path end and the second path end of the fourth switch (LD 4) are respectively connected with the working Voltage (VB) and the ground voltage (GND),

wherein the first path end of the fourth switch (LD 4) is connected with the control end of the second impedance switching module (RR 2),

wherein a first path terminal of the third switch (LD 3) is connected to a second output terminal (Reset) of the level shift module (220),

wherein the fourth switch (LD 4) controls the second impedance switching module (RR 2) to switch between a third impedance state in which the second impedance switching module (RR 2) has a third impedance and a fourth impedance state in which the second impedance switching module (RR 2) has a fourth impedance, a modulus of the third impedance being larger than a modulus of the fourth impedance.

12. The circuit (10) of claim 11, wherein the second impedance switching module (RR 2) is in the third impedance state when the fourth switch (LD 4) is off, and wherein the second impedance switching module (RR 2) is in the fourth impedance state when the fourth switch (LD 4) is on.

13. The circuit (10) of claim 11, wherein the second impedance switching module (RR 2) comprises a second voltage drop switch (MP 2) and a second capacitor (C2) connected between a first path terminal and a second path terminal of the second voltage drop switch (MP 2), the first path terminal of the second voltage drop switch (MP 2) being connected to the operating Voltage (VB), the second path terminal of the second voltage drop switch (MP 2) being connected to the first path terminal of the third switch (LD 3), the control terminal of the second impedance switching module (RR 2) being the control terminal of the second voltage drop switch (MP 2).

14. The circuit (10) of claim 11, wherein the second impedance switching module (RR 2) comprises a second voltage drop switch (MP 2) and a sixth resistor (R6) connected between a first path terminal and a second path terminal of the second voltage drop switch (MP 2), the first path terminal of the second voltage drop switch (MP 2) being connected to the operating Voltage (VB), the second path terminal of the second voltage drop switch (MP 2) being connected to the first path terminal of the third switch (LD 3), the control terminal of the second impedance switching module (RR 2) being the control terminal of the second voltage drop switch (MP 2).

15. The circuit (10) of claim 13, wherein the second impedance switching module (RR 2) further comprises a fourth resistor (R4), the second capacitor (C2) and the fourth resistor (R4) being connected in series between the first and second path terminals of the second voltage drop switch (MP 2).

16. The circuit (10) of claim 14, wherein the first pass terminal of the second voltage drop switch (MP 2) is connected to the operating Voltage (VB) via an eighth resistor (R8).

17. The circuit (10) of claim 13, wherein the circuit is configured to,

the electrical parameters of the first switch (LD 1) and the third switch (LD 3) are identical,

the electrical parameters of the second switch (LD 2) and the fourth switch (LD 4) are identical,

the electrical parameters of the first voltage drop switch (MP 1) and the second voltage drop switch (MP 2) are the same,

the electrical parameters of the first capacitance (C1) and the second capacitance (C2) are identical.

18. The circuit (10) of claim 11, wherein,

a first input (N1) of the level shift module (220) is connected to a first output (2102) of the pulse generation module (210),

a second input (N2) of the level shift module (220) is connected to a second output (2104) of the pulse generation module (210).

19. The circuit (10) of claim 11, wherein the circuit (10) further comprises an RS flip-flop (230), a first trigger terminal (S) of the RS flip-flop (230) being connected to the first output terminal (Set) of the level shifting block (220), and a second trigger terminal (R) of the RS flip-flop (230) being connected to the second output terminal (Reset) of the level shifting block (220).

20. The circuit (10) of claim 19, wherein a first trigger terminal (S) of the RS flip-flop (230) is connected to a first output terminal (Set) of the level shifting block (220) via a pulse filter (250), and a second trigger terminal (R) of the RS flip-flop (230) is connected to a second output terminal (Reset) of the level shifting block (220) via a pulse filter (250).