JPH09200020A - Level shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To save power consumption of a level shift circuit controlling a high voltage side control object with a low voltage input signal and to improve the control speed. SOLUTION: The circuit is provided with a 1st control circuit 10 2nd control circuit 20) in which a high voltage transistor(TR) 11 (21) and a low voltage TR 12 (22) are connected in series. The high voltage TR of the control circuits 10, 20 is controlled by a potential at an interconnection point between the high voltage and the low voltage TRs of the other control circuit and a bias means 40 is connected in series with the low voltage TRs 12, 22 so as to operate the TRs in an active region in a steady-ON-state to limit currents i1, i2 to a low steady-state current is. A current control means 50 such as a capacitor 51 is connected in parallel with the bias means 40 to increase a current i1 or i2 just after the TRs 12, 22 are conductive to a high peak current ip and while the low voltage TRs 12, 22 are conductive/nonconductive alternately, the on/off of a control object 1 is operated by a potential at the interconnection point of both the TRs 21, 22 of the control circuit 20.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention operates a semiconductor element such as a MOS transistor, an insulated gate bipolar transistor, a bipolar transistor or the like, or an electronic circuit device, which receives a high-side power supply voltage, by an input signal on the low-voltage side, particularly on / off operation. The present invention relates to a level shift circuit used for

2. Description of the Related Art The semiconductor elements and electronic circuit devices to be operated as described above need to be operated under a power supply voltage suitable for their respective applications, and a control system for them usually has a power supply voltage as low as about 5V. Since it is incorporated in the integrated circuit device that operates below, it is difficult to directly control or operate the operation target by the output of the control system. Therefore, it is necessary to interpose the level shift circuit targeted by the present invention between the control system and the operation target, and it is customary to incorporate this into the integrated circuit device for the control system. An example of a conventional level shift circuit suitable for the purpose shown in FIGS. 5 and 6 is shown. FIG. 5 shows a case where the power MOS transistor 1 which is the operation target shown in the upper right part of the drawing operates by receiving the power supply voltage VH of 300V, for example.
A circuit for operating it by a low voltage input signal Si of 5 to 15V shown in the lower left of the figure is shown. A drive circuit 2 for the gate of the MOS transistor 1 is provided in association with the MOS transistor 1, and a floating power supply 2a of 15 V, for example, is connected to the power supply voltage VH side in order to operate it on the high voltage side. The MOS transistor 1 is for driving the load 3 on and off. The level shift circuit is composed of a transistor 4 which receives an input signal Si and a voltage divider circuit composed of a pair of resistors 5 and 6 connected between the transistor 4 and the power source voltage VH. When the input signal Si is high and the transistor 4 is turned on, a voltage drop generated in the resistor 5 by the current flowing from the power supply voltage VH side is given to the drive circuit 2. The drive circuit 2 is usually composed of a plurality of stages of inverters, and when the voltage drop of the resistor 5 is received as an operating voltage, the MOS transistor 1 is turned on, for example. The Zener diode 7 connected in parallel with the resistor 5 keeps this operating voltage constant and prevents overvoltage from being applied to the input of the drive circuit 2.
In the conventional example shown in FIG. 6, the operation target 1, which is a CMOS circuit, which operates by receiving a high-side power supply voltage VH of about 15V by a low-voltage input signal Si of about 5V, which is a so-called TTL level, is operated. Since the high-voltage side power supply voltage VH is much lower than that in the case of FIG. 5, the floating power supply 2a for the drive circuit 2 is omitted. The level shift circuit of this conventional example is a pair of operating circuits for receiving a high-side power supply voltage VH which is formed by connecting high-side transistors 11 and 21 and low-side transistors 12 and 22 in series.
It consists of 10, 20. As shown in the figure, the input signal Si is given to the low-voltage side transistor 12 of the operating circuit 10.
The low voltage side transistor 22 of 0 is supplied with its complementary signal by the inverter 60 which operates by receiving the low voltage side power supply voltage VL of 5V. Further, the high-voltage side transistor 21 of the operating circuit 20 is controlled by the potential of the interconnection point of the transistors 11 and 12 of the operating circuit 10, and the high-voltage side of the operating circuit 10 is controlled by the potential of the interconnection point of the transistors 21 and 22 of the operating circuit 20. The transistor 11 is controlled and the drive circuit 2 of the operation target 1 is operated by the potential of the interconnection point on the operation circuit 20 side. When the input signal Si is low, the low voltage side transistor 12 of the operating circuit 10
Turns off, but the low-voltage side transistor 22 of the operating circuit 20 turns on, which causes the high-voltage side transistor 11 of the operating circuit 10 to turn on.
Turns on. As a result, the high-voltage side transistor 21 of the operating circuit 20 is turned off, and the drive circuit 2 receives the input signal Si
It receives the same low operating voltage as. When the input signal Si changes to high, the on / off states of the transistors of the operating circuits 10 and 20 are reversed, and the drive circuit 2 receives a high operating voltage. As can be seen from this, in the conventional example of FIG.
In both the steady state, the high-voltage side and low-voltage side transistors are turned on and off in the steady state, so no current flows.Current flows only in the transient state immediately after the input signal Si changes to high and low, and is operated. The operating voltage received by the drive circuit 2 of the target 1 is switched between high and low.

However, any of the conventional level shift circuits as described above has the following problems. In the conventional example of FIG. 5, the power consumed by the level shift circuit tends to increase because there is a tradeoff with the operation speed for the operation target 1. That is, when the transistor 4 of FIG. 5 is turned on, power consumption, which is the product of the current flowing through the voltage dividing resistors 5 and 6 and the high-voltage side power supply voltage VH, is generated. However, since the operation speed for the operation target 1 is limited by the time constant which is the product of the capacitance value on the input side of the drive circuit 2 and the resistance value of the resistor 5, In order to obtain the operation speed, it is necessary to set the resistance value of the resistor 5 to a predetermined limit or less, and the same applies to this and the resistor 6 which constitutes the voltage dividing circuit. Therefore, there is a problem that the power consumption of the level shift circuit cannot be reduced below a certain limit, and that it increases rapidly as the high-voltage power supply voltage VH increases. On the other hand, in the conventional example of FIG. 6, as described above, the input signal Si is supplied to both the operation circuits 10 and 20 of the level shift circuit.
Since the current flows only at the beginning of the switching of the logic state of, the power consumption is much less than that in the case of FIG. Further, when the high-voltage side power supply voltage VH exceeds several tens of volts, it cannot be handled as it is in FIG. 6, but the problem can be solved by supplying power to the drive circuit 2 from the floating power supply 2a as shown in FIG. But,
From the result of operating this level shift circuit, it was found that there is a problem that the operation speed for the operation target 1 cannot be increased so much. That is, in order to increase the operation speed, it is necessary to rapidly charge and discharge the electrostatic capacitance on the input side of the drive circuit 2, and for that purpose, the on-resistance of the transistors 21 and 22 of the operation circuit 20 must first be lowered. It is desirable to reduce the on-resistance of the transistors 11 and 12 on the operating circuit 10 side as well, but if the on-resistance is reduced, the so-called shoot-through current that transiently flows through the operating circuits 10 and 20 when the input signal Si is switched increases. If the time period during which the through current flows is long due to variations in the operating time of the constituent transistors, the breakdown of the transistors and the deterioration of the characteristics are likely to occur. Therefore, in the conventional example of FIG. 6, the operation speed for the operation target 1 can be increased only within a safe range in which such troubles can be prevented. It is an object of the present invention to provide a level shift circuit that solves the problems of the conventional technique and can operate an operation target at high speed with the least power consumption.

In the level shift circuit of the present invention, first and second operation circuits in which a low-voltage side transistor and a high-voltage side transistor are connected in series are provided, and the high-voltage side transistor of each operation circuit is turned on / off. The state is controlled by the potential of the interconnection point between the low-voltage side and high-voltage side transistors of the other operating circuit, and the bias means is connected in series to the low-voltage side transistor of the operating circuit to activate the transistor in the steady ON state and the current. The current control means is provided in association with the bias means to increase the current flowing to the low-voltage side transistor at the beginning when the low-voltage side transistor is turned on, and the low-voltage side transistor of both operation circuits is turned on / off according to the logic state of the input signal. While alternately controlling the voltage, the potential of the operation target on the high voltage side is controlled by the potential at the interconnection point of the transistors on the low voltage side and the high voltage side of one operating circuit. To solve the expected problems by manipulating-off state. As can be seen from the above configuration, the present invention uses the first and second operation circuits to put the corresponding transistors in opposite ON / OFF states as in the conventional circuit of FIG. 6 which originally consumes less power. In addition, the circuit of the present invention reduces the power consumption by connecting the bias means referred to in the above configuration to the low-voltage side transistor of the operating circuit in series and operating in the active state in the steady ON state to throttle the current flowing therethrough. Further, a current control means is provided in association with the bias means, and in a transient state immediately after the low-voltage side transistor is turned on, the current flowing therethrough is temporarily increased so that the operation target can be operated at high speed. . In principle, the bias means and the current control means may be provided only for those who operate the operation target by the potential of the interconnection point of the high-voltage side and low-voltage side transistors in the first and second operation circuits. , Of course, it is desirable to provide for both operation circuits, and in some cases, the current flowing through the low voltage side transistor of the current control means on the side of the operation circuit that directly operates the operation target is increased more than the other operation circuit side. It is reasonable to set As the bias means, it is most advantageous to use a source resistance when the low-voltage side transistor of the operating circuit is a MOS transistor and an emitter resistance when it is a bipolar transistor. As the current control means, a capacitor connected in parallel with the bias means is used,
Alternatively, it is advantageous to use a short-circuiting transistor connected in parallel to the biasing means or a part thereof to turn on the low-voltage side transistor only for a short time when it is turned on. When the former capacitor is used as the current control means, it is preferable to connect a series resistor to it and set the degree to increase the current flowing in the low voltage side transistor by the resistance value. It is advantageous to improve the operation speed for the operation target by connecting in parallel and turning on the low-voltage side transistor in the off state. When the latter short-circuit transistor is used as the current control means, a one-shot circuit is used as means for turning it on accurately only within a predetermined short time, and an input signal or its complementary signal is given to this one-shot circuit to change its logic state. It is rational to set the ON time according to the change. In practicing the present invention, it may be advantageous to connect a high resistance in parallel to the high-voltage side transistor of the operating circuit, if necessary, and if a MOS transistor is used for this high-voltage side transistor, It is desirable to connect a Zener diode in parallel between the gate and the source that receives the power supply voltage on the high voltage side.
In addition, it is advantageous to use this Zener diode in a state where the high-voltage side transistor is in a Zener breakdown state in the ON state, and in this case, the Zener diode can also serve the role of the above-mentioned high resistance.

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a first embodiment of a level shift circuit according to the present invention together with related waveform diagrams, FIG. 2 shows a second embodiment, FIG. 3 shows a third embodiment, and FIG. 4 shows a fourth embodiment. 2A and 2B together with related waveform diagrams. In addition, although the operation target 1 is a MOS transistor in these embodiments, the present invention is not limited to this, and the present invention can be applied to a semiconductor device such as a bipolar transistor or various circuit devices. In the example shown in FIG. 1A, the operation target 1 which is a power MOS transistor is for driving the load 3 as in the conventional example of FIG. 5, and the driving circuit 2 is driven by the level shift circuit shown on the left side of the figure. Operated via. For example, the floating power supply 2a of 15V is used for supplying power to the drive circuit 2 which is usually composed of a plurality of stages of inverters.
Connected to the high-side power supply voltage VH. The level shift circuit of the present invention comprises a first operation circuit 10 and a second operation circuit 20.
A bias means 40 and a current control means 50
Inverter 60 that operates by receiving low-voltage power supply voltage VL
Is used in this context. First and second operating circuit 1
In the example of FIG. 4, 0 and 20 are high-voltage side transistors 11 and 21, which are MOS transistors, and low-voltage side transistors 12 and 22, respectively, connected in series. In this embodiment, the operation circuit 10 and
Bias means 40 is provided in each of 20 in the form of a source resistance for the n-channel low-voltage side transistors 12 and 22, and these low-voltage side transistors 12 and 22 are operated as so-called source followers in a steady state. A low-voltage input signal Si is applied to the gate of the low-voltage side transistor 12 of the first operating circuit 10, and a complementary signal of the input signal Si of the inverter 60 is applied to the gate of the low-voltage side transistor 22 of the second operating circuit 20. To be Further, in the illustrated embodiment, high resistances 11a and 21a are connected in parallel to the p-channel type high voltage side transistors 11 and 21 of the first and second operation circuits 10 and 20, respectively, and their gates and the high voltage side power supply voltage are connected. Zener diodes 11b and 21b are connected to the source receiving VH, respectively. These Zener diodes 11b and 21b may be provided only for protecting the gates of the high voltage side transistors 11 and 21, but it is rational to make the Zener breakdown occur when the transistors 11 and 12 are turned on. High resistance 11a or 21a
Can be omitted as appropriate. In the present invention, the first operating circuit 10 and the second operating circuit 20 control the latter high-voltage side transistor 21 by the potential of the interconnection point of the former two transistors 11 and 12 as shown in the figure, and The two transistors 21 and 22 are interconnected so that the former high-voltage side transistor 11 is controlled by the potential at the interconnection point. The operation voltage for the operation target 1 may be taken out from either of the operation circuits 10 and 20, but in the illustrated example, the second operation circuit 20 is used.
The potential of the interconnection point of the two transistors 21 and 22 is applied to the drive circuit 2 of the operation target 1. When the input signal Si is high, the low side transistor 12 of the operating circuit 10
Then, the high voltage side transistor 21 of the operating circuit 20 turns on when the gate potential drops. At this time, the low-voltage side transistor 22 of the operating circuit 20 is
Since the low voltage side transistor 11 of the operating circuit 10 is turned off by receiving the low voltage, the high voltage side transistor 11 of the operating circuit 10 is turned off by receiving the high voltage side power supply voltage VH at its gate. When the input signal Si is low, the on / off states of the transistors in the operating circuits 10 and 20 are all opposite. As described above, also in the present invention, the operation circuit 10 is provided as in the conventional example shown in FIG.
There is no steady-state through current in and 20. In the present invention, the current control means 50 is provided along with the bias means 40 to increase the current flowing through the corresponding low voltage side transistors 12 and 22 immediately after the ON operation. In the embodiment of FIG. 1, a capacitor 51 is used as the current control means 50, and a series resistor 52 is used together with the low voltage side transistors 12 and 22 as the bias means 40.
Connect in parallel to the source resistance of. Transistor 12
Since the charging current flows through the capacitor 51 immediately after turning on the transistor 22 and 22, the current flowing through the transistors 12 and 22 transiently increases and decreases as the charging ends. When the transistors 12 and 22 are turned off, the capacitor 51 is connected to the series resistor 52 and the bias means 40.
Is discharged through the source resistor. When the logic state of the input signal Si changes as shown in Fig. 1 (b), the operation circuit 10
1 (c) and 1 (d) show the waveforms of the currents i1 and i2 flowing in the low-voltage side transistor 12 of FIG. 1 and the low-voltage side transistor 22 of the operating circuit 20, respectively. As shown in the figure, a sharp peak current ip, which is the charging current of the capacitor 51, appears immediately after the transistors 12 and 22 are turned on in the waveforms of these currents i1 and i2, and after a short time, the currents i1 and i2 are very low. It is settled to the steady current is. The bias means 40 or the source resistance serves to reduce the steady current is, and activates them by applying the negative feedback as the source follower to the low voltage side transistors 12 and 22 in the steady state after charging the capacitor 51. The current i1 and i2 are set by the gate threshold value and the resistance value of the source resistance.
We narrow down to a steady current is of about μA. The bias means 40 is set so that the voltage drop due to the currents i1 and i2 is larger than the gate thresholds of the low-voltage side transistors 12 and 22 so that this narrowing-down effect can be enhanced. It is desirable to set the ratio of the above-mentioned peak current ip to the steady-state current is at least 10 times, whereby the high voltage side transistors 11 and 21 can be turned on at a high speed by rapid charging of their gates. To set a large peak current ip, current control means 50
The capacitance of the capacitor 51 of the high voltage side transistor 11 or 21
Is larger than the sum of the gate capacitance and the junction capacitance of the Zener diodes 11b and 21b, and it is preferable to set the number to 10 times that, for example, about 1 pF or more. In order to accelerate the OFF operation of the transistors 11 and 21, it is preferable to set their ON resistances low to increase the discharge speed of the other gate. Further, in order to increase the operation speed of the drive circuit 2 in this embodiment, the peak current ip of the current i2 of the second operation circuit 20 is set to, for example, the series resistor 52.
It is desirable to increase the charging / discharging speed with respect to the capacitance on the input side of the drive circuit 2 by setting the resistance value to a large value and setting the ON resistance of the high voltage side transistor 21 to a minimum value. As can be seen from the above description, according to the present invention, each time the logic state of the input signal Si is switched as shown in FIG. By supplying a large peak current ip to the low voltage side transistors 12 and 22 of the operation circuits 10 and 20, the current I is rapidly interrupted in the operation target 1 as shown in FIG. Power consumption of the operation circuits 10 and 20 can be suppressed to a necessary minimum by narrowing down the steady-state current is flowing in the and 22. In the second embodiment of the present invention shown in the circuit diagram of FIG. 2, pnp type bipolar transistors are used as the high voltage side transistors 11 and 21 of the first and second operating circuits 10 and 20 and a low voltage side transistor 12 is used. 22 to npn
The structure of the level shift circuit is almost the same as that of FIG. An emitter resistance is connected to the low voltage side transistors 12 and 22 as a bias means 40, and a current control means 50 connected in parallel with the bias resistance 40 has the same configuration as in FIG. The Zener diodes 11b and 21b connected to the gates of the high voltage side transistors 11 and 21 in the first embodiment are omitted in the circuit of FIG. Since the operation of the second embodiment is substantially the same as that of the first embodiment, its explanation is omitted. The circuit of the third embodiment of the present invention shown in FIG. 3 is almost the same as that of FIG. 1 (a), except that the short-circuit transistor 53 is connected in parallel to the capacitor 51 of the current control means 50. Capacitor
As described above, 51 is charged when the low-voltage side transistors 12 and 22 are turned on and then discharged in the off state, but when the resistance value of the series resistance 52 in the discharge path or the source resistance as the bias means 40 is large. If the operation cycle of the operation target 1 is short, charging will start before the completion of discharging. For this reason,
In the circuit of FIG. 3, the short-circuit transistor on the first operating circuit 10 side
A complementary signal of the input signal Si from the inverter 60 is applied to 53, and the input signal Si is applied to the short-circuit transistor 53 on the second operating circuit 20 side to turn on the low-voltage side transistors 12 and 22 respectively, thereby turning on the capacitor 51. Short-circuit and discharge completely. Since the capacitor 51 is completely discharged even if the resistance value of the source resistance for the bias means 40 is high, the peak current ip of the current il or i2 can be set large in the third embodiment, or the operation target 1 The operating frequency can be increased to about 1 MHz or higher. In the fourth embodiment of the present invention shown in FIG. 4, as shown in the circuit diagram of FIG. 4 (a), the short circuit transistor 53 is used as the current control means 50 in at least a part of the source resistance for the bias means 40. On the other hand, in the example shown in the figure, the source resistance is
Is divided into two parts and connected in parallel to the resistance part 42, and each time the corresponding low-voltage side transistors 12 and 22 of the operating circuits 10 and 20 are turned on, they are turned on for a short time immediately thereafter, thereby The peak current ip set to a predetermined value as the currents i1 and i2 shown in FIGS. 4 (e) and 4 (f) is passed to the side transistors 12 and 22. In the circuit example of FIG. 4A, the low-side power supply voltage VL is supplied to the one-shot circuit 54 by using the one-shot circuit 54 as means for accurately turning on the short-circuiting transistor 53 for a predetermined short time. The operating circuit 10 side supplies the input signal Si and the operating circuit 20 side supplies the complementary signal, respectively, and the corresponding shorting transistor 53 is switched each time the logic state of the input signal Si switches as shown in FIG. 4 (b).
The high ON operation commands S1 and S2 shown in FIGS. 4 (c) and 4 (d) are given for a short time of, for example, 50 to 100 nS.
As a result, the low side transistors 12 and 22 of the operating circuits 10 and 20 are
Currents i1 and i2 shown in Fig. 4 (e) and Fig. 4 (f), respectively.
A peak current ip within the set time is generated by the one-shot circuit 54, and of course, the currents i1 and i2 after the elapse of this set time are reduced to the low steady-state current is set by the bias means 40. In the circuit of FIG. 4 (a), the drive circuit 2 of the operation target 1 and the floating power supply 2a for the same which are used in the above-described embodiments are omitted, and the operation target 1 is replaced with both transistors 21 of the operation circuit 20. It is designed to operate directly at the potential of 22 interconnection points. Therefore, in the embodiment of FIG. 4, it is necessary to increase the operating force on the operating circuit 20 side compared to the operating circuit 10 side, and as a result, as shown in FIGS. 4 (e) and 4 (f),
The peak current ip of the current i2 on the 20 side is set to be larger than the peak current ip of the current i1 on the operation circuit 10 side. The setting of the value of the peak current ip can be easily adjusted by, for example, the distribution ratio of the resistance values to the resistance portions 41 and 42 for the bias means 40, and the peak current ip on the operating circuit 20 side is, for example, when the steady current is is 20 μA. It is set to 20mA, which is three orders of magnitude larger. The peak current ip on the side of the operation circuit 20 enhances the speed of the on-operation of the operation target 1, but in order to increase the speed of the off-operation, the high-voltage side transistor 21 having a low on-resistance is used as the operation target 1. It is preferable to discharge the capacitance of the gate of the MOS transistor within a short time. FIG. 4 (g) shows the waveform of the current I flowing through the operation target 1 directly operated by the operation circuit 20 configured as described above. As shown in the figure, the current I has a steep intermittent waveform as in the case of the embodiment of FIG. 1, and the time required for the on / off operation of the operation target 1 in this case is about 50 nS. In addition, in response to the strengthening of the driving force on the operating circuit 20 side, the high voltage side transistor 21 of the operating circuit 20 is also used on the operating circuit 10 side.
It is desirable to slightly enhance the driving force for the transistor 21. Therefore, it is preferable to use the transistors 11 and 12 having low on-resistance to speed up the charging and discharging of the gate capacitance of the transistor 21. In the circuit shown in FIG. 4 (a), the high resistances 11a and 21a connected in parallel to the high voltage side transistors 11 and 21 of the operation circuits 10 and 20 in the above embodiments are omitted and the gate side Zener diode 11b and 21b is configured to have the same function. For example, since the high-voltage side transistor 21 of the operation circuit 20 is turned on when the low-voltage side transistor 12 of the operation circuit 10 is on, the current i1 is supplied from the high-voltage side power supply voltage VH via the Zener diode 21b for the transistor 21. Flow to. Of course, the Zener diodes 11b and 21b in this case correspond to the corresponding transistors 11 and 21.
The Zener voltage is selected so that it will break down in the ON state. The present invention can be carried out in various aspects other than the embodiment described above. For example, in the illustrated embodiment, an operation potential is applied to the operation target 1 from the second operation circuit 20, but since both operation circuits 10 and 20 have a symmetrical configuration, from the first operation circuit 10 side. An operating potential may be applied. Further, in the embodiment, the current control means 50 is provided in both the operation circuits 10 and 20, but the peak current ip of the currents i1 and i2 should be set as necessary as can be seen from the embodiment of FIG. In some cases, it may be provided only on one of the operation circuits 10 and 20, particularly on the one which applies the operation potential to the operation target 1, and the bias means 40 corresponding to the omitted current control means 50 may be omitted in some cases. It is also possible.

As described above, in the level shift circuit of the present invention, in order to operate the operation target such as the power semiconductor device connected to the high voltage side power supply voltage by the low voltage input signal, the low voltage side transistor and the high voltage side First and second operating circuits in which the side transistors are connected in series, bias means connected in series to the low-voltage side transistors of the operating circuit, and current control means connected to the bias means, The low-voltage side transistors of both operation circuits are controlled to be turned on and off alternately according to the logical state of the input signal as an operation command for the operation target, and the on-off state of the high-voltage side transistors of each operation circuit is changed to another state. While controlling by the potential of the interconnection point of the low-voltage side and high-voltage side transistors of the operating circuit, By manipulating the state of the on-off of the operation target undergoing high-voltage power source voltage by the potential of interconnections points include the following effects. (a) The low-voltage side transistor to which the bias means is connected operates in the active state as a source follower or emitter follower, and the current flowing through it is narrowed down to a low level in a steady ON state. Power consumption can be reduced to a level that can be practically ignored. (b) The current flowing in the low-voltage side transistor that operates as a source follower or emitter follower can be set accurately by the operating threshold value on the input side and the resistance value given to the bias means, and the value of the high-side power supply voltage received by the operating circuit. Since it is hardly affected by fluctuations in the power supply voltage, it is possible to surely suppress the power consumption below the allowable limit while expanding the range of the high-voltage power supply voltage to which the level shift circuit can be applied. (c) The current flowing in the transient state immediately after the low-voltage side transistor of the operating circuit is turned on can be greatly increased for a short time by the current control means, and the operating speed for the operation target can be remarkably increased as compared with the conventional one. Since the peak current value in the transient state is determined by the constants of the circuit elements constituting the current control means, etc., the operating speed can be set accurately according to the desired value. As the bias means for the circuit of the present invention, in the embodiment in which the source resistance is connected when the low-voltage side transistor of the operating circuit is a MOS transistor and the emitter resistance is connected when the operating circuit is a bipolar transistor, the bias means is composed of simple circuit elements. As a result, the low-voltage side transistor is operated as a source follower or an emitter follower, and a steady current flowing therein can be stably narrowed down. The mode in which the capacitor is used as the current control means has an advantage that the circuit configuration can be simplified, and the mode in which the series resistor is connected to the capacitor has the advantage that the peak current to be flown to the low voltage side transistor can be accurately set by the resistance value of the capacitor. The mode in which the short-circuited transistor is connected in parallel to and is turned on in the off state of the low-voltage side transistor has the effect of increasing the operation speed for the operation target. Further, the mode in which the short-circuit transistor is connected in parallel to at least a part of the bias means as the current control means and is turned on only for a short time immediately after the low-voltage side transistor is turned on has the effect of further increasing the operation speed for the operation target. The mode in which it is controlled by the one-shot circuit has the effect that the short-circuit transistor can be turned on to accurately set the time at which the peak current should flow to the low-voltage side transistor. This current control means sets the peak current flowing through the low-voltage side transistor on the side of the operation circuit that applies the operation potential to the operation target to be larger than that on the other operation circuit side. The drive circuit for the operation target and the floating power supply therefor are set. Has the advantage that it can be omitted. The mode in which a high resistance is connected in parallel to the high voltage side transistor of the operating circuit has the advantage that the current flowing in the low voltage side transistor can be stabilized, and the mode in which a Zener diode is connected to the gate or emitter of the high voltage side transistor is the high voltage side transistor. There is an advantage that it can be protected and the reliability of the operation can be improved, and a mode in which the Zener breakdown occurs in the high voltage side transistor in the ON state has an effect that the above-mentioned high resistance can be omitted.

[Brief description of drawings]

1 shows a first embodiment of a level shift circuit according to the present invention and related waveforms, FIG. 1 (a) is a circuit diagram thereof, FIG. 1 (b) is a waveform diagram of an input signal, and FIG. The waveform diagram of the current flowing through the low-voltage side transistor of the first operating circuit, the same figure (d) is the waveform diagram of the current flowing through the low-voltage side transistor of the second operating circuit,
FIG. 6 (e) is a waveform diagram of the current to be operated.

FIG. 2 is a circuit diagram of a level shift circuit showing a second embodiment of the circuit of the present invention.

FIG. 3 is a circuit diagram of a level shift circuit showing a third embodiment of the circuit of the present invention.

FIG. 4 shows a fourth embodiment of the inventive circuit and related waveforms,
(A) is a circuit diagram of the level shift circuit, (b) is a waveform diagram of its input signal, (c) is a waveform diagram of the ON operation command by the one-shot circuit on the first operation circuit side, (D) is a waveform diagram of the ON operation command by the one-shot circuit on the second operating circuit side, (e) is a waveform diagram of the current flowing through the low-voltage side transistor of the first operating circuit, (f) ) Is a waveform diagram of the current flowing in the low-voltage side transistor of the second operating circuit,
(g) is a waveform diagram of the current of the operation target.

FIG. 5 is a circuit diagram of a conventional level shift circuit.

FIG. 6 is a circuit diagram of a conventional example having a different level shift circuit.

[Explanation of symbols]

1 MOS transistor as operation target 2 Drive circuit for operation target 2a Floating power source for drive circuit 3 Load for operation 10 First operation circuit 11 High-voltage side transistor 11a of first operation circuit High voltage for high-voltage side transistor 11 Resistor 11b Zener diode for high side transistor 11 12 Low side transistor for first operating circuit 20 Second operating circuit 21 High side transistor for second operating circuit 21a High resistance 21b High side transistor 21 for high side transistor 21 High voltage side transistor 21 Zener diode for use 22 Low-voltage side transistor of second operating circuit 40 Bias resistor as bias means 41, 42 Partial resistance of bias resistor 50 Current control means 51 Capacitor as current control means 52 Series resistance to capacitor 53 Current control means Short-circuit transistor 54 One-shot circuit of current control means 60 Input signal I Current that flows from the operation target to the load i1 Current that flows in the first operation circuit i2 Current that flows in the second operation circuit ip Peak current that flows in the operation circuit is Steady current that flows in the operation circuit Si Input signal S1 First operation ON operation command by the one-shot circuit on the circuit side S2 ON operation command by the one-shot circuit on the second operation circuit VH High-voltage side power supply voltage VL Low-voltage side power supply voltage

Claims (12)

[Claims] 1. A level shift circuit for operating a high-voltage side operation target according to a low-voltage side input signal, comprising first and second operation circuits in which a low-voltage side transistor and a high-voltage side transistor are connected in series, respectively. Provided, the on / off state of the high-voltage side transistor of each operation circuit is controlled by the potential at the interconnection point of the low-voltage side and high-voltage side transistors of other operation circuits, and the bias means is connected in series to the low-voltage side transistor of the operation circuit. Then, in the steady ON state, the transistor is activated to reduce the current flowing through it,
A current control means is provided in association with the bias means to increase the current flowing through the corresponding low-voltage side transistor in the process of changing from the off state to the on state, so that the low-voltage side transistors of both operation circuits are changed according to the logic state of the input signal. A level characterized by controlling the ON and OFF states alternately to operate the ON / OFF state of the operation target on the high voltage side by the potential of the interconnection point of the low voltage side and high voltage side transistors of one operation circuit. Shift circuit. 2. A level shift circuit according to claim 1, wherein a MOS transistor is used as a low voltage side transistor in the operating circuit, and a source resistance is connected as a bias means for the MOS transistor. 3. A level shift circuit according to claim 1, wherein a bipolar transistor is used as a low-voltage side transistor in the operating circuit, and an emitter resistance is connected as a bias means for the bipolar transistor. 4. A level shift circuit according to claim 1, wherein a capacitor is connected in parallel to the bias means as a current control means. 5. A level shift circuit according to claim 4, wherein a series resistor is connected to the capacitor. 6. A level shift circuit according to claim 4, wherein a short-circuit transistor is connected in parallel to the capacitor to turn on the corresponding low-voltage side transistor in the off state. 7. The circuit according to claim 1, wherein a short-circuiting transistor as a current control means is connected in parallel to at least a part of a resistor as a biasing means, and a corresponding low-voltage side transistor is changed from an off state to an on state. A level shift circuit characterized in that the short-circuiting transistor is turned on for a predetermined short time when changing. 8. A circuit according to claim 7, wherein a one-shot circuit is used as means for turning on the short-circuiting transistor within a predetermined short time, and an input signal or its complementary signal is applied to the one-shot circuit to change the logic state of the signal. A level shift circuit characterized by being operated in accordance with 9. The circuit according to claim 1, wherein the ON-state current of the corresponding low-voltage side transistor is controlled by the current control means on the side of the operating circuit that applies the operating potential to the operation target more than the other operating circuit side. A level shift circuit characterized in that it is designed to be greatly increased. 10. A level shift circuit according to claim 1, wherein a high resistance is connected in parallel to a high voltage side transistor of the operating circuit. 11. The circuit according to claim 1, wherein the high-voltage side transistor of the operating circuit is a MOS transistor, and a Zener diode is connected in parallel between the gate and the source for receiving the power supply voltage. Level shift circuit characterized by. 12. A level shift circuit according to claim 11, wherein the zener diode is zener-breakdown when the high-voltage side transistor is on.