JP2006157400A - Driver circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driver circuit for establishing a high speed operation and low power consumption. <P>SOLUTION: This driver circuit for inputting a logical signal X with a low potential side power source as a reference, and for generating a logical signal Y by using a high potential side power source Vcc is configured of a level shift circuit 10, an output circuit 20, a first detection control circuit 30, and a second detection control circuit 40. In this case, a pull-down circuit 21 and transistors Q11 and Q21 are complementarily driven to be turned on/off by a logical signal X to be inputted to the level shift circuit 10 and an inverted logical signal X<SP>*</SP>, and drain currents I1 flowing to a driving circuit 11 are controlled based on a control signal out1 from the first detection control circuit 30, and drain currents I2 flowing to a pull-down circuit 21 are controlled based on a control signal out2 from the second detection control circuit 40. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a driver circuit that generates an output logic signal based on a high-potential side power source from an input logic signal based on a low-potential side power source. In particular, the semiconductor switching element connected to the high-potential side power source is driven on and off. The present invention relates to a driver circuit used for this purpose.

  FIG. 3 is a circuit diagram showing a conventional driver circuit. Here, a logic signal X based on the low-potential side power supply is supplied to the gate terminal of an N-channel MOSFET (hereinafter simply referred to as a transistor) Q12, which becomes a logic signal Y based on the high-potential power supply Vcc. It is converted so as to drive the drive target.

  In FIG. 3, a P-channel transistor Q1 to be driven is a semiconductor switching element whose source terminal is connected to the high potential side power supply Vcc, and the potential at the connection point A is pulled up by the resistor R1. The N-channel transistor Q12 whose gate terminal is supplied with the input logic signal X is configured such that the source terminal is grounded, the drain terminal is connected to the connection point A, and the potential is pulled down. Note that the Zener diode ZD connected in parallel with the resistor R1 limits the gate voltage V1 of the transistor Q1 to (Vcc−Vz) by the Zener voltage Vz.

  When the transistor Q12 is off, the potential at the connection point A is pulled up by the resistor R1 and the gate-source voltage Vgs of the transistor Q1 becomes 0 V, so that the transistor Q1 is turned off. When the input logic signal X is inverted and the transistor Q12 is turned on, the potential at the connection point A is pulled down by the voltage R1 × I1 by its drain current I1, and the Zener voltage Vz of the Zener diode ZD connected in parallel with the resistor R1. When it becomes larger, the gate voltage V1 of the transistor Q1 is clamped by the Zener voltage Vz, and the transistor Q1 is turned on.

  In the drive circuit having the above configuration, when the transistor Q12 is off, the potential at the connection point A is passively pulled up by the resistor R1, so that the turn-off time of the transistor Q1 is the capacitance between the gate and the source of the transistor Q1. And the time constant obtained by integrating the resistance value of the resistor R1. For this reason, in order to shorten the turn-off time of the transistor Q1, it is necessary to reduce the resistance value of the resistor R1, but by reducing this resistance value, the power consumption when the transistor Q1 is turned on increases. There was a problem that.

  In order to solve such a problem, it is necessary to flow a large current only during a limited period of turn-on or turn-off, and flow a small current during other periods. Conventionally, various methods have been proposed that achieve both high speed switching operation and low power consumption (see Patent Documents 1 and 2).

FIG. 4 is a circuit diagram showing another example of a conventional driver circuit. A technique for solving the problem of trade-off between operating speed and current consumption will be described.
In the driver circuit of FIG. 4, P-channel transistors Q11 and Q21 are connected in parallel with resistors R1 and R2 that pull up the potentials at connection points A and B, and the gate terminals of transistors Q11 and Q21 are connected to each other's drain terminals. The P-channel transistor Q1, which is connected and driven, is driven on and off by the potential at the connection point B. N-channel transistors Q12 and Q22 are connected in series to the transistors Q11 and Q21, respectively.

In FIG. 4, when the logic signal X is supplied to the gate terminal of the transistor Q12 and the inverted logic signal X ^* is supplied to the gate terminal of the transistor Q22, and the transistors Q12 and Q22 are complementarily turned on and off, the corresponding transistors Q21 and Q21 The drain currents I1 and I2 of Q11 flow alternately, and the transistors Q21 and Q11 are driven on and off to actively pull up the potentials at the connection points A and B. Therefore, the turn-off time of the transistor Q1 can be shortened compared to the circuit example of FIG. Note that Zener diodes ZD1 and ZD2 are provided at the connection points A and B in parallel with the resistors R1 and R2, respectively.

Here, since the transistors Q11 and Q21 are configured to be complementarily turned on and off with the transistors Q12 and Q22, unlike the driver circuit of FIG. 3, there is almost no through current constantly. Therefore, the through current during operation can be suppressed and the current consumption can be extremely reduced.
Japanese Patent Laid-Open No. 9-200020 JP-A-9-214317

  However, the driver circuit of FIG. 4 also has the problem that the transistors Q11 and Q12 or the transistors Q21 and Q22 are simultaneously turned on during the on / off transition period, and a through current is generated between the high potential side power supply and the ground. there were.

  FIG. 5 is a state transition diagram showing the on / off states of the transistors Q11, Q12, Q21, and Q22 when the transistor Q1 transitions from on to off. As shown here, in the transition period from on to off of the transistor Q1, the transistors Q11 and Q12 connected in series always pass through the simultaneous on state (state 2 in FIG. 5). Although not shown here, the same applies to the case where the transistor Ql transitions from OFF to ON, and the driver circuit of FIG. 4 is essentially unable to operate so as not to generate a through current.

  In order to increase the switching operation speed with the driver circuit of FIG. 4, it is necessary to quickly charge and discharge the capacitance between the gate and source of the transistors Qll and Q21. However, for this purpose, the transistors Q12 and Q22 must be configured to have a low on-resistance. In this case, however, there arises a problem that a large through current is generated in the above-described on-off transition period, resulting in an increase in current consumption.

  The present invention has been made in view of the above points, and in the case of generating an output logic signal based on a high potential side power source from an input logic signal based on a low potential side power source, high speed operation and low consumption are achieved. It is an object of the present invention to provide a driver circuit that can achieve both electric power.

In order to solve the above problem, the present invention provides a driver circuit that generates an output logic signal based on a high potential side power source from an input logic signal based on a low potential side power source.
The driver circuit includes a level shift circuit including a driving circuit driven by the input logic signal, a first current control element in which a through current from the high-potential-side power source is controlled by the driving circuit, and the first A second current control element connected in a current mirror to the current control element, an output circuit comprising a pull-down circuit connected in series with the second current control element, and the first and second current control elements At a connection point between the first detection control circuit that detects a change in the control voltage common to the drive circuit and generates a first control signal to the drive circuit, and the pull-down circuit of the second current control element A second detection control circuit that detects a change in potential and generates a second control signal to the pull-down circuit, and is connected to the pull-down circuit by the input logic signal. When the first and second current control elements are complementarily turned on and off, the current flowing through the drive circuit is controlled based on the first control signal, and the pull-down is performed based on the second control signal. The current flowing through the circuit is controlled.

  According to the present invention, a driver that generates an output logic signal based on a high potential side power source from an input logic signal based on a low potential side power source and drives a semiconductor switching element connected to the high potential side power source on and off. High-speed circuit operation and low power consumption can be realized at the same time.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a driver circuit according to an embodiment of the present invention.
The driver circuit receives a logic signal X based on the low potential side power supply and generates a logic signal Y based on the high potential side power supply Vcc. The driver circuit includes a level shift circuit 10, an output circuit 20, The first detection control circuit 30 and the second detection control circuit 40 are configured.

  The level shift circuit 10 includes a P-channel transistor Q11 (first current control element) whose source terminal is connected to the high potential side power supply Vcc, and a drive circuit 11 that controls the drain current I1 of the transistor Q11. . The drive circuit 11 includes an N-channel transistor Q12 constituting a first current source having a large output current, and an N-channel transistor Q13 constituting a second current source having a source terminal grounded via a resistor R13. It is configured. The drain terminals of these transistors Q12 and Q13 are connected to the drain terminal and the gate terminal of the transistor Q11 through the connection point A in common. The gate terminal of the transistor Q12 is connected to an AND gate G1 to which a logic signal X and a control signal out1 from a first detection control circuit 30 described later are input, and an output signal X1 of the AND gate G1 is supplied. ing. Further, the logic signal X is supplied to the gate terminal of the transistor Q13.

  A parallel circuit of a resistor R1 and a Zener diode ZD1 is connected between the source terminal and the drain terminal of the transistor Q11. The gate terminal of the transistor Q11 is connected to the gate terminal of a P-channel transistor Q21 (second current control element) in the output circuit 20, which will be described later, to constitute a current mirror circuit.

The output circuit 20 includes a P-channel transistor Q21 whose source terminal is connected to the high-potential-side power supply Vcc, and a pull-down circuit 21 that controls the drain current I2 of the transistor Q21. The pull-down circuit 21 includes an N-channel transistor Q22 constituting a third current source having a large output current, and an N-channel transistor Q23 constituting a fourth current source whose source terminal is grounded via a resistor R23. It is composed of The drain terminals of these transistors Q22 and Q23 are connected to the drain terminal of the transistor Q21 through the connection point B in common. The gate terminal of the transistor Q22 is connected to an AND gate G2 to which the inverted logic signal X ^* and the control signal out2 from the second detection control circuit 40 are input, and the output signal X ^* 1 is output from the AND gate G2. Is supplied. Further, an inverted logic signal X ^* is supplied to the gate terminal of the transistor Q23.

  The drain terminal of the transistor Q21 is connected to the gate terminal of the P-channel transistor Q1 to be driven by the driver circuit, and a resistor R2 and a Zener diode ZD2 are connected between the source terminal and the drain terminal of the transistor Q21. A parallel circuit is connected.

The first detection control circuit 30 detects a change in control voltage common to the first and second current control elements, and generates a control signal out1 to the drive circuit 11, and includes a resistor R31, A P-channel transistor Q31 having a source terminal connected to the high potential side power supply Vcc via the resistor R31, a resistor R32 having one end connected to the drain terminal of the transistor Q31 and the other end grounded, and a parallel to the resistor R32 And an N-channel transistor Q32 having a drain terminal and a source terminal connected to each other. The gate terminal of the transistor Q31 is connected to the gate terminals of the transistors Q11 and Q21, and their gate potential is supplied as the set signal set1. Further, an inverted logic signal X ^* is supplied to the gate terminal of the transistor Q32. Thereby, the first detection control circuit 30 is reset when the inverted logic signal X ^* becomes H level.

  The second detection control circuit 40 detects a potential change at the connection point B between the transistor Q21 of the output circuit 20 and the pull-down circuit 21, and generates a control signal out2 to the pull-down circuit 21, and includes a resistor R41. A P-channel transistor Q41 having a source terminal connected to the high potential side power supply Vcc via the resistor R41, a resistor R42 having one end connected to the drain terminal of the transistor Q41 and the other end grounded, and the resistor R42 It is composed of an N-channel transistor Q42 having a drain terminal and a source terminal connected in parallel. The potential of the connection point B is supplied to the gate terminal of the transistor Q41 as the set signal set2. The logic signal X is supplied to the gate terminal of the transistor Q42. Thereby, the second detection control circuit 40 is reset when the logic signal X becomes H level.

Next, the operation of the driver circuit according to the embodiment of the present invention will be described.
FIG. 2 is a timing chart showing operation waveforms of each part of the driver circuit of FIG.
FIG. 4A shows the waveform of the logic signal X formed on the basis of the low-potential side power supply and input to this driver circuit, and FIG. 4B shows the waveform of the inverted logic signal X ^* . Show. Now, at the timing when the logic signal X becomes H level (hereinafter simply referred to as H) and the logic signal X ^* becomes L level (hereinafter simply referred to as L), the transistors Q12 and Q13 are turned on, and the transistors Q22 and Q23 are turned on. Turn off. Then, the drain current I1 of the transistor Q11 shown in FIG. 4C is the addition current Ip1 by the transistors Q12 and Q13. Since the logic signal X ^* is H and the transistor Q32 is conductive until just before that, when the logic signal X becomes H, the first detection control circuit 30 is in a reset state (its output). The control signal out1 is at the ground level).

  As a result, as shown in FIG. 2D, the voltage V1 at the connection point A starts to drop from the high potential side power supply Vcc. At this time, the drain current I2 of the transistor Q21 constituting the current mirror pair with the transistor Q11 has an n-fold current value (nIpl) equal to the size ratio of the transistor Q21 to the transistor Q11. Here, the size ratio n of the transistor Q21 with respect to the transistor Q11 is defined as the following equation (1).

(W / L) _Q21 = n (W / L) _Q11 (1)
However, W is a gate width and L is a gate length.
As a result, the voltage V2 at the connection point B is pulled up by the transistor Q21, and the transistor Q1 is turned off (see FIG. 2H).

  As shown in FIG. 2D, when the drain voltage V1 of the transistor Q11 reaches the set voltage of the first detection control circuit 30, the control signal out1 shown in FIG. The transistor Q12 is turned off by the output signal X1 from (see (f) of the figure). As a result, the drain current I1 of the transistor Q11 decreases to the level of the current Is1 generated only by the transistor Q13.

  At this time, since the gate voltage of the transistor Q31 is increased by the set signal set1, the transistor Q31 is turned off. However, if the resistor R32 is a high resistance, the time constant determined by the size of the capacitor Cp1 and the resistor R32 increases. Thus, the control signal out1 to the drive circuit 11 is kept at the H level.

  Here, it is assumed that the capacitor Cp1 is a parasitic capacitance value at the output terminal of the first detection control circuit 30, and the current Is1 is a minute current value that is necessary and sufficient to maintain the ON state of the transistor Q21. Further, the magnitude of the drain current I1 flowing through the transistor Q11 is expressed by the following equation (2).

I1 = (current flowing in Q12) + (current flowing in Q13) − (current flowing in resistor R1)
-(Current flowing through the Zener diode ZD1) (2)
Next, at the timing when the logic signal X becomes L and the logic signal X ^* becomes H, the transistors Q12 and Q13 are turned off, the transistors Q22 and Q23 are turned on, the drain current I1 of the transistor Q11, and the transistor Q11 and the current mirror pair are turned on. The drain current I2 of the transistor Q21 that constitutes each becomes zero. FIG. 2G shows a waveform of the drain current I3 flowing into the pull-down circuit 21. Since the logic signal X is H and the transistor Q42 is conductive until just before that, when the logic signal X ^* becomes H, the second detection control circuit 40 is in a reset state (its output). The control signal out2 is at the ground level).

As a result, in the pull-down circuit 21, the voltage V2 at the connection point B is pulled down from the high potential side power supply Vcc as shown in FIG. 2 (h) by the added current Ip3 of the transistors Q22 and Q23, and the transistor Q1 is turned on. Further, when the gate voltage V2 of the transistor Q1 reaches the set voltage of the second detection control circuit 40, the control signal out2 shown in FIG. 5 (i) becomes H, and the output signal X ^* 1 from the AND gate G2 The transistor Q22 is turned off (see (j) in the figure). As a result, the drain current I2 of the transistor Q21 is reduced to the level of the current Is3 by only the transistor Q23.

Here, the magnitude of the drain current I2 flowing through the transistor Q21 is expressed by the following equation (3).
I2 = (current flowing in Q22) + (current flowing in Q23) − (current flowing in resistor R2)
-(Current flowing through the Zener diode ZD2) (3)
Further, it is assumed that the current Is3 has a minute current value necessary and sufficient to maintain the on state of the transistor Q1. The Zener diodes ZD1 and ZD2 connected in parallel to the transistors Q11 and Q21 perform a protection function so that an overvoltage is not applied between the source and drain of the transistors Q11 and Q21.

  That is, if the Zener diode ZD1 is not provided, the voltage (Vcc−V1) becomes larger than the Zener voltage Vz of the Zener diode ZD1 by turning on the transistors Q12 and Q13, but is clamped by the Zener voltage Vz because of the Zener diode ZD1. Is done. When the transistor Q12 is turned off by the control signal out1, the gate-source voltage of the transistor Q11 decreases as the drain current I1 decreases. Therefore, the potential VI at the connection point A always increases without the Zener diode ZD1. .

  If the potential V1 at the connection point A when the transistor Q12 is turned off satisfies the relationship (Vcc−V1) <Vz, the potential V1 rises even if the Zener diode ZD1 is present. If (Vcc−V1)> Vz, the potential V1 remains (Vcc−Vz) and does not change. The signal waveform shown in FIG. 2 corresponds to the latter case.

  In the present invention, the magnitude relationship between the voltage (Vcc−V1) and the Zener voltage Vz may be either, and is not limited to either one. Further, the threshold voltage Vth for the set signal set to the first detection control circuit 30 needs to be set to a relationship of Vcc> Vth> (Vcc−Vz). However, in the signal waveform of FIG. 2, the control signal out1 is output to the drive circuit 11 when V1 = Vcc−Vz, but actually, the control signal out1 requires a margin.

The driver circuit described above is a driver circuit that receives a logic signal X based on the low-potential side power supply and generates a logic signal Y based on the high-potential side power supply Vcc. The pull-down circuit 21 includes an output circuit 20, a first detection control circuit 30, and a second detection control circuit 40. The pull-down circuit 21 is driven by a logic signal X input to the level shift circuit 10 and an inverted logic signal X ^* . And the P-channel transistors Q11 and Q21 constituting the current mirror pair are complementarily turned on and off, and the drain current I1 flowing through the drive circuit 11 is controlled based on the control signal out1 from the first detection control circuit 30. The drain current I2 flowing through the pull-down circuit 21 is controlled based on the control signal out2 from the second detection control circuit 40. That.

Therefore, the driver circuit of the present invention has the following advantages compared with the conventional driver circuit.
First, in the driver circuit according to the present invention, in the on / off operation of the series of transistors Q11 and Q21, the on / off timing of the pull-up transistor Q21 and the transistors Q22 and Q23 of the pull-down circuit 21 constituting the output circuit 20 It depends on the timing of the signal X and the inverted logic signal X ^* . Therefore, the simultaneous ON state of a plurality of transistors connected in series between the high potential side power supply and the ground as in the conventional circuit can be essentially avoided.

  Further, the drain current I1 flowing through the transistor Q11 of the current mirror pair constituting the level shift circuit 10 is small to a level that can be ignored as compared with the consumption current in the output circuit 20 by increasing the size ratio n with the transistor Q21. It is possible to design to a value.

  Further, the first detection control circuit 30 and the second detection control circuit 40 are used to detect the potentials of the connection points A and B, and the feedback is sent to the level shift circuit 10 and the output circuit 20, respectively. In addition, the potentials V1 and V2 at the connection points A and B can be transited at high speed during the turn-off period. Therefore, it is possible to design a driver circuit that achieves both high-speed operation and low power consumption by supplying a large current and switching to a very small current at the same time as the transition is completed.

It is a circuit diagram showing a driver circuit concerning an embodiment of the invention. FIG. 2 is a timing chart showing operation waveforms of respective parts of the driver circuit of FIG. 1. It is a circuit diagram which shows the conventional driver circuit. It is a circuit diagram which shows another example of the conventional driver circuit. FIG. 5 is a state transition diagram illustrating an on / off state of each transistor in FIG. 4.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Level shift circuit 11 Drive circuit 20 Output circuit 21 Pull-down circuit 30 1st detection control circuit 40 2nd detection control circuit out1 Control signal (1st control signal)
out2 control signal (second control signal)
Q11 P-channel transistor (first current control element)
Q21 P-channel transistor (second current control element)
Q12 N-channel transistor (first current source)
Q13 N-channel transistor (second current source)
Q31, Q41 P-channel transistor Q32, Q42 N-channel transistor Q22 N-channel transistor (third current source)
Q23 N-channel transistor (fourth current source)
R31, R32, R41, R42 Resistor Vcc High potential side power supply X, Y Logic signal

Claims (5)

In a driver circuit that generates an output logic signal based on a high potential power supply from an input logic signal based on a low potential power supply,
A level shift circuit including a drive circuit driven by the input logic signal, and a first current control element in which a through current from the high-potential-side power source is controlled by the drive circuit;
An output circuit comprising a second current control element connected in a current mirror to the first current control element, and a pull-down circuit connected in series with the second current control element;
A first detection control circuit that detects a change in a control voltage common to the first and second current control elements and generates a first control signal to the drive circuit;
A second detection control circuit that detects a potential change at a connection point of the second current control element with the pull-down circuit and generates a second control signal to the pull-down circuit;
With
When the pull-down circuit and the first and second current control elements are complementarily turned on and off by the input logic signal, the current flowing through the drive circuit is controlled based on the first control signal, and the first A driver circuit characterized in that a current flowing through the pull-down circuit is controlled based on a control signal (2). The drive circuit is configured by connecting in parallel a first current source having a large output current and a second current source having a small output current,
The first detection control circuit outputs the first control signal and immediately turns off the first current source when the first and second current control elements are turned on. The driver circuit according to claim 1. The first detection control circuit includes:
A first resistor;
A first P-channel MOSFET having a source terminal connected to the high-potential-side power supply via the first resistor;
A second resistor having one end connected to the drain terminal of the first P-channel MOSFET and the other end connected to the ground;
A drain terminal and a source terminal connected in parallel with the second resistor, a first N-channel MOSFET that is inverted and supplied to the gate terminal;
Consisting of
A control voltage common to the first and second current control elements is supplied to the gate terminal of the first P-channel MOSFET, and the first control signal is output according to the voltage across the second resistor. 3. The driver circuit according to claim 2, wherein the first control signal is reset by inverting and supplying the input logic signal to a gate terminal of the first N-channel MOSFET. The pull-down circuit is configured by connecting in parallel a third current source having a large output current and a fourth current source having a small output current,
The second detection control circuit outputs the second control signal and outputs the third current source when a potential at a connection point between the second current control element and the pull-down circuit becomes a low level. 2. The driver circuit according to claim 1, wherein the driver circuit is immediately turned off. The second detection control circuit includes:
A third resistor;
A second P-channel MOSFET having a source terminal connected to the high-potential-side power supply via the third resistor;
A fourth resistor having one end connected to the drain terminal of the second P-channel MOSFET and the other end connected to the ground;
A second N-channel MOSFET having a drain terminal and a source terminal connected in parallel with the fourth resistor and the input logic signal being supplied to a gate terminal;
Consisting of
A potential at a connection point between the second current control element and the pull-down circuit is supplied to a gate terminal of the second P-channel MOSFET, and the second control signal according to a voltage across the fourth resistor. 5. The driver circuit according to claim 4, wherein the second control signal is reset by supplying the input logic signal to a gate terminal of the second N-channel MOSFET.

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