CN104022121A - Three-dimensional semiconductor device and manufacturing method thereof - Google Patents

Three-dimensional semiconductor device and manufacturing method thereof Download PDF

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CN104022121A
CN104022121A CN201410284777.5A CN201410284777A CN104022121A CN 104022121 A CN104022121 A CN 104022121A CN 201410284777 A CN201410284777 A CN 201410284777A CN 104022121 A CN104022121 A CN 104022121A
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layer
substrate
drain electrode
etching
channel layer
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CN104022121B (en
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霍宗亮
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201410284777.5A priority Critical patent/CN104022121B/en
Priority to US15/321,037 priority patent/US20170154895A1/en
Priority to PCT/CN2014/081923 priority patent/WO2015196515A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Abstract

The invention discloses a three-dimensional semiconductor device comprising a plurality of memory unit transistors and a plurality of selection transistors, wherein the plurality of memory unit transistors are at least partially overlapped in the vertical direction; each selection transistor comprises a first drain electrode distributed along the vertical direction, an active region, a common source electrode formed in a substrate and a metal grid electrode distributed around the active region; each memory unit transistor comprises a channel layer distributed vertical to the surface of the substrate, wherein a plurality of interlayer insulating layers and a plurality of grid electrode stacking structures are alternately stacked along the side wall of the channel layer, and a second drain electrode is located at the top of the channel layer; the channel layer is electrically connected with the first drain electrode. According to the three-dimensional semiconductor device and a manufacturing method thereof disclosed by the invention, multi-grid MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) are formed below memory unit string stacks comprising vertical channels so as to be used as the selection transistors, thus the threshold voltage control characteristic of the grid electrode is improved, the off-state leakage current is reduced, the over-etching for the substrate is avoided, and the reliability of the device is effectively improved.

Description

Three-dimensional semiconductor device and manufacture method thereof
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, particularly relate to a kind of 3 D semiconductor memory device and manufacture method thereof.
Background technology
In order to improve the density of memory device, industry has extensively been devoted to the method for the size of researching and developing the memory cell that reduces two-dimensional arrangement.Along with the memory cell dimensions of two dimension (2D) memory device continues reduction, signal conflict and interference can enlarge markedly, to such an extent as to are difficult to carry out multi-level-cell (MLC) operation.In order to overcome the restriction of 2D memory device, industry been has has been researched and developed the memory device with three-dimensional (3D) structure, improves integration density by memory cell is dimensionally arranged on substrate.
Industry at present a kind of conventional 3D memory device structures is array of bit cells transistor (TCAT) too.Particularly, deposit multilayer laminated construction (multiple ONO structures that for example oxide and nitride replace) on substrate first; By anisotropic etching technics to multilayer laminated structure etching on substrate form along memory cell word line (WL) bearing of trend distribute, perpendicular to multiple raceway groove through holes of substrate surface (can go directly substrate surface or there is certain over etching); In raceway groove through hole, the material such as deposit spathic silicon forms column raceway groove; Form the groove of through substrate along the multilayer laminated structure of WL direction etching, expose and be enclosed in around multilayer laminated of column raceway groove; Optional, the first kind material in wet method sideetching lamination, in the lateral groove of first kind material side formation certain depth, in this lateral groove, filling agent is used as the floating boom utmost point for the material of charge storage; Wet method is removed the Second Type material (for example hot phosphoric acid is removed silicon nitride, or HF removes silica) in lamination, leaves the raised structures of cross direction profiles around column raceway groove; The side wall deposition gate dielectric layer of raised structures in groove (such as high K medium material) and grid conducting layer (such as Ti, W, Cu, Mo etc.) form gate stack; Perpendicular magnetic anisotropy etching is removed the gate stack outside raised sides plane, until expose the gate dielectric layer of projection side; Etching laminated construction forms source drain contact and completes back end fabrication.Now, a part of projection that laminated construction stays in column trench sidewalls has formed the separator between gate electrode, and the gate stack staying is folded between multiple separators as control electrode.In the time applying voltage to grid, the fringe field of grid can make induction in the column trench sidewalls of for example polycrystalline silicon material form source-drain area, forms thus the gate array that multiple series-parallel MOSFET form and records stored logic state.Wherein, for multiple cellular zone connection in series-parallel MOSFET signals are drawn, fill polycrystalline silicon material in column raceway groove top deposition and form drain region, and the Metal Contact plug that formation is electrically connected with drain region is to be further electrically connected to the bit line (bit-line, BL) of top.In addition, between multiple vertical column raceway grooves, in substrate, form the shared source region with Metal-silicides Contact.Under cell conduction state, electric current flows to vertical channel region around from sharing source region, and multiple source-drain areas that in being upward through vertical-channel under the control voltage effect applying at control grid (WL is connected with word line), induction generates, the bit line above further flowing to by the drain region at raceway groove top.
Although this TCAT device architecture have body wipe (change control grid can cause induction source drain region and floating boom extremely in potential change, can bulk erase), metal gates (thereby can more conveniently regulate transistor threshold by controlling metal material control work function), but be all disposable etching, deposition shape owing to selecting transistor (being positioned at memory transistor unit strings top or below) and memory cell, therefore be difficult to accurate adjustment and select transistorized threshold value, be difficult to meet the application demand of some high driveability.In addition, also there is the problem of over etching while forming vertical-channel and common source in this structure, has reduced device reliability.
Another kind of conventional device architecture is for example to adopt position cost can reduce the enable nand gate of (BiCS), on substrate, improve integration density by memory cell is dimensionally arranged in, wherein channel layer stands vertically on substrate, grid is divided into selection grid, the control grid in middle level and selection grid three parts on upper strata of lower floor, by signal being distributed in three groups of gate electrodes to reduce crosstalking between signal.Particularly, the device of the upper and lower is with electing transistor---the vertical MOSFET that gate height/thickness is larger, and gate dielectric layer is the conventional high k material of individual layer; The device in middle level is as memory cell string, and gate height/thickness is less, and gate dielectric layer is the stacked structure on tunnel layer, accumulation layer, barrier layer.
The concrete manufacturing process of above-mentioned device generally comprises, on silicon substrate, deposit lower floor and select gate electrode layer, the contact of drawing with the lower part of deposition channel layer and lower-layer gate electrode of hole slot that gate electrode layer forms through substrate is selected by etching lower floor, deposition is controlled grid layer up, etching control grid layer forms the contact of drawing as the intermediate channel district of memory cell area and middle level control grid electrode, etching formation control grid, according to word line, bit line is divided need to be divided into multiple regions by whole device, on deposit upper strata and select grid etching, deposition forms top raceway groove and contact is drawn on upper strata, adopt afterwards subsequent technique to complete the manufacture of device.In this technical process, the most key etch step be only for memory channel region, intermediate layer with draw the photoetching contacting, this has directly determined integrated level and the signal antijamming capability of whole device.
But, although BiCS structure is utilized and controlled gate threshold respectively with selecting transistor stack to place by storage array, can only wipe by gate induced drain leakage electric current (GIDL), cannot carry out body to wipe, read-write efficiency is lower.
Summary of the invention
From the above mentioned, the object of the invention is to overcome above-mentioned technical difficulty, propose a kind of novelty 3 D semiconductor memory device manufacture method.
For this reason, the invention provides a kind of three-dimensional semiconductor device, comprise in vertical direction overlapping at least in part multiple memory cell transistors and multiple selection transistor, wherein, each the first drain electrode, active area of selecting transistor to comprise vertically to distribute, be formed on the common-source in substrate, and be distributed in active area metal gates around; Wherein, each memory cell transistor comprises the channel layer distributing perpendicular to substrate surface, and multiple interlayer insulating films and multiple gate stack structure are alternately laminated along the sidewall of described channel layer, and the second drain electrode is positioned at the top of described channel layer; Wherein, described channel layer is electrically connected with described the first drain electrode.
Wherein, described metal gates is multi-grid structure or annular grid electrode structure.
Wherein, the lateral dimension of described the first drain electrode is more than or equal to the lateral dimension of described channel layer.
Wherein, each selects transistor to comprise gate insulator, and described gate insulator has surrounded bottom and the sidewall of described metal gates.
Wherein, each of multiple gate stack structures comprises the gate dielectric layer being made up of tunnel layer, accumulation layer, barrier layer.
The manufacture method that the invention also discloses a kind of three-dimensional semiconductor device, comprises step: on substrate, form and select transistorized active area; Around active area, form and select transistorized metal gates; At the stacked structure of selecting to form on transistor the first material layer and the second material layer; Etching stacked structure forms vertical multiple hole slots; In each hole slot, form the channel layer of memory cell transistor; Selective removal the second material layer leaves multiple transverse concave grooves between the first material layer; In multiple transverse concave grooves, form multiple gate stack structures.
Wherein, the step that is formed with source region comprises:
A) etched substrate forms multiple active areas of vertical distribution; Or
B) on substrate, form the mask stack of the first mask layer and the second mask layer, the stacking formation through hole of etching mask, in through hole, deposition is formed with source region.
Wherein, further comprise:
A1) after forming metal gates, form interlayer dielectric layer on substrate, etching interlayer dielectric layer forms the opening that exposes active area, forms the first drain electrode in opening; Or
B1) before forming metal gates, form the opening that exposes active layer at mask stack top, in opening, form the first drain electrode.
Wherein, the lateral dimension of described the first drain electrode exposes the lateral dimension of the opening of active layer described in being more than or equal to.
Wherein, each of multiple gate stack structures comprises the gate dielectric layer being made up of tunnel layer, accumulation layer, barrier layer.
According to 3 D semiconductor memory device of the present invention and manufacture method thereof, below the memory cell string that comprises vertical-channel is stacking, form multiple-grid MOSFET with the transistor that elects, improve threshold voltage of the grid control characteristic, reduced off-state leakage current, avoid, to substrate over etching, effectively having improved device reliability.
Brief description of the drawings
Describe technical scheme of the present invention in detail referring to accompanying drawing, wherein:
Fig. 1 to Figure 16 is the cutaway view according to each step of the 3 D semiconductor memory device manufacture method of first embodiment of the invention; And
Figure 17 to Figure 25 is the cutaway view according to each step of the 3 D semiconductor memory device manufacture method of second embodiment of the invention.
Embodiment
Also describe feature and the technique effect thereof of technical solution of the present invention referring to accompanying drawing in conjunction with schematic embodiment in detail, disclose semiconductor storage unit and the manufacture method thereof of effective raising grid control performance and device reliability.It is pointed out that structure like similar Reference numeral representation class, term " first " used in the application, " second ", " on ", D score etc. can be used for modifying various device architectures or manufacturing process.These modify the space, order or the hierarchical relationship that not imply unless stated otherwise institute's modification device architecture or manufacturing process.
Fig. 1 to Figure 16 shows according to grid technique before the employing of embodiment 1 and forms the selection transistor of multiple-grid and form the cutaway view of each step of method of storage crystal pipe string thereon.
As shown in Figure 1, provide substrate 1.Substrate 1 material can comprise body silicon (bulk Si), body germanium (bulk Ge), silicon-on-insulator (SOI), germanium on insulator (GeOI) or other compound semiconductor substrate, for example SiGe, SiC, GaN, GaAs, InP etc., and the combination of these materials.For with existing IC manufacturing process compatibility, substrate 1 is preferably the substrate of siliceous material, such as Si, SOI, SiGe, Si:C etc.Preferably, substrate 1 is carried out to doping to form the well region (not shown) of n or p-type, to use the transistorized well region that comprises channel region that elects.
Optional, as shown in Figure 2, on substrate 1, form hard mask layer 2.Adopt the various techniques such as PECVD, LPCVD, HDPCVD, MOCVD, MBE, ALD, thermal oxidation, evaporation, sputter, form hard mask layer 2 at substrate 1 top, its material such as silicon nitride, silica, silicon oxynitride, amorphous carbon etc. and substrate 1 material have the material (for example etching selection ratio is greater than 5:1, is even greater than 10:1) of larger Etch selectivity.
As shown in Figure 3, taking hard mask layer 2 as mask, etched substrate 1 is formed with source region 1A.Optional, on hard mask layer 2, apply photoresist layer (not shown), and adopt the techniques such as exposure imaging to form photoetching agent pattern.Preferably, taking photoetching agent pattern as mask, adopt anisotropic dry etch, for example Ar dry plasma etch or employing are the reactive ion etching (RIE) of master's etching gas containing C, F, first etch hardmask layer 2 forms hard mask graph 2P, adjust subsequently etching technics parameter and make it faster for substrate 1 etch rate, etching has formed multiple active area 1A and has selected transistorized active area for the multiple-grid that forms below, has multiple groove 1T between the 1A of active area.Active area 1A is from substrate 1 top surface multiple column structures of projection vertically upward, and its cross sectional shape can be rectangle, square, rhombus, circle, semicircle, ellipse, triangle, pentagon, pentagon, hexagon, octagon etc. various geometries.
As shown in Figure 4, formed first grid insulating barrier 3 in substrate 1 end face, 1A side, active area.Can adopt the techniques such as PECVD, LPCVD, HDPCVD, MOCVD, MBE, ALD, thermal oxidation, the dielectric of cvd silicon oxide, silicon nitride, silicon oxynitride or other high k materials is to select transistorized gate insulator 3 as multiple-grid.Wherein high k material includes but not limited to that nitride (for example SiN, AlN, TiN), metal oxide (are mainly subgroup and lanthanide element oxide, for example MgO, Al 2o 3, Ta 2o 5, TiO 2, ZnO, ZrO 2, HfO 2, CeO 2, Y 2o 3, La 2o 3), nitrogen oxide (as HfSiON), Perovskite Phase oxide (for example PbZr xti 1-xo 3(PZT), Ba xsr 1-xtiO 3(BST)) etc.
As shown in Figure 5, formed in 1A side, active area and selected transistorized multiple first grid electrode 4 and the side wall 5 in first grid electrode 4 sides.First, etching gate insulation layer 3 leaves vertical Part I and on substrate 1 end face, leaves the Part II of shorter level on the sidewall of active area 1A.By methods such as PECVD, HDPCVD, MBE, ALD, sputter, plating, chemical platings, on gate insulation layer 3, formed multiple first grid electrodes 4 of metal material, also in the side of gate insulation layer 3 Part I and the end face of Part II formed metal gates 4.Metal gates 4 materials can comprise metal simple-substance or the alloy of these metals and the nitride of these metals such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, thereby can further accurately control and select transistorized threshold voltage with regulatory work function doped with elements such as C, F, N, O, B, P, As in addition.The barrier layer (not shown) that also preferably forms nitride between metal gate electrode 4 and gate insulator 3 by conventional methods such as PVD, CVD, ALD, barrier layer material is M xn y, M xsi yn z, M xal yn z, M aal xsi yn z, wherein M is Ta, Ti, Hf, Zr, Mo, W or other element.After this, the grid 4 first deposition of insulative material in sides then isotropic etching formed grid curb wall 5.As shown in Figure 5, grid 4 is formed at least both sides of active area 1A also can think double-gate structure, but in other embodiments, grid 4 is actual can be surrounded with source region 1A and form gate-all-around structure, or be the multiple grids (its number for example 3,4,6,8 etc.) that distribute around active area 1A, so can make in the 1A of active area Electric Field Distribution more accurately controlled, select transistorized performance thereby improved.In addition, in Fig. 5, metal gates 4 height will be lower than active area 1A, and this is to select transistorized drain region facility for follow-up formation.Nature, metal gates 4 highly also can flush with active area 1A.
As shown in Figure 6, in the substrate 1 exposing at groove 1T, form shared source region 1S.Can form source region 1S by ion implantation doping, and preferably further form metal silicide (not shown) on surface to reduce contact resistance.Metal silicide is NiSi such as 2-y, Ni 1-xpt xsi 2-y, CoSi 2-yor Ni 1-xco xsi 2-y, wherein x is all greater than 0 and is less than 1, y and is all more than or equal to 0 and is less than 1.In this process; because being formed in the top draining on the 1A of active area, the vertical-channel of follow-up storage crystal pipe string make substrate be subject to drain electrode protection; while substrate in being etched with source region process shown in Fig. 3 is before subject to the protection of hard mask layer 2; therefore there is not the problem of over etching substrate 1; reduce blemish, improved channel region performance, thereby improved the device reliability of selecting transistor and memory transistor.
As shown in Figure 7, on device, form the first interlayer dielectric layer (ILD) 6.By techniques such as spin coating, printing, sprayings, form the ILD6 of low-k materials, low-k materials includes but not limited to the organic low-k materials organic polymer of aryl or polynary ring (for example containing), inorganic low-k materials (for example amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silex glass, BSG, PSG, BPSG), porous low k material (for example two silicon three oxygen alkane (SSQ) hole, Quito low-k materials, porous silica, porous SiOCH, mix C silicon dioxide, mix F porous amorphous carbon, porous diamond, porous organo polysilica compound).Preferably, adopt CMP, return the technique planarization ILD6 such as quarter until expose hard mask graph 2P.
As shown in Figure 8, remove hard mask graph 2P, in ILD6, leave groove 6T.For hard mask layer figure 2P material, can select suitable wet etching liquid, for example hot phosphoric acid is removed the 2P of silicon nitride material, or select suitable dry removal processes, for example oxygen plasma dry etching is to remove the 2P (the method can effectively improve cleanliness factor that etching removes, avoid rete 2P residual, can adopt subsequently HF base corrosive liquid to clean to remove primary silicon oxide film) of amorphous carbon material.Preferably, increase side direction etch rate or select suitable etching mask, making the width of groove 6T be greater than the width of active area 1A.Preferably, groove 6T transverse width is at least greater than 1.5 times of top vertical-channel layer transverse width, and preferably 2～4 times.
As shown in Figure 9, in groove 6T, fill and form the transistorized drain region 1D of selection.Adopt MBE, ALD homepitaxy technique, or the depositing operations such as PECVD, HDPCVD, MOCVD, in groove 6T, filling semiconductor material forms drain region 1D, and its material can be identical or close with active area 1A, substrate 1, for example Si (polycrystalline or monocrystalline), SiGe, Si:C.Preferably, deposition, epitaxy technique adopt in-situ doped simultaneously, also pass into the unstripped gass such as SiH4 and also pass into the gas containing dopant atom such as borine, phosphine simultaneously, have formed thus n+ or the p+ type drain region 1D of doping.In addition,, after also can having deposited, select the techniques such as Implantation to form doped drain.As shown in Figure 8 and described in, thereby the width of groove 6T is greater than the width that width that the width of active area 1A makes drain region 1D is greater than active area 1A, can make to select transistorized drain region area to increase, avoided causing due to etching mask torsional deformation form memory transistor above selecting transistor time vertical channel region dislocation, memory transistor and below select transistorized mismatch (mismatch) problem.
As shown in figure 10, on whole device, (being also on the top of drain region 1D and ILD6) alternately forms the stacked structure 7 of the first material layer 7A and the second material layer 7B.The combination that is selected from following material of stacked structure 7 and at least comprise a kind of dielectric: as silica, silicon nitride, amorphous carbon, diamond like carbon amorphous carbon (DLC), germanium oxide, aluminium oxide, etc. and combination.The first material layer 7A has the first Etch selectivity, and the second material layer 7B has the second Etch selectivity and is different from the first Etch selectivity.In a preferred embodiment of the invention, laminated construction 7A/7B is insulating material, for example silica of combination and combination, silica and the polysilicon of silicon nitride or combination, silica or the silicon nitride of amorphous silicon and combination of amorphous carbon etc. of layer 7A/ layer 7B.In another preferred embodiment of the present invention, layer 7A and layer 7B have larger etching selection ratio (being for example greater than 5:1) in wet etching condition or under oxygen plasma dry etching condition.The deposition process of layer 7A, layer 7B comprises the various techniques such as PECVD, LPCVD, HDPCVD, MOCVD, MBE, ALD, thermal oxidation, evaporation, sputter.
As shown in figure 11, etching stacked structure 7 until expose substrate drain region 1D, forms the hole slot 7T of vertical break-through stacked structure for the vertical channel region of definition storage crystal pipe string.Preferably, adopt the stacked structure 7 of RIE or dry plasma etch anisotropic etching layer 7A/ layer 7B, expose drain region 1D with and submit the sidewall for stacking layer 7A/ layer 7B.More preferably, the process conditions of control anisotropic etching stacked structure 7 obtain vertical deep hole or the deep trouth 7T of high-aspect-ratio (for example depth-to-width ratio AR is more than or equal to 10:1) to make lateral etching speed significantly be less than longitudinal etching speed.Be parallel to substrate 1 surface cut the cross sectional shape of hole slot 7TP can be rectangle, square, rhombus, circle, semicircle, ellipse, triangle, pentagon, pentagon, hexagon, octagon etc. various geometries.
As shown in figure 12, in hole slot 7T, form vertical-channel layer 8.The material of channel layer 8 can comprise the semi-conducting materials such as monocrystalline silicon, amorphous silicon, polysilicon, microcrystal silicon, monocrystalline germanium, SiGe, Si:C, SiGe:C, SiGe:H, and depositing operation is described above.In an embodiment shown in Figure 12 of the present invention, the depositional mode of channel layer 8 is the hollow cylindrical that local sidewall of filling hole slot 7T is formed as having air-gap.In other not shown embodiment of the present invention, select the depositional mode of vertical-channel layer 8 with the complete or local hole slot 7T that fills, form the core-shell mechanism of filling insulating barrier (not shown) in solid post, cavity ring or cavity ring.The shape of the horizontal cross-section of channel layer 8 and hole slot 7T are similar and preferably conformal, can be solid rectangle, square, rhombus, circle, semicircle, ellipse, triangle, pentagon, pentagon, hexagon, octagon etc. various geometries, or be above-mentioned geometry the develop hollow ring-type, the barrel-like structure (and insulating barrier can be filled in its inside) that obtain.The below part of vertical-channel layer 8 is as the source electrode 8S of memory cell transistor.
As shown in figure 13, form the drain region 8D of storage string.Preferably, for hollow column channel layer 8 structures, can further fill dielectric isolation layer 9 in channel layer 8 inner sides, for example, form the layer 9 of for example silica material by techniques such as LPCVD, PECVD, HDPCVD, for supporting, insulating and isolation channel layer 8.After this, at channel layer 8 deposition drain region, top 8D.Preferably, adopt (for example with Si close material SiGe, SiC etc. identical or close with channel layer 8 materials, so that fine setting lattice constant and improve carrier mobility, thereby the driveability of control unit device) material be deposited on the top of hole slot 7T and form the transistorized drain region 8D of memory device unit.Nature, if from different shown in Figure 13, channel layer 8 be the solid construction of filling completely, channel layer 8 forms corresponding drain region 8D and without extra drain region deposition step in the part of whole top device.
As shown in figure 14, selective etch is to remove the second material layer 7B, select transistor (particularly, exposing ILD6 and drain electrode 1D) until expose, selecting to leave the discrete vertical stratification being formed by the first material layer 7A, channel layer 8, dielectric isolation layer 9 on transistorized ILD6.According to the material difference of layer 7A/ layer 7B, can selective wet etching liquid remove a layer 7B with etching isotropically.Particularly, for layer 7B material, take HF base corrosive liquid for silica material, adopt hot phosphoric acid corrosion liquid for silicon nitride material, adopt the alkali corrosion liquid such as KOH or TMAH for polysilicon or amorphous silicon material.Can also select oxygen plasma dry etching for the layer 7B of the carbon back such as amorphous carbon, DLC material in addition, make O react formation gas with C and extract out.Further, adopt anisotropic dry etch process, such as dry plasma etch, RIE etc., the first material layer 7A staying along word line WL bearing of trend etching, forms the belt structure along WL direction.After removing layer 7B, laterally multiple grooves of (being parallel to the horizontal direction of substrate surface) between multiple the first material layer 7A, are left, for formation control electrode after a while.It should be noted that, in one embodiment of the invention, as shown in figure 14, for selective etch is better removed horizontal layer 7B, can first adopt anisotropic etching technics to form the multiple vertical openings or the groove (not marking font size in figure) that expose ILD6, start sideetching to remove horizontal layer 7B completely from the sidewall of vertical openings or groove subsequently.
As shown in figure 15, among transverse concave groove, form the gate dielectric layer stacked structure 10 of memory transistor.Deposition process comprises PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputter etc.Not shown, layer 10 preferably further comprises multiple sublayers, for example tunnel layer, accumulation layer, barrier layer.Wherein tunnel layer comprises SiO 2or high k material, wherein high k material includes but not limited to that nitride (for example SiN, AlN, TiN), metal oxide (are mainly subgroup and lanthanide element oxide, for example MgO, Al 2o 3, Ta 2o 5, TiO 2, ZnO, ZrO 2, HfO 2, CeO 2, Y 2o 3, La 2o 3), nitrogen oxide (as HfSiON), Perovskite Phase oxide (for example PbZr xti 1-xo 3(PZT), Ba xsr 1-xtiO 3(BST)) etc., tunnel layer can be single layer structure or the multiple-level stack structure of above-mentioned material.Accumulation layer is the dielectric material with electric charge capture ability, and such as SiN, HfO, ZrO etc. and combination thereof, can be single layer structure or the multiple-level stack structure of above-mentioned material equally.Barrier layer can be single layer structure or the multiple-level stack structure of the dielectric materials such as silica, aluminium oxide, hafnium oxide.In one embodiment of the invention, gate dielectric layer stacked structure 10 is for example the ONO structure of silica, silicon nitride, silica composition.Then, deposition is filled and is formed grid conducting layer 11.Grid conducting layer 11 can be polysilicon, poly-SiGe or metal, wherein metal can comprise metal simple-substance or the alloy of these metals and the nitride of these metals such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, also can be doped with elements such as C, F, N, O, B, P, As with regulatory work function in grid conducting layer 11.The barrier layer (not shown) that also preferably forms nitride between gate dielectric layer 10 and grid conducting layer 11 by conventional methods such as PVD, CVD, ALD, barrier layer material is M xn y, M xsi yn z, M xal yn z, M aal xsi yn z, wherein M is Ta, Ti, Hf, Zr, Mo, W or other element.Similarly, layer 11 can be that single layer structure can be also multiple-level stack structure.Now, the first upper and lower material layer 7A of multiple grid conducting layers 11 is the dielectric material of insulation, has therefore formed the dielectric isolation layer between grid conducting layer 11.
As shown in figure 16, on whole device, form the second interlayer dielectric layer (ILD) 13.The formation technique of ILD13 and material and ILD6 are similar.Preferably, adopt CMP, return the method planarization ILD13 such as quarter until expose the first material layer 7A.
In addition, can also further adopt method as shown in Figures 1 to 9, above the vertical-channel 8 of storage string, further form the selection transistor (not shown) on upper strata to form BiCS structure.But according to the step of first embodiment of the invention, the three-dimension device structure forming as shown in figure 16, comprise in vertical direction overlapping at least in part multiple memory cell transistors and multiple selection transistor, wherein each selects transistor to comprise the first drain electrode 1D, active area 1A (being included near the first channel layer on the side of metal gates 4), the common-source 1S of vertically distribution, and being distributed in active area metal gates 4 around, metal gates 4 can be that multi-grid structure (preferably symmetrical) can be also annular grid electrode structure; Each memory cell transistor comprises the channel layer 8 distributing perpendicular to substrate surface, and multiple interlayer insulating film 7A and multiple gate stack structure 10/11 are alternately laminated along the sidewall of described channel layer 8, and the second drain electrode 8D is positioned at the top of described channel layer 8.Wherein, gate stack structure comprises gate dielectric layer 10 and grid conducting layer 11, and gate dielectric layer 10 further comprises tunnel layer, accumulation layer, barrier layer, and gate dielectric layer 10 has surrounded bottom and the sidewall of grid conducting layer 11.Other concrete layouts and material behavior, formation technique are described above.
Figure 17 to Figure 24 shows according to grid technique after the employing of embodiment 2 and forms the selection transistor of multiple-grid and form the cutaway view of each step of method of storage crystal pipe string thereon.
As shown in figure 17, provide foregoing substrate 1.Preferably, in foregoing substrate 1, form bit line 1BL, can form highly doped low-resistance bit line 1BL by Implantation, for example n+ doping.Bit line 1BL has played the effect of common-source 1S in Fig. 1 to Figure 16.
As shown in figure 18, on substrate 1, alternately form the stacked structure 2 of the first mask layer 2A and the second mask layer 2B.The combination that is selected from following material of stacked structure 2 and at least comprise a kind of dielectric: as silica, silicon nitride, amorphous carbon, diamond like carbon amorphous carbon (DLC), germanium oxide, aluminium oxide, etc. and combination.The first mask layer 2A has the first Etch selectivity, and the second mask layer 2B has the second Etch selectivity and is different from the first Etch selectivity.In a preferred embodiment of the invention, laminated construction 2A/2B is insulating material, for example silica of combination and combination, silica and the polysilicon of silicon nitride or combination, silica or the silicon nitride of amorphous silicon and combination of amorphous carbon etc. of layer 2A/ layer 2B.In another preferred embodiment of the present invention, layer 2A and layer 2B have larger etching selection ratio (being for example greater than 5:1) in wet etching condition or under oxygen plasma dry etching condition.The deposition process of layer 2A, layer 2B comprises the various techniques such as PECVD, LPCVD, HDPCVD, MOCVD, MBE, ALD, thermal oxidation, evaporation, sputter.In a preferred embodiment of the invention, a layer 2A is two, and a layer 2B is one, and layer 2B thickness is greater than a layer 2A thickness (for example layer 2B thickness is more than or equal to 2 times of layer 2A thickness, and preferably 10～100nm).
As shown in figure 19, etching stacked structure 2, forms until expose the through hole 2T of substrate 1 (1BL on surface).The preferred anisotropic dry etch of etching, for example, adopt dry plasma etch or the RIE of the fluorine-based etching gas of carbon.
As shown in figure 20, in through hole 2T, form the transistorized active area 1A of foregoing selection.For example, by extension or CVD deposition process, form the active area 1A identical or close with substrate 1 material, for example monocrystalline or polycrystalline Si.Further preferably, with Fig. 8,9 similar, can expand through hole 2T top width so that form wider drain electrode 1D.
As shown in figure 21, selective removal the second mask layer 2B has left horizontal groove 2R between the first mask layer 2A.Etching can be wet etching, for example, adopt hot phosphoric acid for silicon nitride material, or HF base corrosive liquid is for silica material; Also can be isotropic dry etching, for example oxygen plasma etch be for the layer 2B of amorphous carbon material.After this, etching definition word line regions, also by etching control the transverse width of remaining layer 2A.
As shown in figure 22, in horizontal groove 2R, fill and form the transistorized gate insulator 3 of selection and metal gates 4 and optional grid curb wall 5.Layer 3,4 material and technique are all as described in Example 1.Preferably, return and carve (etch-back) or the vertical etching of anisotropy, until the sidewall of exposed surface 2A.Identical with Fig. 6, metal gates 4 is also double grid or around multi-gate structure.
As shown in figure 23, similar with Fig. 9, deposition and ILD layer 6 similar in embodiment 1 on whole device, and preferably planarization until expose the 1D that drains.
As shown in figure 24, similar with Figure 10, on whole device, deposit the stacked structure 7 that the first material layer 7A and the second material layer 7B form, to form follow-up BiCS structure.After this step is similar to Figure 11 to Figure 16, repeats no more.
As shown in figure 25, in the device architecture in the end forming, similar with Figure 16, the three-dimension device structure forming as shown in figure 16, comprise in vertical direction overlapping at least in part multiple memory cell transistors and multiple selection transistor, wherein each selects transistor to comprise the first drain electrode 1D of vertically distribution, active area 1A (being included near the first channel layer on the side of metal gates 4), common-source 1S, and be distributed in active area metal gates 4 around, metal gates 4 can be that multi-grid structure (preferably symmetrical) can be also annular grid electrode structure, each memory cell transistor comprises the channel layer 8 distributing perpendicular to substrate surface, and multiple interlayer insulating film 7A and multiple gate stack structure 10/11 are alternately laminated along the sidewall of described channel layer 8, and the second drain electrode 8D is positioned at the top of described channel layer 8.Wherein, gate stack structure comprises gate dielectric layer 10 and grid conducting layer 11, and gate dielectric layer 10 further comprises tunnel layer, accumulation layer, barrier layer, and gate dielectric layer 10 has surrounded bottom and the sidewall of grid conducting layer 11.Other concrete layouts and material behavior, formation technique are described above.
According to 3 D semiconductor memory device of the present invention and manufacture method thereof, below the memory cell string that comprises vertical-channel is stacking, form multiple-grid MOSFET with the transistor that elects, improve threshold voltage of the grid control characteristic, reduced off-state leakage current, avoid, to substrate over etching, effectively having improved device reliability.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know without departing from the scope of the invention device architecture or method flow are made to various suitable changes and equivalents.In addition, can make and manyly may be suitable for the amendment of particular condition or material and not depart from the scope of the invention by disclosed instruction.Therefore, object of the present invention does not lie in and is limited to as the disclosed specific embodiment for realizing preferred forms of the present invention, and disclosed device architecture and manufacture method thereof will comprise all embodiment that fall in the scope of the invention.

Claims (10)

1. a three-dimensional semiconductor device, comprises in vertical direction overlapping at least in part multiple memory cell transistors and multiple selection transistor,
Wherein, each the first drain electrode, active area of selecting transistor to comprise vertically to distribute, be formed on the common-source in substrate, and be distributed in active area metal gates around;
Wherein, each memory cell transistor comprises the channel layer distributing perpendicular to substrate surface, and multiple interlayer insulating films and multiple gate stack structure are alternately laminated along the sidewall of described channel layer, and the second drain electrode is positioned at the top of described channel layer;
Wherein, described channel layer is electrically connected with described the first drain electrode.
2. three-dimensional semiconductor device according to claim 1, wherein, described metal gates is multi-grid structure or annular grid electrode structure.
3. three-dimensional semiconductor device according to claim 1, wherein, the lateral dimension of described the first drain electrode is more than or equal to the lateral dimension of described channel layer.
4. three-dimensional semiconductor device according to claim 1, wherein, each selects transistor to comprise gate insulator, and described gate insulator has surrounded bottom and the sidewall of described metal gates.
5. three-dimensional semiconductor device according to claim 1, wherein, each of multiple gate stack structures comprises the gate dielectric layer being made up of tunnel layer, accumulation layer, barrier layer.
6. a manufacture method for three-dimensional semiconductor device, comprises step:
On substrate, form and select transistorized active area;
Around active area, form and select transistorized metal gates;
At the stacked structure of selecting to form on transistor the first material layer and the second material layer;
Etching stacked structure forms vertical multiple hole slots;
In each hole slot, form the channel layer of memory cell transistor;
Selective removal the second material layer leaves multiple transverse concave grooves between the first material layer;
In multiple transverse concave grooves, form multiple gate stack structures.
7. method according to claim 6, wherein, the step that is formed with source region comprises:
A) etched substrate forms multiple active areas of vertical distribution; Or
B) on substrate, form the mask stack of the first mask layer and the second mask layer, the stacking formation through hole of etching mask, in through hole, deposition is formed with source region.
8. method according to claim 7, wherein, further comprises:
A1) after forming metal gates, form interlayer dielectric layer on substrate, etching interlayer dielectric layer forms the opening that exposes active area, forms the first drain electrode in opening; Or
B1) before forming metal gates, form the opening that exposes active layer at mask stack top, in opening, form the first drain electrode.
9. method according to claim 8, wherein, exposes the lateral dimension of the opening of active layer described in the lateral dimension of described the first drain electrode is more than or equal to.
10. method according to claim 6, wherein, each of multiple gate stack structures comprises the gate dielectric layer being made up of tunnel layer, accumulation layer, barrier layer.
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Families Citing this family (209)

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Publication number Priority date Publication date Assignee Title
US20130023129A1 (en) 2011-07-20 2013-01-24 Asm America, Inc. Pressure transmitter for a semiconductor processing environment
US10714315B2 (en) 2012-10-12 2020-07-14 Asm Ip Holdings B.V. Semiconductor reaction chamber showerhead
US20160376700A1 (en) 2013-02-01 2016-12-29 Asm Ip Holding B.V. System for treatment of deposition reactor
US10941490B2 (en) 2014-10-07 2021-03-09 Asm Ip Holding B.V. Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same
US10276355B2 (en) 2015-03-12 2019-04-30 Asm Ip Holding B.V. Multi-zone reactor, system including the reactor, and method of using the same
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JP6556556B2 (en) * 2015-08-20 2019-08-07 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
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US10211308B2 (en) 2015-10-21 2019-02-19 Asm Ip Holding B.V. NbMC layers
US11139308B2 (en) 2015-12-29 2021-10-05 Asm Ip Holding B.V. Atomic layer deposition of III-V compounds to form V-NAND devices
US10529554B2 (en) 2016-02-19 2020-01-07 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US10367080B2 (en) 2016-05-02 2019-07-30 Asm Ip Holding B.V. Method of forming a germanium oxynitride film
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US10612137B2 (en) 2016-07-08 2020-04-07 Asm Ip Holdings B.V. Organic reactants for atomic layer deposition
US9887082B1 (en) 2016-07-28 2018-02-06 Asm Ip Holding B.V. Method and apparatus for filling a gap
KR102532607B1 (en) 2016-07-28 2023-05-15 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and method of operating the same
US9812320B1 (en) 2016-07-28 2017-11-07 Asm Ip Holding B.V. Method and apparatus for filling a gap
KR20180033369A (en) * 2016-09-23 2018-04-03 삼성전자주식회사 Method for manufacturing semiconductor device
US11532757B2 (en) 2016-10-27 2022-12-20 Asm Ip Holding B.V. Deposition of charge trapping layers
US10714350B2 (en) 2016-11-01 2020-07-14 ASM IP Holdings, B.V. Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures
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TW202344708A (en) 2018-05-08 2023-11-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures
US10468503B1 (en) 2018-05-15 2019-11-05 International Business Machines Corporation Stacked vertical transport field effect transistor electrically erasable programmable read only memory (EEPROM) devices
KR102596988B1 (en) 2018-05-28 2023-10-31 에이에스엠 아이피 홀딩 비.브이. Method of processing a substrate and a device manufactured by the same
US11718913B2 (en) 2018-06-04 2023-08-08 Asm Ip Holding B.V. Gas distribution system and reactor system including same
US11270899B2 (en) 2018-06-04 2022-03-08 Asm Ip Holding B.V. Wafer handling chamber with moisture reduction
US11286562B2 (en) 2018-06-08 2022-03-29 Asm Ip Holding B.V. Gas-phase chemical reactor and method of using same
KR102568797B1 (en) 2018-06-21 2023-08-21 에이에스엠 아이피 홀딩 비.브이. Substrate processing system
US10797133B2 (en) 2018-06-21 2020-10-06 Asm Ip Holding B.V. Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures
WO2020003000A1 (en) 2018-06-27 2020-01-02 Asm Ip Holding B.V. Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
WO2020002995A1 (en) 2018-06-27 2020-01-02 Asm Ip Holding B.V. Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
US10580829B2 (en) * 2018-06-28 2020-03-03 International Business Machines Corporation Fabricating a vertical ReRAM array structure having reduced metal resistance
US10612136B2 (en) 2018-06-29 2020-04-07 ASM IP Holding, B.V. Temperature-controlled flange and reactor system including same
US10755922B2 (en) 2018-07-03 2020-08-25 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10388513B1 (en) 2018-07-03 2019-08-20 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10665667B2 (en) * 2018-08-14 2020-05-26 Globalfoundries Inc. Junctionless/accumulation mode transistor with dynamic control
US11430674B2 (en) 2018-08-22 2022-08-30 Asm Ip Holding B.V. Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
KR20200030162A (en) 2018-09-11 2020-03-20 에이에스엠 아이피 홀딩 비.브이. Method for deposition of a thin film
US11024523B2 (en) 2018-09-11 2021-06-01 Asm Ip Holding B.V. Substrate processing apparatus and method
CN110970344A (en) 2018-10-01 2020-04-07 Asm Ip控股有限公司 Substrate holding apparatus, system including the same, and method of using the same
US11232963B2 (en) 2018-10-03 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
KR102592699B1 (en) 2018-10-08 2023-10-23 에이에스엠 아이피 홀딩 비.브이. Substrate support unit and apparatuses for depositing thin film and processing the substrate including the same
KR102546322B1 (en) 2018-10-19 2023-06-21 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and substrate processing method
KR102605121B1 (en) 2018-10-19 2023-11-23 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and substrate processing method
US11087997B2 (en) 2018-10-31 2021-08-10 Asm Ip Holding B.V. Substrate processing apparatus for processing substrates
KR20200051105A (en) 2018-11-02 2020-05-13 에이에스엠 아이피 홀딩 비.브이. Substrate support unit and substrate processing apparatus including the same
US11572620B2 (en) 2018-11-06 2023-02-07 Asm Ip Holding B.V. Methods for selectively depositing an amorphous silicon film on a substrate
US10818758B2 (en) 2018-11-16 2020-10-27 Asm Ip Holding B.V. Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures
US10847366B2 (en) 2018-11-16 2020-11-24 Asm Ip Holding B.V. Methods for depositing a transition metal chalcogenide film on a substrate by a cyclical deposition process
US11217444B2 (en) 2018-11-30 2022-01-04 Asm Ip Holding B.V. Method for forming an ultraviolet radiation responsive metal oxide-containing film
KR102636428B1 (en) 2018-12-04 2024-02-13 에이에스엠 아이피 홀딩 비.브이. A method for cleaning a substrate processing apparatus
US11527548B2 (en) 2018-12-11 2022-12-13 Micron Technology, Inc. Semiconductor devices and electronic systems including an etch stop material, and related methods
US11158513B2 (en) 2018-12-13 2021-10-26 Asm Ip Holding B.V. Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures
JP2020096183A (en) 2018-12-14 2020-06-18 エーエスエム・アイピー・ホールディング・ベー・フェー Method of forming device structure using selective deposition of gallium nitride, and system for the same
US10957705B2 (en) * 2018-12-24 2021-03-23 Sandisk Technologies Llc Three-dimensional memory devices having a multi-stack bonded structure using a logic die and multiple three-dimensional memory dies and method of making the same
TWI819180B (en) 2019-01-17 2023-10-21 荷蘭商Ａｓｍ 智慧財產控股公司 Methods of forming a transition metal containing film on a substrate by a cyclical deposition process
KR20200091543A (en) 2019-01-22 2020-07-31 에이에스엠 아이피 홀딩 비.브이. Semiconductor processing device
CN111524788B (en) 2019-02-01 2023-11-24 Asm Ip私人控股有限公司 Method for topologically selective film formation of silicon oxide
JP2020136677A (en) 2019-02-20 2020-08-31 エーエスエム・アイピー・ホールディング・ベー・フェー Periodic accumulation method for filing concave part formed inside front surface of base material, and device
KR102626263B1 (en) 2019-02-20 2024-01-16 에이에스엠 아이피 홀딩 비.브이. Cyclical deposition method including treatment step and apparatus for same
KR20200102357A (en) 2019-02-20 2020-08-31 에이에스엠 아이피 홀딩 비.브이. Apparatus and methods for plug fill deposition in 3-d nand applications
TW202044325A (en) 2019-02-20 2020-12-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of filling a recess formed within a surface of a substrate, semiconductor structure formed according to the method, and semiconductor processing apparatus
TW202100794A (en) 2019-02-22 2021-01-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Substrate processing apparatus and method for processing substrate
KR20200108248A (en) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. STRUCTURE INCLUDING SiOCN LAYER AND METHOD OF FORMING SAME
KR20200108242A (en) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. Method for Selective Deposition of Silicon Nitride Layer and Structure Including Selectively-Deposited Silicon Nitride Layer
KR20200108243A (en) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. Structure Including SiOC Layer and Method of Forming Same
KR20200116033A (en) 2019-03-28 2020-10-08 에이에스엠 아이피 홀딩 비.브이. Door opener and substrate processing apparatus provided therewith
KR20200116855A (en) 2019-04-01 2020-10-13 에이에스엠 아이피 홀딩 비.브이. Method of manufacturing semiconductor device
KR20200123380A (en) 2019-04-19 2020-10-29 에이에스엠 아이피 홀딩 비.브이. Layer forming method and apparatus
KR20200125453A (en) 2019-04-24 2020-11-04 에이에스엠 아이피 홀딩 비.브이. Gas-phase reactor system and method of using same
KR20200130118A (en) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. Method for Reforming Amorphous Carbon Polymer Film
KR20200130121A (en) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. Chemical source vessel with dip tube
KR20200130652A (en) 2019-05-10 2020-11-19 에이에스엠 아이피 홀딩 비.브이. Method of depositing material onto a surface and structure formed according to the method
JP2020188255A (en) 2019-05-16 2020-11-19 エーエスエム アイピー ホールディング ビー．ブイ． Wafer boat handling device, vertical batch furnace, and method
USD947913S1 (en) 2019-05-17 2022-04-05 Asm Ip Holding B.V. Susceptor shaft
USD975665S1 (en) 2019-05-17 2023-01-17 Asm Ip Holding B.V. Susceptor shaft
USD935572S1 (en) 2019-05-24 2021-11-09 Asm Ip Holding B.V. Gas channel plate
KR20200141002A (en) 2019-06-06 2020-12-17 에이에스엠 아이피 홀딩 비.브이. Method of using a gas-phase reactor system including analyzing exhausted gas
KR20200143254A (en) 2019-06-11 2020-12-23 에이에스엠 아이피 홀딩 비.브이. Method of forming an electronic structure using an reforming gas, system for performing the method, and structure formed using the method
USD944946S1 (en) 2019-06-14 2022-03-01 Asm Ip Holding B.V. Shower plate
USD931978S1 (en) 2019-06-27 2021-09-28 Asm Ip Holding B.V. Showerhead vacuum transport
KR20210005515A (en) 2019-07-03 2021-01-14 에이에스엠 아이피 홀딩 비.브이. Temperature control assembly for substrate processing apparatus and method of using same
JP2021015791A (en) 2019-07-09 2021-02-12 エーエスエム アイピー ホールディング ビー．ブイ． Plasma device and substrate processing method using coaxial waveguide
CN112216646A (en) 2019-07-10 2021-01-12 Asm Ip私人控股有限公司 Substrate supporting assembly and substrate processing device comprising same
KR20210010307A (en) 2019-07-16 2021-01-27 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
KR20210010816A (en) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. Radical assist ignition plasma system and method
KR20210010820A (en) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. Methods of forming silicon germanium structures
US11643724B2 (en) 2019-07-18 2023-05-09 Asm Ip Holding B.V. Method of forming structures using a neutral beam
CN112242296A (en) 2019-07-19 2021-01-19 Asm Ip私人控股有限公司 Method of forming topologically controlled amorphous carbon polymer films
CN112309843A (en) 2019-07-29 2021-02-02 Asm Ip私人控股有限公司 Selective deposition method for achieving high dopant doping
CN112309899A (en) 2019-07-30 2021-02-02 Asm Ip私人控股有限公司 Substrate processing apparatus
CN112309900A (en) 2019-07-30 2021-02-02 Asm Ip私人控股有限公司 Substrate processing apparatus
US11587814B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
US11227782B2 (en) 2019-07-31 2022-01-18 Asm Ip Holding B.V. Vertical batch furnace assembly
US11587815B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
KR20210018759A (en) 2019-08-05 2021-02-18 에이에스엠 아이피 홀딩 비.브이. Liquid level sensor for a chemical source vessel
USD965044S1 (en) 2019-08-19 2022-09-27 Asm Ip Holding B.V. Susceptor shaft
USD965524S1 (en) 2019-08-19 2022-10-04 Asm Ip Holding B.V. Susceptor support
JP2021031769A (en) 2019-08-21 2021-03-01 エーエスエム アイピー ホールディング ビー．ブイ． Production apparatus of mixed gas of film deposition raw material and film deposition apparatus
USD949319S1 (en) 2019-08-22 2022-04-19 Asm Ip Holding B.V. Exhaust duct
USD979506S1 (en) 2019-08-22 2023-02-28 Asm Ip Holding B.V. Insulator
USD930782S1 (en) 2019-08-22 2021-09-14 Asm Ip Holding B.V. Gas distributor
USD940837S1 (en) 2019-08-22 2022-01-11 Asm Ip Holding B.V. Electrode
KR20210024423A (en) 2019-08-22 2021-03-05 에이에스엠 아이피 홀딩 비.브이. Method for forming a structure with a hole
KR20210024420A (en) 2019-08-23 2021-03-05 에이에스엠 아이피 홀딩 비.브이. Method for depositing silicon oxide film having improved quality by peald using bis(diethylamino)silane
US11286558B2 (en) 2019-08-23 2022-03-29 Asm Ip Holding B.V. Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film
KR20210029090A (en) 2019-09-04 2021-03-15 에이에스엠 아이피 홀딩 비.브이. Methods for selective deposition using a sacrificial capping layer
KR20210029663A (en) 2019-09-05 2021-03-16 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US11562901B2 (en) 2019-09-25 2023-01-24 Asm Ip Holding B.V. Substrate processing method
CN112593212B (en) 2019-10-02 2023-12-22 Asm Ip私人控股有限公司 Method for forming topologically selective silicon oxide film by cyclic plasma enhanced deposition process
TW202129060A (en) 2019-10-08 2021-08-01 荷蘭商Ａｓｍ Ｉｐ控股公司 Substrate processing device, and substrate processing method
KR20210043460A (en) 2019-10-10 2021-04-21 에이에스엠 아이피 홀딩 비.브이. Method of forming a photoresist underlayer and structure including same
KR20210045930A (en) 2019-10-16 2021-04-27 에이에스엠 아이피 홀딩 비.브이. Method of Topology-Selective Film Formation of Silicon Oxide
US11637014B2 (en) 2019-10-17 2023-04-25 Asm Ip Holding B.V. Methods for selective deposition of doped semiconductor material
KR20210047808A (en) 2019-10-21 2021-04-30 에이에스엠 아이피 홀딩 비.브이. Apparatus and methods for selectively etching films
US11646205B2 (en) 2019-10-29 2023-05-09 Asm Ip Holding B.V. Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same
KR20210054983A (en) 2019-11-05 2021-05-14 에이에스엠 아이피 홀딩 비.브이. Structures with doped semiconductor layers and methods and systems for forming same
US11501968B2 (en) 2019-11-15 2022-11-15 Asm Ip Holding B.V. Method for providing a semiconductor device with silicon filled gaps
KR20210062561A (en) 2019-11-20 2021-05-31 에이에스엠 아이피 홀딩 비.브이. Method of depositing carbon-containing material on a surface of a substrate, structure formed using the method, and system for forming the structure
CN112951697A (en) 2019-11-26 2021-06-11 Asm Ip私人控股有限公司 Substrate processing apparatus
KR20210065848A (en) 2019-11-26 2021-06-04 에이에스엠 아이피 홀딩 비.브이. Methods for selectivley forming a target film on a substrate comprising a first dielectric surface and a second metallic surface
CN112885693A (en) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 Substrate processing apparatus
CN112885692A (en) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 Substrate processing apparatus
JP2021090042A (en) 2019-12-02 2021-06-10 エーエスエム アイピー ホールディング ビー．ブイ． Substrate processing apparatus and substrate processing method
KR20210070898A (en) 2019-12-04 2021-06-15 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
JP2021097227A (en) 2019-12-17 2021-06-24 エーエスエム・アイピー・ホールディング・ベー・フェー Method of forming vanadium nitride layer and structure including vanadium nitride layer
US11527403B2 (en) 2019-12-19 2022-12-13 Asm Ip Holding B.V. Methods for filling a gap feature on a substrate surface and related semiconductor structures
KR20210089077A (en) 2020-01-06 2021-07-15 에이에스엠 아이피 홀딩 비.브이. Gas supply assembly, components thereof, and reactor system including same
KR20210095050A (en) 2020-01-20 2021-07-30 에이에스엠 아이피 홀딩 비.브이. Method of forming thin film and method of modifying surface of thin film
TW202130846A (en) 2020-02-03 2021-08-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of forming structures including a vanadium or indium layer
KR20210100010A (en) 2020-02-04 2021-08-13 에이에스엠 아이피 홀딩 비.브이. Method and apparatus for transmittance measurements of large articles
US11776846B2 (en) 2020-02-07 2023-10-03 Asm Ip Holding B.V. Methods for depositing gap filling fluids and related systems and devices
US11781243B2 (en) 2020-02-17 2023-10-10 Asm Ip Holding B.V. Method for depositing low temperature phosphorous-doped silicon
KR20210116240A (en) 2020-03-11 2021-09-27 에이에스엠 아이피 홀딩 비.브이. Substrate handling device with adjustable joints
US11876356B2 (en) 2020-03-11 2024-01-16 Asm Ip Holding B.V. Lockout tagout assembly and system and method of using same
KR20210117157A (en) 2020-03-12 2021-09-28 에이에스엠 아이피 홀딩 비.브이. Method for Fabricating Layer Structure Having Target Topological Profile
KR20210124042A (en) 2020-04-02 2021-10-14 에이에스엠 아이피 홀딩 비.브이. Thin film forming method
TW202146689A (en) 2020-04-03 2021-12-16 荷蘭商Ａｓｍ Ｉｐ控股公司 Method for forming barrier layer and method for manufacturing semiconductor device
TW202145344A (en) 2020-04-08 2021-12-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Apparatus and methods for selectively etching silcon oxide films
US11821078B2 (en) 2020-04-15 2023-11-21 Asm Ip Holding B.V. Method for forming precoat film and method for forming silicon-containing film
KR20210132600A (en) 2020-04-24 2021-11-04 에이에스엠 아이피 홀딩 비.브이. Methods and systems for depositing a layer comprising vanadium, nitrogen, and a further element
CN113555279A (en) 2020-04-24 2021-10-26 Asm Ip私人控股有限公司 Method of forming vanadium nitride-containing layers and structures including the same
TW202146831A (en) 2020-04-24 2021-12-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Vertical batch furnace assembly, and method for cooling vertical batch furnace
KR20210134226A (en) 2020-04-29 2021-11-09 에이에스엠 아이피 홀딩 비.브이. Solid source precursor vessel
KR20210134869A (en) 2020-05-01 2021-11-11 에이에스엠 아이피 홀딩 비.브이. Fast FOUP swapping with a FOUP handler
KR20210141379A (en) 2020-05-13 2021-11-23 에이에스엠 아이피 홀딩 비.브이. Laser alignment fixture for a reactor system
TW202147383A (en) 2020-05-19 2021-12-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Substrate processing apparatus
KR20210145078A (en) 2020-05-21 2021-12-01 에이에스엠 아이피 홀딩 비.브이. Structures including multiple carbon layers and methods of forming and using same
TW202201602A (en) 2020-05-29 2022-01-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Substrate processing device
US11581366B2 (en) * 2020-06-22 2023-02-14 Taiwan Semiconductor Manufacturing Company Limited Memory cell device with thin-film transistor selector and methods for forming the same
TW202218133A (en) 2020-06-24 2022-05-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method for forming a layer provided with silicon
TW202217953A (en) 2020-06-30 2022-05-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Substrate processing method
US11647633B2 (en) * 2020-07-13 2023-05-09 Micron Technology, Inc. Methods used in forming integrated circuitry comprising a stack comprising vertically-alternating first tiers and second tiers with the stack comprising a cavity therein that comprises a stair-step structure
TW202219628A (en) 2020-07-17 2022-05-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Structures and methods for use in photolithography
TW202204662A (en) 2020-07-20 2022-02-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method and system for depositing molybdenum layers
KR20220027026A (en) 2020-08-26 2022-03-07 에이에스엠 아이피 홀딩 비.브이. Method and system for forming metal silicon oxide and metal silicon oxynitride
USD990534S1 (en) 2020-09-11 2023-06-27 Asm Ip Holding B.V. Weighted lift pin
USD1012873S1 (en) 2020-09-24 2024-01-30 Asm Ip Holding B.V. Electrode for semiconductor processing apparatus
TW202229613A (en) 2020-10-14 2022-08-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of depositing material on stepped structure
KR20220053482A (en) 2020-10-22 2022-04-29 에이에스엠 아이피 홀딩 비.브이. Method of depositing vanadium metal, structure, device and a deposition assembly
TW202223136A (en) 2020-10-28 2022-06-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method for forming layer on substrate, and semiconductor processing system
TW202235675A (en) 2020-11-30 2022-09-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Injector, and substrate processing apparatus
CN114639631A (en) 2020-12-16 2022-06-17 Asm Ip私人控股有限公司 Fixing device for measuring jumping and swinging
TW202231903A (en) 2020-12-22 2022-08-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Transition metal deposition method, transition metal layer, and deposition assembly for depositing transition metal on substrate
USD1023959S1 (en) 2021-05-11 2024-04-23 Asm Ip Holding B.V. Electrode for substrate processing apparatus
USD980813S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas flow control plate for substrate processing apparatus
USD980814S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas distributor for substrate processing apparatus
USD981973S1 (en) 2021-05-11 2023-03-28 Asm Ip Holding B.V. Reactor wall for substrate processing apparatus
US20230066753A1 (en) * 2021-09-01 2023-03-02 Micron Technology, Inc. Electronic devices including vertical strings of memory cells, and related memory devices, systems and methods
USD990441S1 (en) 2021-09-07 2023-06-27 Asm Ip Holding B.V. Gas flow control plate
KR20230106130A (en) * 2021-12-30 2023-07-12 양쯔 메모리 테크놀로지스 씨오., 엘티디. Semiconductor device and its manufacturing method
CN116207152B (en) * 2022-10-25 2024-03-15 北京超弦存储器研究院 Storage structure, preparation method thereof and electronic equipment
CN115988875B (en) * 2023-01-30 2023-09-05 北京超弦存储器研究院 3D stacked semiconductor device, manufacturing method thereof and electronic equipment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102544049A (en) * 2010-12-22 2012-07-04 中国科学院微电子研究所 Three-dimensional semiconductor storage device and preparation method for three-dimensional semiconductor storage device
CN102569203A (en) * 2010-12-20 2012-07-11 中国科学院微电子研究所 Preparation method of three-dimensional multi-value non-volatile memorizer
US20120300547A1 (en) * 2011-05-24 2012-11-29 Eun Seok Choi 3-dimensional non-volatile memory device and method of manufacturing the same

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19600307C1 (en) * 1996-01-05 1998-01-08 Siemens Ag Highly integrated semiconductor memory and method for producing the semiconductor memory
US5874760A (en) * 1997-01-22 1999-02-23 International Business Machines Corporation 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation
US6246083B1 (en) * 1998-02-24 2001-06-12 Micron Technology, Inc. Vertical gain cell and array for a dynamic random access memory
AU2001286432A1 (en) * 2000-08-14 2002-02-25 Matrix Semiconductor, Inc. Dense arrays and charge storage devices, and methods for making same
US6448601B1 (en) * 2001-02-09 2002-09-10 Micron Technology, Inc. Memory address and decode circuits with ultra thin body transistors
JP4822841B2 (en) * 2005-12-28 2011-11-24 株式会社東芝 Semiconductor memory device and manufacturing method thereof
JP4745108B2 (en) * 2006-04-06 2011-08-10 株式会社東芝 Nonvolatile semiconductor memory device
JP4772656B2 (en) * 2006-12-21 2011-09-14 株式会社東芝 Nonvolatile semiconductor memory
JP5091491B2 (en) * 2007-01-23 2012-12-05 株式会社東芝 Nonvolatile semiconductor memory device
JP4939955B2 (en) * 2007-01-26 2012-05-30 株式会社東芝 Nonvolatile semiconductor memory device
US7848145B2 (en) * 2007-03-27 2010-12-07 Sandisk 3D Llc Three dimensional NAND memory
US7745265B2 (en) * 2007-03-27 2010-06-29 Sandisk 3D, Llc Method of making three dimensional NAND memory
JP2009038201A (en) * 2007-08-01 2009-02-19 Elpida Memory Inc Semiconductor device and manufacturing method of semiconductor device
JP2009164485A (en) * 2008-01-09 2009-07-23 Toshiba Corp Nonvolatile semiconductor storage device
KR101543331B1 (en) * 2009-07-06 2015-08-10 삼성전자주식회사 Method of fabricating vertical structure Non-volatile memory device having metal source line
US8575584B2 (en) * 2011-09-03 2013-11-05 Avalanche Technology Inc. Resistive memory device having vertical transistors and method for making the same
KR20130044711A (en) * 2011-10-24 2013-05-03 에스케이하이닉스 주식회사 Three dimension non-volatile memory device, memory system comprising the same and method of manufacturing the same
KR20130072076A (en) * 2011-12-21 2013-07-01 에스케이하이닉스 주식회사 Nonvolatile memory device and method for fabricating the same
US9018613B2 (en) * 2012-08-14 2015-04-28 Kabushiki Kaisha Toshiba Semiconductor memory device with a memory cell block including a block film
US9165933B2 (en) * 2013-03-07 2015-10-20 Sandisk 3D Llc Vertical bit line TFT decoder for high voltage operation
US9379246B2 (en) * 2014-03-05 2016-06-28 Sandisk Technologies Inc. Vertical thin film transistor selection devices and methods of fabrication
US9147468B1 (en) * 2014-05-21 2015-09-29 Macronix International Co., Ltd. Multiple-bit-per-cell, independent double gate, vertical channel memory
US9484390B2 (en) * 2014-05-30 2016-11-01 SK Hynix Inc. Method for fabricating semiconductor apparatus
US9653617B2 (en) * 2015-05-27 2017-05-16 Sandisk Technologies Llc Multiple junction thin film transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569203A (en) * 2010-12-20 2012-07-11 中国科学院微电子研究所 Preparation method of three-dimensional multi-value non-volatile memorizer
CN102544049A (en) * 2010-12-22 2012-07-04 中国科学院微电子研究所 Three-dimensional semiconductor storage device and preparation method for three-dimensional semiconductor storage device
US20120300547A1 (en) * 2011-05-24 2012-11-29 Eun Seok Choi 3-dimensional non-volatile memory device and method of manufacturing the same

Cited By (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI719015B (en) * 2015-04-01 2021-02-21 美商應用材料股份有限公司 Plasma enhanced chemical vapor deposition of films for improved vertical etch performance in 3d nand memory devices
US11365476B2 (en) 2015-04-01 2022-06-21 Applied Materials, Inc. Plasma enhanced chemical vapor deposition of films for improved vertical etch performance in 3D NAND memory devices
TWI766525B (en) * 2015-04-01 2022-06-01 美商應用材料股份有限公司 Plasma enhanced chemical vapor deposition of films for improved vertical etch performance in 3d nand memory devices
CN106206507A (en) * 2015-04-30 2016-12-07 旺宏电子股份有限公司 Semiconductor structure and manufacture method thereof
CN106206507B (en) * 2015-04-30 2019-06-14 旺宏电子股份有限公司 Semiconductor structure and its manufacturing method
CN108124495A (en) * 2015-07-24 2018-06-05 桑迪士克科技有限责任公司 Three-dimensional storage device with metal and silicide control gate
CN105742250A (en) * 2016-05-13 2016-07-06 武汉新芯集成电路制造有限公司 Storage structure and preparation method thereof
US11695074B2 (en) 2016-09-30 2023-07-04 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device, method of manufacturing the same and electronic device including the device
US11195765B2 (en) 2016-09-30 2021-12-07 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device including stressed source/drain, method of manufacturing the same and electronic device including the same
US11158547B2 (en) 2016-09-30 2021-10-26 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device, method of manufacturing the same, and electronic device including the device
WO2018059107A1 (en) * 2016-09-30 2018-04-05 中国科学院微电子研究所 Semiconductor device, manufacturing method thereof, and electronic apparatus comprising same
CN106298792B (en) * 2016-09-30 2019-07-30 中国科学院微电子研究所 Memory device and its manufacturing method and electronic equipment including the memory device
US10833193B2 (en) 2016-09-30 2020-11-10 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device, method of manufacturing the same and electronic device including the device
CN106298792A (en) * 2016-09-30 2017-01-04 中国科学院微电子研究所 Memory device and manufacture method thereof and include the electronic equipment of this memory device
CN108122924B (en) * 2016-10-31 2021-01-26 中芯国际集成电路制造(北京)有限公司 Flash memory device and method of manufacturing the same
CN108122924A (en) * 2016-10-31 2018-06-05 中芯国际集成电路制造(北京)有限公司 Flush memory device and its manufacturing method
CN109716522B (en) * 2016-11-17 2023-08-08 桑迪士克科技有限责任公司 Three-dimensional memory device with self-aligned drain side select gate electrode and method of fabricating the same
CN109716522A (en) * 2016-11-17 2019-05-03 桑迪士克科技有限责任公司 Three dimensional memory device and its manufacturing method with autoregistration drain side selection gate electrode
CN108735758A (en) * 2017-04-24 2018-11-02 美光科技公司 Vertically extending memory cell strings and the method for forming vertically extending memory cell strings
US11616075B2 (en) 2017-04-24 2023-03-28 Micron Technology, Inc. Elevationally-extending string of memory cells and methods of forming an elevationally-extending string of memory cells
CN107658312A (en) * 2017-08-28 2018-02-02 长江存储科技有限责任公司 The method for reducing corner damage in memory block in three-dimensional storage processing procedure
CN107579071A (en) * 2017-08-31 2018-01-12 长江存储科技有限责任公司 The forming method of channel layer in a kind of raceway groove hole
CN112951838A (en) * 2018-07-20 2021-06-11 长江存储科技有限责任公司 Three-dimensional memory device
CN112951838B (en) * 2018-07-20 2023-05-19 长江存储科技有限责任公司 Three-dimensional memory device
WO2020034809A1 (en) * 2018-08-13 2020-02-20 Wuxi Petabyte Technologies Co., Ltd. Three-dimensional ferroelectric memory devices
CN110827880A (en) * 2018-08-13 2020-02-21 无锡拍字节科技有限公司 Method for operating a ferroelectric memory cell with a plurality of capacitors
CN111668225A (en) * 2019-03-05 2020-09-15 爱思开海力士有限公司 Semiconductor device and method for manufacturing the same
CN111668225B (en) * 2019-03-05 2023-06-16 爱思开海力士有限公司 Semiconductor device and method for manufacturing the same
US11784126B2 (en) 2019-03-05 2023-10-10 SK Hynix Inc. Semiconductor device and manufacturing method thereof
CN110137176A (en) * 2019-03-29 2019-08-16 长江存储科技有限责任公司 3D nand flash memory and preparation method
CN112309860A (en) * 2019-07-30 2021-02-02 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN112309860B (en) * 2019-07-30 2023-07-04 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN110931500B (en) * 2019-10-25 2023-09-05 长江存储科技有限责任公司 3D memory device and method of manufacturing the same
CN110931500A (en) * 2019-10-25 2020-03-27 长江存储科技有限责任公司 3D memory device and method of manufacturing the same
CN110767655B (en) * 2019-10-31 2022-04-01 长江存储科技有限责任公司 Method for manufacturing three-dimensional memory
CN110767655A (en) * 2019-10-31 2020-02-07 长江存储科技有限责任公司 Method for manufacturing three-dimensional memory
CN113314521A (en) * 2020-02-26 2021-08-27 台湾积体电路制造股份有限公司 Semiconductor device and method for manufacturing the same
CN111463280B (en) * 2020-03-18 2023-04-07 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof, integrated circuit and electronic equipment
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WO2023216360A1 (en) * 2022-05-10 2023-11-16 长鑫存储技术有限公司 Three-dimensional memory and method for forming same
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WO2024060369A1 (en) * 2022-09-19 2024-03-28 长鑫存储技术有限公司 Memory and storage system

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