CN106298792A - Memory device and manufacture method thereof and include the electronic equipment of this memory device - Google Patents

Memory device and manufacture method thereof and include the electronic equipment of this memory device Download PDF

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Publication number
CN106298792A
CN106298792A CN201610872390.0A CN201610872390A CN106298792A CN 106298792 A CN106298792 A CN 106298792A CN 201610872390 A CN201610872390 A CN 201610872390A CN 106298792 A CN106298792 A CN 106298792A
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layer
source drain
memory element
selector
channel layer
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CN106298792B (en
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朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels

Abstract

Disclose a kind of memory device and manufacture method thereof and include the electronic equipment of this memory device.According to embodiment, this memory device can include memory element and the selector being sequentially stacked on substrate.Memory element and selector each may each comprise: the first source drain, channel layer and the second source drain being sequentially stacked, wherein, channel layer includes the semi-conducting material different from first, second source drain；And the grid stacking around the formation of the periphery of channel layer.The grid stacking of memory element is storage grid stacking.

Description

Memory device and manufacture method thereof and include the electronic equipment of this memory device
Technical field
It relates to semiconductor applications, in particular it relates to memory device based on vertical-type device and manufacture method thereof And include the electronic equipment of this memory device.
Background technology
In horizontal type device such as mos field effect transistor (MOSFET), source electrode, grid and drain electrode Arrange along the direction being roughly parallel to substrate surface.Due to this layout, horizontal type device is difficult to reduce further.With this not With, in vertical-type device, source electrode, grid and drain electrode are arranged along the direction being approximately perpendicular to substrate surface.Accordingly, with respect to water Flat pattern device, vertical-type device is easier to reduce.
But, part is taken for vertical-type, it is difficult to control gate is long, especially for the channel material of monocrystalline.On the other hand, as Fruit uses the channel material of polycrystalline, then relative to monocrystal material, channel resistance is greatly increased, thus is difficult to stack multiple vertical-type Device, because this can cause too high resistance.
Summary of the invention
In view of this, the purpose of the disclosure be at least in part to provide a kind of can the vertical-type of control gate length well Memory device and manufacture method thereof and include the electronic equipment of this memory device.
According to an aspect of this disclosure, it is provided that a kind of memory device, including the storage list being sequentially stacked on substrate Unit and selector, wherein, memory element and selector the most all include: the first source drain of being sequentially stacked, channel layer and Second source drain, wherein, channel layer includes the semi-conducting material different from first, second source drain；And around channel layer The grid stacking that periphery is formed, wherein, the grid stacking of memory element is storage grid stacking.
According to another aspect of the present disclosure, it is provided that a kind of method manufacturing memory device, including: fold successively on substrate Put the first source drain of memory element, channel layer and the second source drain and the first source drain of selector, channel layer and Second source drain；In the first source of the first source drain, channel layer and second source drain of memory element and selector/ Drop ply, channel layer and the second source drain limit the active area of this memory device；And rotating around memory element and selector The periphery of respective channel layer forms memory element and selector respective grid stacking, and wherein, the grid stacking of memory element is Storage grid stacking.
According to another aspect of the present disclosure, it is provided that a kind of electronic equipment, including above-mentioned memory device.
According to embodiment of the disclosure, the periphery of grid heap lap wound channel layer is formed and raceway groove is formed in channel layer, thus Grid length is determined by the thickness of channel layer.Channel layer such as can be formed by epitaxial growth, thus its thickness can be well Control.Therefore, it can control gate well long.The periphery of channel layer can be inside relative to the periphery of first, second source drain Recessed, thus grid stacking can embed this recessed in, reduce or even avoid the crossover with source/drain region, contribute to reduce grid with Parasitic capacitance between source/drain.It addition, channel layer can be single-crystal semiconductor material, can have high carrier mobility and Low discharge current, thus improve device performance.Owing to vertical-type device can be the most stacked on top of each other, such that it is able to system Make three-dimensional storage part, increase memory density.
Accompanying drawing explanation
By description to disclosure embodiment referring to the drawings, above-mentioned and other purposes of the disclosure, feature and Advantage will be apparent from, in the accompanying drawings:
Fig. 1～19 shows the schematic diagram of the flow process manufacturing memory device according to disclosure embodiment；
Figure 20～27 showed according to the showing of part stage in the flow process manufacturing memory device of another embodiment of the disclosure It is intended to.
Running through accompanying drawing, same or analogous reference represents same or analogous parts.
Detailed description of the invention
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure.However, it should be understood that these descriptions are the most exemplary , and it is not intended to limit the scope of the present disclosure.Additionally, in the following description, eliminate the description to known features and technology, with Avoid unnecessarily obscuring the concept of the disclosure.
Various structural representations according to disclosure embodiment shown in the drawings.These figures are not drawn to scale , wherein in order to understand the purpose of expression, it is exaggerated some details, and some details may be eliminated.Shown in figure Various regions, the shape of layer and the relative size between them, position relationship are only exemplary, are likely to be due to system in reality Make tolerance or technical limitations and deviation, and those skilled in the art have difference according to actually required can additionally design Shape, size, the regions/layers of relative position.
In the context of the disclosure, when one layer/element is referred to as positioned at another layer/element " on " time, this layer/element can To be located immediately on this another layer/element, or intermediate layer/element between them, can be there is.If it addition, one towards In one layer/element be positioned at another layer/element " on ", then when turn towards time, this layer/element may be located at this another layer/unit Part D score.
Memory device according to disclosure embodiment is based on vertical-type device.Here, memory element can be flash memory (flash) unit, such as floating gate type or charge trap-type.Specifically, each memory element in memory device is vertical-type device Part.It addition, selector can be stacked in memory element.Selector is also vertical-type device.This vertical-type device can To include the first source drain, channel layer and the second source drain that are sequentially stacked.In the first source drain and the second source drain The source/drain region of device can be formed, and the channel region of device can be formed in channel layer.Office in channel region two ends source/ Conductive channel can be formed by channel region between drain region.Grid stacking can be formed around the periphery of channel layer.Then, grid length is permissible Determined by the thickness of channel layer self rather than as in routine techniques, depend on time-consuming etching and determine.Channel layer example As formed by epitaxial growth, thus its thickness can control well.Therefore, it can control gate well long.Ditch The periphery of channel layer can inwardly concave relative to the periphery of first, second source drain.So, the grid stacking formed can be embedding In channel layer relative to first, second source drain recessed in, reduce or even avoid the crossover with source/drain region, contribute to fall Parasitic capacitance between low grid and source/drain.Channel layer can be made up of single-crystal semiconductor material, to improve device performance.Especially It is can to reduce channel resistance, thus beneficially vertical-type device is stacked on top of each other.Certainly, source drain partly can also be led by monocrystalline Body material is constituted.In this case, the single-crystal semiconductor material of channel layer and the single crystal semiconductor material of first, second source drain Material can be eutectic.
The grid stacking of memory element can be storage grid stacking, such as, include floating boom or electric charge capture layer or ferroelectricity material Material, in order to realize storage function.Specifically, the grid stacking of memory element can include the first grid dielectric layer being sequentially stacked, float Gate layer or electric charge capture layer, second gate dielectric layer and grid conductor layer, or the first metal layer, the ferroelectricity being sequentially stacked can be included Material layer, the second metal level, gate dielectric layer and grid conductor layer.Selector can be gating device, e.g. field effect transistor Pipe (FET) device.Such as, the grid stacking of selector can include gate dielectric layer and the grid conductor layer being sequentially stacked.
Multiple such memory element (thus forming storage string) can be stacked, to increase memory density.This storage string Such as can be approximately perpendicular to substrate surface extend.Same storage string can have public selector.Such as, selector The top of this string can be arranged on.By selector, can select to store string accordingly.
Electrical connections between memory element is as passed through the second source drain of memory element and the depositing of upper strata of lower floor The first source drain i.e. direct physical adjacent to each other contact of storage unit realizes.Under this situation, the memory element of lower floor First source drain of memory element on the second source drain and upper strata can even is that one, that is, they can pass through There is provided with semi-conductor layer.
Similarly, the electrical connections between memory element and selector is as passed through the second source/drain of memory element Layer i.e. direct physical adjacent to each other with the first source drain of selector contacts and realizes.Under this situation, the of memory element Two source drain can even is that one, that is, they can pass through same semiconductor with the first source drain of selector Layer provides.
It addition, multiple storage string can be arranged on substrate, thus constitute storage array.In this storage array, each Storage string can have equal number of memory element, and they are sequentially stacked, thus form multilamellar.In each storage string on identical layer Memory element can be located substantially in identical plane (such as, being roughly parallel to the plane of substrate surface).Specifically, phase Can be formed by identical semiconductor layer with the respective channel layer of the memory element on layer, respective first source drain can be by phase Being formed with semiconductor layer, respective second source drain can be formed by identical semiconductor layer.It addition, the storage on identical layer Unit respective grid stacking can be integral.
According to embodiment of the disclosure, the doping for source/drain region can be partially into channel layer near the first source/drain Layer and the end of the second source drain.Thus, at channel layer near the formation doping of the end of the first source drain and the second source drain Distribution, resistance between source/drain region and channel region when this contributes to reducing break-over of device, thus boost device performance.Particularly, For memory element, the scope between dopant profiles in the opposed end of its channel layer and its scope occupied by grid conductor layer Can be with substantial alignment.This contributes to reducing non-essential resistance, thus improves device performance.
According to embodiment of the disclosure, channel layer can include the semi-conducting material different from first, second source drain. So, be conducive to channel layer being processed such as selective etch, to be allowed to recessed relative to first, second source drain.Separately Outward, the first source drain and the second source drain can include identical semi-conducting material.
Owing to memory element and selector are all vertical-type devices and stacked on top of each other, therefore except being in the choosing of the top Selecting outside the second source drain of device, memory element and selector respective grid stacking cannot be directly square respective Become electrical contacts.Therefore, in order to form their electrical connection, the electrical contacts transversely offset can be formed at, and pass through The parts of horizontal expansion and be electrically connected.Such as, grid stacking (specifically, grid conductor therein) formed around channel layer periphery Can include that, from the most recessed lateral extension portions extended laterally outward, this lateral extension portions can extend beyond and be limited Fixed active area periphery, in order to be then able to form the electrical contacts contacted therewith above it.For being in bottom First source drain of memory element, can be patterned the periphery extending beyond top for bottom, thus be then able under it The top in portion forms the electrical contacts contacted therewith.
Owing to there is multiple such lateral extension portions, at least some in these lateral extension portions can be towards not Same direction horizontal expansion, to avoid interfering between corresponding electrical contacts.If in these lateral extension portions at least Some in the vertical direction crossovers, then, in the lateral extension portions of these crossovers, the lateral extension portions being positioned at lower section is permissible Extend beyond lateral extension portions above, to avoid making electrical contact with accordingly interfering.
This memory device such as can manufacture as follows.Specifically, the of memory element can be sequentially stacked on substrate One source drain, channel layer and the second source drain and the first source drain of selector, channel layer and the second source drain.As Upper described, multiple memory element can be stacked.Specifically, can be stacked the first source drain of the first memory element, channel layer and Second source drain, the first source drain of the second memory element, channel layer and the second source drain, by that analogy.In the top In memory element, the first source drain of selector, channel layer and the second source drain can be stacked.For example, it is possible to by outward Epitaxial growth provides these layers.When epitaxial growth, the thickness of grown channel layer can be controlled.It addition, under as it has been described above, Layer the second source drain of memory element and the first source drain of upper strata memory element can be one, i.e. same layer；Go up most Second source drain of memory element of side and the first source drain of selector can be one, i.e. same layer.
For stacked above layers, source region can be defined wherein.For example, it is possible to by they selective etch successively For required shape.Generally, active area can be in column (such as, cylindric).The order of etching can be from top to bottom to each layer Carry out successively.In the case of forming storage array, each layer can be patterned into part (" island ", the example in other words of multiple separation Such as circular islands).These islands in each layer with substantial alignment, thus can respectively constitute and fold each other on the stacked direction of these layers The memory element put and selector.As it has been described above, for the ease of connecting the memory element being in bottom in subsequent process The first source drain in the source/drain region that formed, can be just for the top of this layer to the etching of this layer, thus the bottom of this layer The periphery on its top can be extended beyond.
It is then possible to form grid stacking around the periphery of channel layer.Here, the grid stacking of memory element can be storage grid heap Folded.Such as, the grid stacking of memory element can include being sequentially stacked first grid dielectric layer, floating gate layer or electric charge capture layer, the Two gate dielectric layers and grid conductor layer, or can include being sequentially stacked the first metal layer, ferroelectric material layer, the second metal level, Gate dielectric layer and grid conductor layer, the grid stacking of selector can include the gate dielectric layer and the grid conductor layer that are sequentially stacked.
Furthermore it is possible to make the periphery of the channel layer of each memory element or selector relative to corresponding first, second source/ The periphery of drop ply inwardly concaves, in order to limit the space accommodating grid stacking.Such as, this can be realized by selective etch. Then, grid stacking can embed this recessed in.
Source/drain region can be formed in first, second source drain of each device.Such as, this can be by first, Two source drain doping realize.For example, it is possible to carry out ion implanting, plasma doping, or in growth first, second source/ Doping in situ during drop ply.According to an advantageous embodiment, can be outside the periphery of channel layer be relative to first, second source drain Formed in week recessed in, form sacrificial gate, on the surface of first, second source drain, then form adulterant active layer, and pass through Such as annealing makes the adulterant in adulterant active layer in first, second source drain enters active area.Sacrificial gate can stop mixes Adulterant in miscellaneous dose of active layer is directly entered in channel layer.However, it is possible to have element dopants via first, second source drain And enter channel layer near the first source drain and the end of the second source drain.For memory element and selector, formed source/ The operation in drain region can carry out that (such as, the source/drain region in each of which has the situation of same or similar doping characteristic together Under), or can separately carry out (in the case of such as, the source/drain region in each of which has different doping characteristics).
The disclosure can present in a variety of manners, some of them example explained below.
Fig. 1～19 shows the schematic diagram of the flow process manufacturing memory device according to disclosure embodiment.
As shown in Figure 1, it is provided that substrate 1001.This substrate 1001 can be various forms of substrate, includes but not limited to body Semiconductive material substrate such as body Si substrate, semiconductor-on-insulator (SOI) substrate, compound semiconductor substrate such as SiGe substrate Deng.In the following description, for convenience of description, it is described as a example by body Si substrate.
On substrate 1001, such as epitaxial growth can be passed through, sequentially form first source drain the 1003, first channel layer 1005, the second source drain the 1007, second channel layer 1009 and the 3rd source drain 1011.Such as, for p-type device, first Source drain 1003 can include suitable semi-conducting material such as SiGe (atomic percent of Ge can be about 10-40%), thickness It is about 20-50nm；First channel layer 1005 can include being different from partly leading of first source drain the 1003, second source drain 1007 Body material such as Si, thickness is about 10-100nm；Second source drain 1007 can include the material identical with the first source drain 1003 Material is such as SiGe (atomic percent of Ge can be about 10-40%)；Second channel layer 1009 can include being different from the second source/drain The semi-conducting material such as Si of layer the 1007, the 3rd source drain 1011, thickness is about 10-100nm；3rd source drain 1011 can be wrapped Including the material such as SiGe (atomic percent of Ge can be about 10-40%) identical with the second source drain 1007, thickness is about 20-50nm.SiGe lattice paprmeter in the case of not having strain is not having the lattice paprmeter in the case of straining more than Si. The material of source drain and channel layer selects to be not limited to this, may be configured to provide other quasiconductors of suitable Etch selectivity Material.Such as, for n-type device, first source drain the 1003, second source drain 1007 and the 3rd source drain 1011 can be wrapped Include Si:C (atomic percent of C can be about 0.1-5%)；First channel layer 1005 and the second channel layer 1009 can include Si.Si:C lattice paprmeter in the case of not having strain is not having the lattice paprmeter in the case of straining less than Si.Certainly, originally Disclosure is not limited to this.Such as, each channel layer can include with under or over the identical component of source drain, but component contains Measure different semi-conducting material (such as, be all SiGe, but wherein the atomic percent of Ge is different), if channel layer relative to Under and on source drain possess Etch selectivity.
In this example, the first source drain the 1003, first channel layer 1005 and bottom of the second source drain 1007 1007-1 (such as, thickness is about 10-50nm) is for limiting the active area of memory element, and the top of the second source drain 1007 1007-2 (such as, thickness is about 10-50nm), the second channel layer 1009 and the 3rd source drain 1011 are used for limiting selector The active area of part.Here, memory element and selector are adjacent to each other, and share identical source drain 1007.But the disclosure It is not limited to this.For example, it is possible to growth is used for source drain 1007-1 of memory element and is used for the source/drain of selector respectively Layer 1007-2, they can have identical or different semi-conducting material.
When growing each source drain 1003,1007,1011, can carry out adulterating in situ to them, in order to subsequently form Source/drain region.Such as, for n-type device, N-shaped doping can be carried out；For p-type device, p-type doping can be carried out.Memory element Doping type respective with selector can be identical, it is also possible to different.
It addition, when growing channel layer 1005,1009, it is also possible to carry out adulterating, with adjusting means threshold value in situ to them Voltage (Vt).Such as, for n-type device, can carry out p-type doping, doping content is about 1E17-1E19cm-3；For p-type device Part, can carry out N-shaped doping, and doping content is about 1E17-1E19cm-3。
It addition, for without junction device, each source drain 1003,1007,1011 and channel layer 1005,1009 can be entered The doping of row same type.
In this example, the first source drain 1003 is additionally to be grown on substrate 1001.But, the disclosure is not limited to This.For example, it is possible to self form the first source drain by substrate 1001.In such a case, it is possible to by substrate 1001 Middle formation well region, in order to form source/drain region wherein.
It addition, for the convenience of composition and provide the purposes such as suitable stop-layer in subsequent processes, grown this A little semiconductor layer, it is also possible to form hard mask 1013.In this example, hard mask 1013 can include be sequentially stacked One hard mask layer 1013-1, the second hard mask layer 1013-2 and the 3rd hard mask layer 1013-3.Such as, the first hard mask layer 1013-1 can include oxide (such as silicon oxide), and thickness is about 2-10nm；Second hard mask layer 1013-2 can include nitridation Thing (such as silicon nitride), thickness is about 10-100nm；3rd hard mask layer 1013-3 can include that oxide, thickness are about 20- 100nm.The lamination of hard mask 1013 configures primarily to provide suitable Etch selectivity in subsequent processes, this area skill Art personnel it is contemplated that other configure.
It follows that the active area of device can be limited.Such as, this can be carried out as follows.Specifically, such as Fig. 2 (a) and 2 (b) Shown in (Fig. 2 (a) is sectional view, and Fig. 2 (b) is top view, and AA ' line therein shows the interception position in cross section), can be firmly Form photoresist (not shown) on mask 1013, by photoetching (exposed and developed), photoresist is patterned into required form (at this In example, circular), then the shape of the photoresist after composition can be transferred to hard mask 1013.For example, it is possible to successively 3rd hard mask layer 1013-3, the second hard mask layer 1013-2 and the first hard mask layer 1013-1 are carried out selective etch as anti- Answer ion etching (RIE).It is then possible to successively to the 3rd source drain the 1011, second channel layer 1009 and the second source drain 1007 carry out selective etch such as RIE.Etching proceeds in the second source drain 1007, but does not proceed to the second source drain At the bottom surface of 1007, thus the top 1007-2 of the second source drain is patterned to the shape corresponding to hard mask, and its underpart 1007-1 is the most unchanged.Then, the 3rd source drain the 1011, second channel layer 1009 and the top of the second source drain after etching 1007-2 forms column (in this example, cylindric).RIE such as can be carried out by the direction being approximately perpendicular to substrate surface, Thus this column is also roughly perpendicular to substrate surface.Afterwards, photoresist can be removed.
For p-type device, after rie, the lattice paprmeter in the case of straining is not being had not have more than Si due to SiGe Having the lattice paprmeter in the case of strain, produce strain in Si, this strain can make the hole mobility of Si not have more than it Hole mobility in the case of strain, or the effective mass of the light hole of Si is less than its light sky in the case of not strain The effective mass in cave, or the concentration of the light hole of Si is more than the concentration of its light hole in the case of not having strain, and then make p The ON state current of type device increases and therefore enhances the performance of p-type device.Alternatively, for n-type device, after rie, by There is no the lattice paprmeter in the case of straining in Si:C lattice paprmeter in the case of not having strain less than Si, producing in Si Raw strain, this strain can make the electron mobility of Si not have the electron mobility in the case of straining more than it, or the electricity of Si The effective mass of son is less than the effective mass of its electronics in the case of not having strain, and then makes the ON state current of n-type device Increase and enhance the performance of n-type device with this.
If it addition, select SiGe to use Si as source drain material as channel layer materials, this selection i.e. can increase The ON state current of p-type device, can reduce again the off-state current of p-type device, thus enhance the performance of p-type device.Reason exists Energy gap in Si is more than the energy gap of SiGe, and SiGe hole mobility is more than the hole mobility of Si.
Then, as it is shown on figure 3, the periphery top 1007-relative to the second source drain of the second channel layer 1009 can be made 2 and the 3rd periphery of source drain 1011 recessed (in this example, recessed along the horizontal direction being roughly parallel to substrate surface). Such as, this can be by relative to the second source drain 1007 and the 3rd source drain 1011, further selective etch the second ditch Channel layer 1009 realizes.In one example, particularly in the case of source drain is Si and channel layer is SiGe, it is possible to use Numeral etching.Specifically, surface oxide layer can be formed on the surface of Si source drain and SiGe channel layer by heat treatment, Then surface oxide layer is removed by etching.The oxidation rate of the SiGe oxidation rate higher than Si, and the oxide on SiGe is more It is easily removed.Can be with the step of repeated oxidation-removal oxide, recessed needed for realizing.Compared to selective etch, this Mode can better control over recessed degree.
So, active area (the top 1007-2 of the second source drain after etching, second ditch of selector are just defined Channel layer 1009 and the 3rd source drain 1011).In this example, active area is generally cylindrical.In active area, the second source drain Top 1007-2 and the periphery of the 3rd source drain 1011 can be with substantial alignment, and the periphery of the second channel layer 1009 is relative Recessed.Certainly, the shape of active area is not limited to this, but can form other shapes according to layout.Such as, at top view In, active area can be with ovalize, square, rectangle etc..
Recessed relative to the top 1007-2 of the second source drain and the 3rd source drain 1011 of the second channel layer 1009 In, will be subsequently formed grid stacking.For avoiding subsequent processes to impact for channel layer 1009 or stay not in this is recessed Necessary material thus affect the formation of follow-up grid stacking, can be at this recessed middle filling one material layer to occupy the sky of grid stacking Between (therefore, this material layer can be referred to as " sacrificial gate ").Such as, this can pass through deposition of nitride in the structure shown in Fig. 3, Then the nitride to deposit carries out eat-back such as RIE.RIE, nitride can be carried out to be approximately perpendicular to the direction of substrate surface Can be only left at recessed interior, form sacrificial gate 1015, as shown in Figure 4.In this case, sacrificial gate 1015 can be substantially filled with State recessed.
Alternatively, it is also possible to top 1007-2 and the 3rd source drain 1011 to the second source drain adulterate further, special It not in the case of above-mentioned original position doping content is inadequate.Specifically, as it is shown in figure 5, can be formed in the structure shown in Fig. 4 Adulterant active layer 1017.Such as, adulterant active layer 1017 can include oxide such as silicon oxide, wherein contains adulterant.For n Type device, can comprise n-type dopant；For p-type device, p-type dopant can be comprised.Here, in order to reduce dopant source Layer 1017 on the impact of the second source drain bottom 1007-1 for memory element (particularly at memory element and selector Source/drain region there is different doping characteristic in the case of), adulterant active layer 1017 can be formed as the active area of selector (due to the existence of sacrificial gate 1015, this side wall is in fact formed at the second source drain to the form of the side wall (spacer) on sidewall Top 1007-2 and the 3rd source drain 1011 sidewall on).For example, it is possible to by such as chemical vapor deposition (CVD) or former Sublayer deposit (ALD) etc. the most conformally deposits a thin film on the surface of structure shown in Fig. 4, then along being approximately perpendicular to substrate The direction on surface carries out RIE to this thin film, obtains the adulterant active layer 1017 of side wall form.
Then, as shown in Figure 6, the impurity of doping in situ by such as annealing, can be activated or make adulterant further The adulterant comprised in active layer 1017 enters in active area, thus forms doped region wherein, as shown in the dash area in figure. More specifically, can in the 3rd source drain 1011 one of source/drain region forming selector S/D-t1, and in the second source/drain The top 1007-2 of layer is formed another source/drain region S/D-t2 of selector.Afterwards, adulterant active layer 1017 can be removed.
It addition, exist despite sacrificial gate 1015, but adulterant can also be via the top 1007-2 of the second source drain With the 3rd source drain 1011 and enter in the second channel layer 1009, thus at the two ends up and down of the second channel layer 1009 formed Certain dopant profiles, as shown in the dotted-line ellipse circle in figure.When this dopant profiles can reduce break-over of device source/drain region it Between resistance, thus boost device performance.
It follows that similar process can be carried out for memory element.In order to protective seletion device active area (particularly Source/drain region) unaffected in subsequent processes (especially for suppression adulterant cross-contamination), can be formed in its periphery and protect Sheath 1019, as shown in Figure 7.This protective layer 1019 can also be formed as side wall form.
It is then possible to limit the active area of memory element.As it is shown in fig. 7, hard mask 1013 and protection can be there is In the case of layer 1019, the bottom 1007-1 of the second source drain 1007, the first channel layer 1005 and the first source drain successively 1003 carry out selective etch such as RIE.Here, etching proceeds at the bottom surface of the first source drain 1003.But, the disclosure is not It is limited to this.Such as, etching may proceed in the first source drain 1003, but does not proceed to the bottom surface of the first source drain 1003 Place, thus the top of the first source drain 1003 is etched, and bottom is the most unchanged.Then, the second source drain 1007 after etching Bottom 1007-1, the first channel layer 1005 and the first source drain 1003 (or its top) form column (in this example, circle Column).RIE such as can be carried out by the direction being approximately perpendicular to substrate surface, thus this column is also roughly perpendicular to substrate table Face.
Then, the periphery bottom 1007-relative to the second source drain 1007 of the first channel layer 1005 can similarly be made 1 and first the periphery of source drain 1003 (or its top) recessed (in this example, along the horizontal stroke being roughly parallel to substrate surface Recessed to direction), see accompanying drawing 8.Such as, this can pass through relative to the second source drain 1007 and the first source drain 1003, Selective etch the first channel layer 1005 realizes further.Similarly, this can also be etched by numeral and realize.
So, active area (the bottom 1007-1 of the second source drain after etching, first ditch of memory element are just defined Channel layer 1005 and the first source drain 1003).In this example, active area is generally cylindrical, and with the active area base of selector (because utilizing identical mask) it is directed in basis.In active area, the bottom 1007-1 of the second source drain and the first source drain The periphery on 1003 (or its tops) can be with substantial alignment, and the periphery of the first channel layer 1005 is the most recessed.As it has been described above, Sacrificial gate 1021 can be formed, as shown in Figure 8 during this is recessed.Sacrificial gate 1021 such as can include nitride.As it has been described above, this Can be realized by deposition of nitride eat-back.In order to improve selectivity or technology controlling and process, before deposition of nitride, also may be used To deposit one layer of thin-oxide (such as, thickness is about 1-5nm).
It is likewise possible to bottom 1007-1 and the first source drain 1003 to the second source drain mix further alternatively Miscellaneous, particularly in the case of above-mentioned original position doping content is inadequate.Specifically, as it is shown in figure 9, can be in the structure shown in Fig. 8 Upper formation adulterant active layer 1023.Such as, adulterant active layer 1023 can include oxide such as silicon oxide, wherein contains doping Agent.For n-type device, n-type dopant can be comprised；For p-type device, p-type dopant can be comprised.Here, dopant source Layer 1023 can be a thin film, such that it is able to be substantially conformally deposited on the table of structure shown in Fig. 8 by such as CVD or ALD etc. On face.
It is then possible to by such as annealing, activate the impurity of doping in situ or make further in adulterant active layer 1023 The adulterant comprised enters in active area, thus forms doped region wherein, as shown in the dash area in Fig. 9.More specifically, Can in the bottom 1007-1 of the second source drain one of source/drain region forming memory element S/D-b1, and in the first source/drain Layer 1003 is formed another source/drain region S/D-b2 of memory element.Due to the existence of protective layer 1019, dopant source can be suppressed Adulterant in layer 1023 enters in the active area of selector.Similarly, as it has been described above, upper and lower at the first channel layer 1005 Certain dopant profiles is formed, as shown in the dotted-line ellipse circle in figure at two ends.Afterwards, such as selective etch can be passed through, Remove adulterant active layer 1023 and protective layer 1019, as shown in Figure 10.
In this example, adulterant active layer 1023 includes the part extended along the horizontal surface of substrate 1001, thus even Can form doped region in the surface of substrate 1001, this doped region extends beyond the periphery of column active area.So, follow-up Technique easily can be electrically connected to source/drain region S/D-b2 by this doped region.
In the above examples, by from adulterant active layer to active area drives in (drive in) adulterant formed source/ Drain region, but the disclosure is not limited to this.For example, it is possible to by the mode such as ion implanting, plasma doping, form source/drain District.
In the above examples, for memory element and selector, carry out active area restriction respectively.But, the disclosure is not It is limited to this.Active area restriction can be together carried out for memory element and selector.Such as, in the description above in association with Fig. 3 In, selective etch not stops at the top of the second source drain 1007, and is to continue with carrying out downwards, until the first source drain 1003 (being etched to its bottom surface or middle part).So, the 3rd source drain the 1011, second channel layer the 1009, second source/drain after etching Layer the 1007, first channel layer 1005 and the first source drain 1003 (or its top) are in column.It is then possible to make the first channel layer 1005 is relative recessed with the second channel layer 1009.Such as, this can be by relative to the 3rd source drain the 1011, second source drain 1007 and first source drain 1003 (SiGe) selective etch the first channel layer 1005 and the second channel layer 1009 (Si) come real Existing.By deposition of nitride and be etched back, can the first channel layer 1005 and the second channel layer 1009 recessed in concurrently form Sacrificial gate.
It addition, in the above examples, for memory element and selector, it is utilized respectively corresponding adulterant active layer and carries out The supplementary doping of source/drain region.But, the disclosure is not limited to this.Source/drain can be together carried out for memory element and selector The supplementary doping in district.Such as, the active area of memory element and selector (and forming sacrificial gate) as defined above it After, identical adulterant active layer can be formed on the sidewall of the active area of both memory element and selector, and will wherein Adulterant drive in active layer.
Alternatively, in order to reduce contact resistance, silicide 1025 can be formed in the surface of source/drain region, such as Figure 11 institute Show.Such as, this by depositing layer of metal layer (such as, Ni, NiPt or Co) in the structure shown in Figure 10, and can move back Fire, so that this metal level and semi-conducting material generation silicification reaction, generates silicide 1025.In this example, silicide 1025 It is also formed on the surface of substrate 1001.Subsequently, unreacted residual metallic can be removed.
Sealing coat can be formed, to realize electric isolution at active region.Here, the formation stacked for the following grid of cooperation, Sealing coat divides multilamellar to be formed.
Such as, as shown in figure 12, can in the structure shown in Figure 11 deposited oxide 1027, and it is planarized Process such as chemically mechanical polishing (CMP).CMP can stop at the second hard mask layer 1013-2 (nitride).Then, such as Figure 13 institute Show, can be with the oxide of etch-back planarization, to form the first sealing coat 1027.Here, the end face of sealing coat 1027 may be located at Between end face and the bottom surface of the first channel layer 1005, this contributes to forming self aligned grid stacking.Due to sacrificial gate 1015,1021 Existence, can avoid sealing coat 1027 material enter grid to be accommodated stacking above-mentioned recessed in.
Afterwards, as shown in figure 14, sacrificial gate 1021 can be removed, with discharge the first semiconductor layer 1005 recessed in sky Between.For example, it is possible to by selective etch, remove sacrificial gate 1021 (nitride).In this example, due to sacrificial gate 1015 And second hard mask layer 1013-2 be nitride equally, so it is also removed.Additionally, after removing sacrificial gate 1015, Can also be carried out, to clean the surface (such as, removing surface oxide layer that may be present) of channel layer 1005,1009.? In cleaning process, the first hard mask layer 1013-1 can also be removed.
Then, as shown in figure 15, can be in the recessed middle formation storage grid stacking of the first channel layer 1005.Specifically, may be used To deposit first grid dielectric layer 1029, floating gate layer or electric charge capture layer 1031 in the structure shown in Figure 14 successively, second gate is situated between Matter layer 1033 and grid conductor layer 1035.Such as, first grid dielectric layer 1019 can include high-K gate dielectric such as HfO2, thickness is About 1-10nm；Floating gate layer or electric charge capture layer 1021 can include floating gate material such as metal or charge-trapping material such as nitride, Thickness is about 1-20nm；Second gate dielectric layer 1023 includes high-K gate dielectric such as HfO2, thickness is about 1-10nm；Grid conductor layer 1025 can include metal gate conductor.Here, first grid dielectric layer 1029, floating gate layer or electric charge capture layer 1031, second gate Jie Matter layer 1033 is formed relatively thin, can substantially be conformally formed.It addition, at first grid dielectric layer 1029 and first grid conductor layer Between 1031, it is also possible to form work function regulating course.Before forming first grid dielectric layer 1029, it is also possible to formed and such as aoxidize The boundary layer of thing.It is then possible to the grid conductor layer 1035 deposited is etched back so that it is the end face of the part outside recessed It is not higher than and the end face of the preferably shorter than first channel layer 1005.It addition, after eat-back grid conductor layer 1035, it is also possible to pass through example Such as selective etch, remove and be exposed to outer second gate dielectric layer and floating gate layer or electric charge capture layer (and alternatively first Gate dielectric layer 1029).
Alternatively, grid stacking can include ferroelectric material.Such as, grid stacking can include the first metal being sequentially stacked Layer, ferroelectric material layer, the second metal level, gate dielectric layer and grid conductor layer (not shown).Such as, ferroelectric material can include oxygen Change hafnium such as HfO2, zirconium oxide such as ZrO2, tantalum oxide such as TaO2, hafnium oxide zirconium HfxZr1-xO2(wherein x value is the scope of (0,1)) Such as Hf0.5Zr0.5O2, hafnium oxide tantalum HfxTa1-xO2(wherein x value is the scope of (0,1)) is such as Hf0.5Ta0.5O2, HfO containing Si2、 HfO containing Al2、BaTiO3、KH2PO4Or SBTi, the first metal layer and the second metal level each may each comprise TiN.This feelings Under condition, the first metal layer, ferroelectric material layer, the second metal level, gate dielectric layer and grid conductor layer can be deposited successively.After deposit Can proceeded as above be etched back.Here, not only need to be etched back grid conductor layer, in addition it is also necessary to other layers in eat-back grid stacking.
So, memory element storage grid stacking can embed and be self-aligned to the first channel layer 1005 recessed in, from And overlap with the whole height of the first channel layer 1005.Then, the grid length of memory element is by the height of the first channel layer 1005 Determine.
It addition, the second channel layer 1009 recessed in, also embedded in first grid dielectric layer 1029, floating gate layer or electric charge and catch Obtain layer 1031, second gate dielectric layer 1033 and the lamination of grid conductor layer 1035.
It follows that the shape of grid stacking can be adjusted, in order to follow-up interconnection makes.For example, it is possible at Figure 15 Photoresist (not shown) is formed in shown structure.This photoresist such as by photoetching composition for cover grid stacking be exposed to recessed it An outer part (in this example, left side in figure), and expose grid stacking be exposed to recessed outside another part (in this example In, right one side of something in figure).It is then possible to photoresist is mask, to grid conductor layer 1035, second gate dielectric layer 1033 and floating boom Layer or electric charge capture layer 1031 carry out selective etch such as RIE.So, grid conductor layer 1035, second gate dielectric layer 1033 and Floating gate layer or electric charge capture layer 1031, in addition to staying the part within recessed, are photo-etched the part that glue blocks and are retained, As shown in figure 16.Subsequently, the electrical connection of grid stacking can be realized by this part.
According to another embodiment, it is also possible to further first grid dielectric layer 1029 is carried out selective etch such as RIE (in figure Not shown).Afterwards, photoresist can be removed.
It follows that the grid stacking of selector can be similarly formed.Such as, as shown in figure 17, can be shown in Figure 16 Structure on deposited oxide, and to its be etched back, to form the second sealing coat 1037.Before eat-back, can be to the oxygen of deposit Compound carries out planarization and processes such as CMP.Here, the end face of sealing coat 1037 may be located at end face and the end of the second channel layer 1009 Between face, this contributes to forming self aligned grid stacking.Due to first grid dielectric layer 1029, floating gate layer or electric charge capture layer 1031, the existence of the lamination of second gate dielectric layer 1033 and grid conductor layer 1035, can avoid the material of sealing coat 1037 to enter Enter grid to be accommodated stacking above-mentioned recessed in.
Afterwards, as shown in figure 18, floating gate layer or electric charge capture layer 1031, second gate dielectric layer 1033 and grid can be removed The lamination of conductor layer 1035, with discharge the second channel layer 1011 recessed in space, and form selector within this space Grid stacking, including first grid dielectric layer 1029 and grid conductor layer 1039.Here, remain first grid dielectric layer 1029, it is used as The gate dielectric layer of selector.But the disclosure is not limited to this.First grid dielectric layer can also be removed, and another for selector Outer formation gate dielectric layer.Likewise it is possible to the shape of grid stacking being adjusted, in order to follow-up interconnection makes.? In this example, grid stacking is shaped as grid conductor 1039 and extends towards right side.It is to be herein pointed out the grid of selector are situated between Matter layer need not be identical with first grid dielectric layer 1029, the grid conductor layer 1039 of selector and the grid conductor layer 1035 of memory element Need not be identical.
So, the grid of selector stacking can embed and be self-aligned to recessed in, thus with the second channel layer 1011 Whole height overlaps.Then, the grid length of selector is determined by the height of the second channel layer 1011.
It is then possible to as shown in figure 19, the structure shown in Figure 18 forms interlevel dielectric layer 1041.For example, it is possible to Deposited oxide also carries out planarization if CMP is to form interlevel dielectric layer 1049 to it.In interlevel dielectric layer 1049, can To form memory element and the respective source/drain region of selector and electrical contacts 1043-1～1043-4 of grid conductor layer. These contact sites by etching hole in interlevel dielectric layer 1041 and sealing coat, and can fill conductive material wherein As metal is formed.
Owing to grid conductor layer 1035,1039 is stretched beyond active area periphery, such that it is able to be readily formed corresponding contact site 1043-3、1043-2.Further, since the doped region in substrate 1001 extends beyond outside active area, such that it is able to easily landform Become corresponding contact portion 1043-4.
As shown in figure 19, memory element and the selector being vertically stacked is included according to the memory device of this embodiment Part.Memory element includes the first source drain the 1003, first channel layer 1005 and the second source drain being vertically stacked 1007 (or its underpart 1007-1).First channel layer 1005 is the most recessed, and grid stacking (1029/1031/1033/1035) are around first The periphery of channel layer 1005 is formed, and be embedded in this recessed in.Similarly, selector includes second be vertically stacked Source drain 1007 (or its top 1007-2), the second channel layer 1009 and the 3rd source drain 1011.Second channel layer 1009 is horizontal To recessed, grid stacking (1029/1039) around the periphery of the second channel layer 1009 formed, and be embedded in this recessed in.
It addition, as shown in the phantom line segments in figure, on stacked direction (vertical direction), the channel layer 1005 of memory element Scope between dopant profiles in two ends can be substantially with the scope occupied by grid conductor layer 1035 of memory element up and down Alignment.This contributes to reducing non-essential resistance.
In this example, it is shown that single memory element is stacked mutually with selector.But, the disclosure is not limited to this, can There to be more multiple memory cell in the vertical direction stacked on top of each other, thus constitute storage string.Furthermore it is also possible to arrange many on substrate Individual storage string, to form three-dimensional (3D) storage array.
Figure 20～27 showed according to the showing of part stage in the flow process manufacturing memory device of another embodiment of the disclosure It is intended to.
As shown in figure 20, on substrate 1001, the first source drain 1003-1, the first channel layer 1005-can be sequentially stacked 1, the second source drain 1003-2, the second channel layer 1005-2, the 3rd source drain 1007, triple channel layer 1009 and the 4th Source drain 1011.
In these layers, the first source drain 1003-1, the first channel layer 1005-1, the second source drain 1003-2 are used for limiting The active area of fixed first memory element, the second source drain 1003-2, the second channel layer 1005-2, the 3rd source drain 1007 times Portion 1007-1 is for limiting the active area of the second memory element.Here, the first memory element and the second memory element share second Source drain 1003-2.Certainly, the disclosure is not limited to this, can be respectively the first memory element and the second memory element arrange source/ Drop ply.First memory element can be identical with the second memory element respective lamination configuration.It addition, the 3rd source drain 1007 Top 1007-2 (such as, thickness is about 10-50nm), triple channel layer 1009 and the 4th source drain 1011 are used for limiting choosing Select the active area of device.
About substrate and the details of these layers, may refer to the explanation above in association with Fig. 1, do not repeat them here.Here, For the sake of illustrating conveniently, not shown hard mask layer.
It follows that the active area of selector can be limited.As it has been described above, as shown in figure 21, it is possible to use covering of composition Mould (not shown), successively to the 4th source drain 1011, triple channel layer 1009 and the 3rd source drain 1007 (here, the 3rd source/ The top 1007-2 of drop ply) carry out selective etch such as RIE.Furthermore it is also possible to make the periphery of triple channel layer 1009 relative to The top 1007-2 of the 3rd source drain and the periphery of the 4th source drain 1011 are recessed.Triple channel layer 1009 recessed in, Sacrificial gate 1015 can be formed, as shown in figure 22.To this, such as, may refer to the explanation above in association with Fig. 2-4.Alternatively, also To utilize the adulterant active layer of such as side wall form, the top 1007-2 of the 4th source drain 1011 and the 3rd source drain can be entered Row doping, above in association with as described in Fig. 5 and 6.
It follows that similar process can be carried out for memory element.As it has been described above, be the active area of protective seletion device (particularly source/drain region) unaffected in subsequent processes (especially for suppression adulterant cross-contamination), can be outside it Week forms protective layer (not shown).Then, as shown in figure 22, it is possible to use same mask, successively to the 3rd source drain 1007 Bottom 1007-1, the second channel layer 1005-2, the second source drain 1003-2, the first channel layer 1005-1 and the first source drain 1003-1 carries out selective etch such as RIE.It addition, the periphery of the second channel layer 1005-2 similarly can be made relative to the 3rd The bottom 1007-1 of source drain 1007 and the periphery of the second source drain 1003-2 are recessed, make outside the first channel layer 1005-1 Week is recessed relative to the periphery of the second source drain 1003-2 and the first source drain 1003-1 (or its top).At the first raceway groove Layer 1005-1 and the second channel layer 1005-2 recessed in, sacrificial gate 1021 can be formed, as shown in figure 23.To this, such as may be used To see the explanation above in association with Fig. 7 and 8.
Alternatively, it is also possible to utilize adulterant active layer, bottom 1007-1, the second source drain to the 3rd source drain 1007 1003-2 and the first source drain 1003-1 are doped, above in association with as described in Fig. 9 and 10.
Subsequently, sealing coat can be formed at active region, to realize electric isolution.Here, for coordinating following grid stacking Being formed, sealing coat divides multilamellar to be formed.
Such as, as shown in figure 24, sealing coat 1027-1 can be formed in the structure shown in Figure 23.This sealing coat 1027-1 End face may be located between end face and the bottom surface of the first channel layer 1005-1, this contributes to forming self aligned grid stacking.It After, sacrificial gate 1021 can be removed, with discharge the first semiconductor layer 1005-1 recessed in space.As it has been described above, this is simultaneously Sacrificial gate 1015 can also be removed.It is then possible at the recessed middle formation storage grid stacking G1 of the first channel layer 1005-1.? This, be only for the sake of illustrating conveniently, does not shows that the concrete laminated construction of storage grid stacking G1, and storage grid stack G1 and such as can wrap Include first grid dielectric layer, floating gate layer or electric charge capture layer, second gate dielectric layer and grid conductor layer, or can include folding successively The first metal layer, ferroelectric material layer, the second metal level, gate dielectric layer and the grid conductor layer put.At the second channel layer 1005-2 And triple channel layer 1009 respective recessed in, it is also possible to form similar lamination G1 '.The shape of grid stacking G1 can be entered Row sum-equal matrix, in order to follow-up interconnection makes.In this example, the shape that grid stack G1 is patterned in figure left side extension.Right This, such as, may refer to the explanation above in association with Figure 12-16.
Afterwards, as shown in figure 25, sealing coat 1027-2 can be formed in the structure shown in Figure 24.This sealing coat 1027-2 End face may be located between end face and the bottom surface of the second channel layer 1005-2, this contributes to forming self aligned grid stacking.Logical Cross and the same manner of above-mentioned formation grid stacking, can be at the recessed middle formation storage grid stacking G2 of the second channel layer 1005-2. Here, for the sake of only diagram is convenient, do not show that the concrete laminated construction of storage grid stacking G2, store grid stacking G2 the most permissible Including first grid dielectric layer, floating gate layer or electric charge capture layer, second gate dielectric layer and grid conductor layer.Storage grid stacking G1 and G2 Can have identical configuration.Equally, triple channel layer 1009 recessed in can form similar lamination G2 '.
If being also stacked more memory element, then can carry out in a comparable manner.Specifically, can be formed every Absciss layer, the end face of sealing coat is between end face and the bottom surface of the channel layer of a certain memory element.On this sealing coat, can be with shape Become to be self-aligned to the storage grid stacking of the channel layer of this memory element.Then, then form next sealing coat, the end face of this sealing coat It is between end face and the bottom surface of the channel layer of last layer memory element.On this sealing coat, can be formed and be self-aligned on this The storage grid stacking of the channel layer of one layer of memory element.By that analogy.
After the making of storage grid stacking completing memory element, the grid heap of selector can be similarly formed Folded.As shown in figure 26, can form sealing coat 1027-3, its end face is between the end face and bottom surface of triple channel layer 1009.Logical Cross and the same manner of above-mentioned formation grid stacking, G3 can be stacked at the recessed middle formation grid of triple channel layer 1009.Here, only For diagram convenient for the sake of, do not show that the concrete laminated construction of grid stacking G3, grid stacking G3 such as can include gate dielectric layer and Grid conductor layer.To this, may refer to the explanation above in association with Figure 17 and 18.
Then, as shown in figure 27, interlevel dielectric layer 1041, and shape wherein can be formed in the structure shown in Figure 26 Become each electrical contacts 1043-1～1043-6.To this, may refer to the explanation above in association with Figure 19.
As shown in figure 27, according in the memory device of this embodiment, store string (here it is shown that two) including multiple, Each storage string has the multiple memory element being sequentially stacked and (here it is shown that two memory element: 1003-1/1005-1/ 1003-2,1003-2/1005-2/1007-1) and it is stacked and placed on the selector (1007-2/1009/ above memory element 1011).In each storage string, the memory element on identical level is positioned at and is roughly parallel to being substantially the same in plane of substrate surface. More specifically, the respective source drain of memory element on identical level can be respectively by identical semiconductor layer shape with channel layer Become.Memory element on same level such as can be arranged in rows into two-dimensional array.Memory element on same level Respective grid stacking can one.Stack G1 or G2 by corresponding grid, corresponding one layer of memory element can be selected (to pass through G1 Next layer can be selected, last layer can be selected by G2)；It addition, by corresponding selector, can select in this layer special Fixed memory element.Preferably, the grid stacking G3 of the selector of same a line (or row) may be coupled to row electrode (or row electricity Pole), the source/drain region 1011 of the selector of same column (or row) may be coupled to row electrode (or row electrode).So, by phase The row electrode answered and row electrode, can select corresponding selector, and therefore select to store string accordingly.
Memory device according to disclosure embodiment can apply to various electronic equipment.Such as, memory device can be deposited Various programs, application and data needed for storage electronic device.Electronic equipment can also include matching with memory device Processor.Such as, processor can operate electronic equipment by allowing the program of storage in memory device.This electronic equipment Such as smart phone, computer, panel computer (PC), wearable smart machine, portable power source etc..
In the above description, the ins and outs such as the composition of each layer, etching are not described in detail.But It will be appreciated by those skilled in the art that and can form the layer of required form, region etc. by various technological means.It addition, be Formation same structure, those skilled in the art can be devised by method the most identical with process as described above. Although it addition, respectively describing each embodiment above, but it is not intended that the measure in each embodiment can not be favourable Be used in combination.
Embodiment the most of this disclosure is described.But, the purpose that these embodiments are merely to illustrate that, and It is not intended to limit the scope of the present disclosure.The scope of the present disclosure is limited by claims and equivalent thereof.Without departing from these public affairs The scope opened, those skilled in the art can make multiple replacement and amendment, and these substitute and amendment all should fall in the disclosure Within the scope of.

Claims (34)

1. a memory device, including the memory element being sequentially stacked on substrate and selector, wherein, memory element and choosing Select device the most all to include:
The first source drain, channel layer and the second source drain being sequentially stacked, wherein, channel layer includes and first, second source/drain The semi-conducting material that layer is different；And
The grid stacking formed around the periphery of channel layer, wherein, the grid stacking of memory element is storage grid stacking.
Memory device the most according to claim 1, wherein, the grid stacking of memory element includes that the first grid being sequentially stacked is situated between Matter layer, floating gate layer or electric charge capture layer, second gate dielectric layer and grid conductor layer, the grid stacking of selector includes being sequentially stacked Gate dielectric layer and grid conductor layer.
Memory device the most according to claim 1, wherein, outside the periphery of channel layer is relative to first, second source drain Week inwardly concaves.
Memory device the most according to claim 3, wherein, the channel layer of the grid stacking autoregistration memory element of memory element And/or the channel layer of the grid stacking autoregistration selector of selector.
Memory device the most according to claim 1, including multiple described memory element being sequentially stacked, wherein, selector Part is stacked and placed in the memory element of the top,
Wherein, for each memory element, its first source drain with under the second source drain one of memory element, it is second years old Source drain with on memory element first source drain one.
Memory device the most according to claim 5, including multiple by the multiple described memory element being sequentially stacked with described The storage string that selector is formed.
7. according to the memory device according to any one of claim 1-6, wherein, selector the first source drain and with choosing The second source drain selecting the immediate memory element of device is one.
Memory device the most according to claim 6, wherein,
In the plurality of storage string, respective first source drain of memory element of bottom is connected to public electrode,
In the plurality of storage string, the corresponding respective grid of memory element are stacked into one.
Memory device the most according to claim 1, wherein, channel layer includes single-crystal semiconductor material.
Memory device the most according to claim 1, wherein, channel layer is near the first source drain and the second source drain End has dopant profiles.
11. memory devices according to claim 10, wherein, on stacked direction, the channel layer of memory element relative The scope between dopant profiles in end and the scope substantial alignment occupied by grid conductor layer of memory element.
12. memory devices according to claim 3, wherein,
The grid stacking of memory element includes from the most recessed lateral extension portions extended laterally outward,
The grid stacking of selector includes from the most recessed lateral extension portions extended laterally outward,
Wherein, each memory element grid stacking lateral extension portions and selector grid stacking lateral extension portions in extremely Some are towards different direction horizontal expansions less.
13. memory devices according to claim 1, wherein, memory element and respective first source/drain of selector Layer, channel layer and the second source drain are the semiconductor layer at respective lower floor Epitaxial growth respectively.
14. memory devices according to claim 1, wherein, the grid stacking of memory element includes ferroelectric material.
15. memory devices according to claim 14, wherein, the grid stacking of memory element includes being sequentially stacked the first metal Layer, ferroelectric material layer, the second metal level, gate dielectric layer and grid conductor layer.
16. memory devices according to claim 15, wherein, ferroelectric material includes hafnium oxide, zirconium oxide, tantalum oxide, oxygen Change hafnium zirconium or hafnium oxide tantalum, the first metal layer and the second metal level include TiN.
17. memory devices according to claim 16, wherein, hafnium oxide includes HfO2, zirconium oxide includes ZrO2, tantalum oxide Including TaO2, hafnium oxide zirconium includes HfxZr1-xO2, hafnium oxide tantalum includes HfxTa1-xO2, wherein x value is the scope of (0,1).
18. memory devices according to claim 15, wherein, ferroelectric material includes the HfO containing Si2, HfO containing Al2、 BaTiO3、KH2PO4Or SBTi, the first metal layer and the second metal level include TiN.
19. 1 kinds of methods manufacturing memory device, including:
Substrate is sequentially stacked the of the first source drain of memory element, channel layer and the second source drain and selector One source drain, channel layer and the second source drain；
The first source drain, channel layer and the second source drain and the first source drain of selector, raceway groove in memory element Layer and the second source drain limit the active area of this memory device；And
Periphery rotating around the respective channel layer of memory element and selector forms memory element and the respective grid of selector Stacking, wherein, the grid stacking of memory element is storage grid stacking.
20. methods according to claim 19, wherein, define source region and also include:
The periphery making the channel layer of memory element inwardly concaves relative to the periphery of first, second source drain of memory element；With And
The periphery making the channel layer of selector inwardly concaves relative to the periphery of first, second source drain of selector.
21. methods according to claim 19, including being sequentially stacked respective first source drain of multiple memory element, ditch Channel layer and the second source drain,
Wherein, stacked first source drain of selector, channel layer and the second source drain in the memory element of the top,
Wherein, for each memory element, its first source drain with under the second source drain one of memory element, it is second years old Source drain with on memory element first source drain one.
22. according to the method according to any one of claim 19-21, wherein, defines source region and includes:
Each first source drain, channel layer and the second source drain are patterned into the part including multiple separation respectively, in each layer The plurality of part is along the stacked direction substantial alignment of these layers.
23. according to the method according to any one of claim 19-21, wherein, the first source drain of selector and with selection Second source drain of the immediate memory element of device is one.
24. according to the method according to any one of claim 19-21, wherein, arranges each first source/drain by epitaxial growth Layer, channel layer and the second source drain.
25. methods according to claim 20, wherein, define source region and include:
Successively the second source drain, channel layer and first source drain of selector is carried out selective etch, and make channel layer Periphery recessed relative to the periphery of first, second source drain, limit the active area of selector；
At the channel layer of selector relative to the sacrificial gate of the recessed middle formation selector of first, second source drain；
Successively the second source drain, channel layer and first source drain of memory element is carried out selective etch, and make channel layer Periphery recessed relative to the periphery of first, second source drain, limit the active area of memory element；And
At the channel layer of memory element relative to the sacrificial gate of the recessed middle formation memory element of first, second source drain.
26. methods according to claim 25, wherein, store list after forming the sacrificial gate of selector and limiting Before the active area of unit, the method also includes: form protective layer on the surface of first, second source drain of selector.
27. according to the method described in claim 25 or 26, and wherein, the active area of restriction is column, and the first of memory element The top of source drain is column and bottom extends beyond the periphery of cylindrical upper section.
28. methods according to claim 25, wherein, store list after forming the sacrificial gate of selector and limiting Before the active area of unit, the method also includes:
First source drain of selector and the surface of the second source drain are formed adulterant active layer；And
The adulterant in adulterant active layer is made to enter in first, second source drain of selector.
29. according to the method described in claim 25 or 28, and wherein, after forming the sacrificial gate of memory element, the method is also Including:
First source drain of memory element and the surface of the second source drain form another adulterant active layer；And
The adulterant in another adulterant active layer is made to enter in first, second source drain of memory element.
30. methods according to claim 25, wherein,
The grid stacking forming memory element includes:
Formation the first sealing coat around active area on substrate, wherein the end face of the first sealing coat is in the raceway groove of memory element Between end face and the bottom surface of layer；
Remove the sacrificial gate of memory element, with discharge the channel layer of memory element relative to first, second source drain recessed in Space；
Sequentially form first grid dielectric layer, floating gate layer or the electric charge capture layer of memory element on the first sealing coat, second gate is situated between Matter layer and grid conductor layer；And
Eat-back grid conductor layer, makes the end face top less than the channel layer of memory element of grid conductor layer part outside the female Face；
Further selective etch second gate dielectric layer and floating gate layer or electric charge capture layer, and
The grid stacking forming selector includes:
Forming the second sealing coat on the first sealing coat, wherein the end face of the second sealing coat is in the top of channel layer of selector Between face and bottom surface；
Remove the channel layer material layer relative to the recessed interior existence of first, second source drain of selector, to discharge selection The channel layer of device relative to first, second source drain recessed in space；
Second sealing coat sequentially forms gate dielectric layer and the grid conductor layer of selector；And
Eat-back grid conductor layer, makes the end face top less than the channel layer of selector of grid conductor layer part outside the female Face.
31. methods according to claim 30, also include:
In the operation of grid stacking forming memory element, the grid conductor layer of memory element is patterned into one part from corresponding female Enter to extend laterally outward,
In the operation of grid stacking forming selector, the grid conductor layer of selector is patterned into one part from corresponding female Enter to extend laterally outward.
32. 1 kinds of electronic equipments, including the memory device as according to any one of claim 1-18.
33. electronic equipments according to claim 32, also include the processor matched with described memory device.
34. electronic equipments according to claim 32, this electronic equipment include smart phone, computer, panel computer, can Dress smart machine, portable power source.
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