CN106158877B - Memory device and its manufacturing method and electronic equipment including the memory device - Google Patents

Memory device and its manufacturing method and electronic equipment including the memory device Download PDF

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CN106158877B
CN106158877B CN201610872345.5A CN201610872345A CN106158877B CN 106158877 B CN106158877 B CN 106158877B CN 201610872345 A CN201610872345 A CN 201610872345A CN 106158877 B CN106158877 B CN 106158877B
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layer
grid
processing hole
memory device
source drain
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CN106158877A (en
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朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels

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Abstract

Disclose a kind of memory device and its manufacturing method and the electronic equipment including the memory device.Memory device may include: the multiple first column active areas and multiple second column active areas upwardly extended on substrate, it is arranged as the first, second array respectively, every one first column active area includes being alternately stacked for source drain and channel layer, corresponding channel layer is in substantially the same plane in each first column active area, and corresponding source drain is in substantially the same plane, every one second column active area includes the active semiconductor layer integrally extended；Post-like conductive contact portion positioned at each second column active area lower part；The insulating layer formed around the periphery of each post-like conductive contact portion；It is in respectively with each plane where channel layer in substantially the same plane and the multilayer first around the periphery of each channel layer in respective planes stores grid stacking respectively；Multilayer second around each second column active area periphery stores grid and stacks.

Description

Memory device and its manufacturing method and electronic equipment including the memory device
Technical field
This disclosure relates to semiconductor field, and in particular, to memory device and its manufacturing method based on vertical-type device And the electronic equipment including this memory device.
Background technique
In horizontal type device such as Metal Oxide Semiconductor Field Effect Transistor (MOSFET), source electrode, grid and drain electrode Along the direction arrangement for being roughly parallel to substrate surface.Due to this arrangement, horizontal type device is not easy to further reduce.Not with this Together, in vertical-type device, source electrode, grid and drain electrode are along the direction arrangement for being approximately perpendicular to substrate surface.Accordingly, with respect to water Flat pattern device, vertical-type device are easier to reduce.
But for vertical-type device, it is difficult to grid length is controlled, especially for the channel material of monocrystalline.On the other hand, such as Fruit uses polycrystalline channel material, then relative to monocrystal material, channel resistance is greatly increased, to be difficult to stack multiple vertical-types Device, because this will lead to excessively high resistance.
Summary of the invention
In view of this, the purpose of the disclosure be at least partly to provide a kind of memory device based on vertical-type device and Its manufacturing method and electronic equipment including this memory device, wherein grid length can be controlled well.
According to one aspect of the disclosure, a kind of memory device is provided, comprising: formed on a substrate upward from substrate The multiple first column active areas and multiple second column active areas extended, wherein the first column active area is arranged as first gust Column, the second column active area are arranged as second array, and every one first column active area includes the alternating heap of source drain and channel layer Folded, the bottom of the stacking is source drain, and the top is source drain, and corresponding channel layer is in each first column active area In substantially the same plane, and corresponding source drain is in substantially the same plane, every one second column active area packet Include the active semiconductor layer integrally extended；Post-like conductive contact portion positioned at each second column active area lower part；It is led around each column The insulating layer that the periphery of electrical contacts is formed；It is in more in substantially the same plane with each plane where channel layer respectively Layer first stores grid and stacks, wherein each layer first stores grid and stacks respectively around the periphery of each channel layer in respective planes；And Multilayer second around each second column active area periphery stores grid and stacks.
According to another aspect of the present disclosure, a kind of method for manufacturing memory device is provided, comprising: be arranged on substrate Source drain and channel layer are alternately stacked, and the bottom of the stacking is source drain, and the top is source drain；In the stacking It is middle to form several processing holes；Via processing hole, the side wall exposed in processing hole from channel layer drives in dopant into channel layer, To form lateral dopant distribution in channel layer；Via processing hole, selective etch stack in channel layer, to stack In each channel layer in form the array in the multiple cell channel portions being separated from each other；Sky via processing hole, in the stacking It is formed in gap and is stacked for the storage grid of the first storage unit；Material in removal processing hole, to expose processing hole；Via processing Hole, selective etch stack in source drain, unit source/drain portion is respectively formed with the upper side and lower side in each unit groove, Wherein, the corresponding units source/drain portion of each unit groove and its upper side and lower side constitutes the first storage unit；Via processing Hole forms separation layer in the gap in the stacking；Material in removal processing hole, to expose processing hole；In processing hole The electrically conducting contact surrounded by insulating layer is formed on bottom；Side wall and above electrically conducting contact and insulating layer, in processing hole Upper formed stacks for the storage grid of the second storage unit, and the storage grid heap for the second storage unit is formed on side wall Filling is used for the active semiconductor layer of the second storage unit in folded processing hole.
According to another aspect of the present disclosure, a kind of electronic equipment, including above-mentioned memory device are provided.
In accordance with an embodiment of the present disclosure, channel region is limited by channel layer, so that grid length is determined by the thickness of channel layer.Channel Layer can for example be formed by epitaxial growth, so that its thickness can control well.It therefore, can control gate well It is long.In addition, channel layer can be single-crystal semiconductor material, high carrier mobility and low discharge current can have, to change It has been apt to device performance.Since vertical-type device can be relatively easily stacked on top of each other, so as to manufacture three-dimensional storage part, increase Big storage density.In addition, being additionally formed storage unit in processing hole, help to save chip area.In extra storage list The electrically conducting contact of first lower part helps to reduce the resistance of additional memory units and increases its operating current.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present disclosure, the above-mentioned and other purposes of the disclosure, feature and Advantage will be apparent from, in the accompanying drawings:
Fig. 1~19 (b) shows the schematic diagram of the process of the manufacture memory device according to the embodiment of the present disclosure；
Figure 20 (a) and 20 (b) shows the schematic diagram of the processing hole arrangement according to the embodiment of the present disclosure；
Figure 21 (a)~23 show part stage in the process according to the manufacture memory device of another embodiment of the disclosure Schematic diagram；
Figure 24 (a)~30 (b) shows sublevel in the middle part of the process according to the manufacture memory device of another embodiment of the disclosure The schematic diagram of section；
Figure 31 (a)~36 (b) shows sublevel in the middle part of the process according to the manufacture memory device of another embodiment of the disclosure The schematic diagram of section.
Through attached drawing, the same or similar appended drawing reference indicates the same or similar component.
Specific embodiment
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure.However, it should be understood that these descriptions are only exemplary , and it is not intended to limit the scope of the present disclosure.In addition, in the following description, descriptions of well-known structures and technologies are omitted, with Avoid unnecessarily obscuring the concept of the disclosure.
The various structural schematic diagrams according to the embodiment of the present disclosure are shown in the attached drawings.These figures are not drawn to scale , wherein some details are magnified for the purpose of clear expression, and some details may be omitted.It is shown in the drawings Various regions, the shape of layer and relative size, positional relationship between them are merely exemplary, in practice may be due to system It makes tolerance or technical restriction and is deviated, and those skilled in the art may be additionally designed as required with difference Shape, size, the regions/layers of relative position.
In the context of the disclosure, when one layer/element is referred to as located at another layer/element "upper", which can May exist intermediate layer/element on another layer/element or between them.In addition, if in a kind of direction In one layer/element be located at another layer/element "upper", then when turn towards when, which can be located at another layer/member Part "lower".
According to the memory device of the embodiment of the present disclosure be based on vertical-type device, therefore may include it is formed on a substrate from Substrate (for example, perpendicular to substrate surface) extends upwards multiple first column active areas and multiple second column active areas.Base In the column active area that these extend vertically, is stacked by forming grid around their peripheries, vertical device can be formed.Grid stacking can It to be storage grid stacking, such as may include floating gate or electric charge capture layer or ferroelectric material, to realize store function.Example Such as, storage grid stacking may include the first gate dielectric layer, floating gate layer or the electric charge capture layer being sequentially stacked, the second gate dielectric layer and Grid conductor layer, or may include the first metal layer being sequentially stacked, ferroelectric material layer, second metal layer, gate dielectric layer and grid Conductor layer.Then, vertical device forms vertical storage unit.Here, storage unit can be flash memory (flash) unit.
In accordance with an embodiment of the present disclosure, every one first column active area may include the alternating heap of source drain and channel layer Folded, the bottom of the stacking is source drain, and the top is also source drain.Each first column active area may include identical The number of plies, and corresponding channel layer in each first column active area (for example, the layer of the identical number of number from top to bottom, or under The up layer of the identical number of number) it may be in substantially the same plane (for example, they can be from identical semiconductor layer It is isolated), corresponding source drain may be in substantially the same plane (for example, they can be from identical semiconductor Layer is isolated).These layers can for example extend substantially parallel to substrate surface.
It is corresponding in the plane where channel layer, multilayered memory grid can be formed and stack (the hereinafter referred to as first storage grid heap It is folded).Each layer of storage grid stacking can be integrated, and (in fact also surround around the periphery of each channel layer in respective planes The periphery of second column active area, since first grid stacking is laterally extended on substrate, and the second column active area is on substrate It is vertical to extend).In this way, each channel layer, the source drain of its upper and lower two sides and corresponding first storage grid stacking constitute first Storage unit.The source/drain region of device can be formed in source drain, and the channel region of device can be formed in channel layer.Point Conductive channel can be formed by channel region between source/drain region in channel region both ends.
Then, grid length can be determined by the thickness of channel layer itself, rather than dependent on consumption as in routine techniques When etching to determine.Channel layer can for example be formed by epitaxial growth, so that its thickness can control well.Therefore, Grid length can be controlled well.Channel layer can be made of single-crystal semiconductor material, to improve device performance.Especially it is possible to Channel resistance is reduced, so that it is stacked on top of each other to be conducive to vertical-type device.Certainly, source drain is also possible to single-crystal semiconductor material. In this case, the single-crystal semiconductor material of channel layer and the single-crystal semiconductor material of source drain can be eutectic.
In accordance with an embodiment of the present disclosure, channel layer can have Etch selectivity relative to source drain, for example including with The different semiconductor material of source drain.In this way, being conducive to respectively handle channel layer and source drain.In addition, each source/drain Layer may include identical semiconductor material.
The periphery of channel layer can be inwardly concaved relative to the periphery of source drain, in this way, being formed by grid stacking can be embedding In channel layer relative to source drain it is recessed in, thus facilitate reduce grid stack with source drain be folded so as to reduce grid with Parasitic capacitance between source/drain.
In accordance with an embodiment of the present disclosure, every one second column active area may include the active semi-conductor material integrally extended Material.Second column active area can be solid, be also possible to hollow (so that cyclic structure is formed, wherein electricity can be filled Medium).It is stacked likewise it is possible to which the multilayer second around each second column active area periphery stores grid.Due to as described above, One storage grid stack in fact also around the second column active area, therefore the grid conductor in the first storage grid stacking can be used for Second storage grid stack.Therefore, it only needs to form another first gate dielectric layer, Ling Yi electricity in each second column active area periphery respectively Lotus capture layer, another second gate dielectric layer.Another first gate dielectric layer, another electric charge capture layer, another second gate are situated between Matter layer can extend in its substantially entire height around the periphery of each second column active area.Then, which is situated between Matter layer, another electric charge capture layer, another second gate dielectric layer can form the concentric ring structure around each second column active area.
Here, although another first gate dielectric layer, another electric charge capture layer, another second gate dielectric layer are in each second column It is extended continuously in the entire height of active area, but mainly work (their continuous shapes for its part opposite with grid conductor layer It is the reason of at mainly manufacturing process, as described below).That is, although another first gate dielectric layer, another electric charge capture layer, another One second gate dielectric layer is extended continuously in the entire height of the second column active area, but is mutually tied with corresponding grid conductor layer It closes, defines that multilayer second stores grid and stacks.These the second storage grid are stacked with the second column active area to cooperation, define the Two storage units.
In accordance with an embodiment of the present disclosure, the first column active area can be arranged as the first array (for example, be usually by row and Arrange the two-dimensional array of arrangement), the second column active area can be arranged as second array (for example, being usually to be arranged in rows Two-dimensional array).In addition, extending vertically on substrate as described above due to them and being limited respectively by the grid of multilayer stacking more Layer storage unit, so that the memory device can be three-dimensional (3D) array.In the 3D array, each column active area, which defines, to be deposited The string of storage unit.
Due to manufacture craft, as described below, the first array and second array can be nested with one another.For example, each One column active area can be located at the approximate centre of the grid of the two-dimensional array of the second column active area, each second column active area The approximate centre of the grid of the two-dimensional array of the first column active area can be located at.
It, can be in each second column active area in order to reduce the resistance of the second storage unit and therefore increase its operating current Lower section forms post-like conductive contact portion.In the periphery of post-like conductive contact portion, insulating layer can be formed to connect around post-like conductive Contact portion, to avoid unnecessary electrical connection.Electrically conducting contact can be held on it is electrically connected to the second column active area, and can To carry out required electrical connection (for example, being connected to earth potential or selection transistor) in its lower end.
This memory device can for example manufacture as follows.Specifically, source drain and channel layer can be set on substrate It is alternately stacked, the bottom of the stacking is source drain, and the top is source drain.For example, can be provided by epitaxial growth These layers.In epitaxial growth, the thickness of grown channel layer can control.In addition, original can be carried out in epitaxial growth Position doping, to realize required doping polarity and doping concentration.
For the ease of handling the layer inside stacking, several processing holes can be formed in a stack.These add Work hole can extend along the stacked direction (vertical direction) of stacking, and the side wall of all channel layers can be exposed in processing hole. In the following process, these processing holes are processing channels.
Channel layer in being stacked via processing hole, selective etch.In order to preferably control the etching to channel layer, Can be first via processing hole, the side wall exposed in processing hole from channel layer drives in dopant into channel layer, in channel layer It is middle to form lateral dopant distribution.Since dopant is spread from processing hole to their own surrounding, in certain time Later, the dopant profiles gradually decreased from processing hole to the position between them can be formed.It is then possible to via processing hole, Selective etch channel layer, doped portion especially therein.Thus it is possible to leave channel layer at the position processed between hole A part, and channel layer can be substantially removed at remaining position.The channel layer part left can be used for storing list The channel of member, referred to herein as cell channel portion.It, can be in each ditch by the layout (the first array can be referred to as) in setting processing hole The array (second array can be referred to as) in cell channel portion is left in channel layer.Moreover, because stacked side of the processing hole along stacking Extend to (vertical direction), therefore it is substantially the same to be diffused in the degree carried out in transverse direction in each channel layer, thus each channel layer The degree of middle etching is substantially the same.As a result, the array in the cell channel portion that each channel layer leaves is substantially consistent, and each Cell channel portion in array can be substantially aligned on the stacked direction (vertical direction) of stacking.
Storage grid can be formed in the gap in stacking and are stacked via processing hole.For example, the first grid can be sequentially formed Grid stacking is consequently formed in dielectric layer, floating gate layer or electric charge capture layer, the second gate dielectric layer and grid conductor layer.Due to upper and lower two sides The presence of source drain, grid stacking is filled at position of the gap between source drain i.e. where script channel layer, thus from right Standard is in cell channel portion.
At this point, the channel (being provided by cell channel portion) of storage unit, grid stack and source/drain region is (by cell channel portion The source drain of upper and lower provides) it is complete, but the source/drain region of each storage unit be connected to each other (at this point, each source/ Drop ply is other than the position in processing hole or continuous).For this purpose, (can first remove the material wherein filled via processing hole Such as above-mentioned grid stack, to expose processing channel) selective etch stack in source drain.Since selective etch is from processing Hole is carried out to their own surrounding, therefore, by controlling etch amount, can leave source/drain at the position between processing hole A part of layer, and channel layer can be substantially removed at remaining position.Certainly, herein can also first via processing hole, The side wall exposed in processing hole from source drain drives in dopant into source drain, to form lateral mix in source drain Miscellaneous dose of distribution, preferably to control the etching to source drain.Due to performed etching by identical processing hole or dopant expand It dissipates, etch and be consistent from these modes for carrying out around of processing holes (carrying out speed i.e. etching speed may be different, but It is to carry out path to etch path being substantially the same), thus left in the source drain part left and before channel layer What part was substantially aligned in the vertical direction.Then, the top for leaving part and being located at each unit groove of source drain On face and bottom surface, to form storage unit respective unit source/drain portion.
Then, separation layer can also be formed on device.Meanwhile separation layer can enter in stacking via processing hole, It is filled in the gap in stacking.Furthermore it is also possible to form various electrical contacts.
In accordance with an embodiment of the present disclosure, can also be further formed additional storage unit in processing hole (can be referred to as Second storage unit).For example, (for example above-mentioned separation layer of material wherein filled can be first removed, to expose processing in processing hole Hole) bottom form the electrically conducting contact that is surrounded by insulating layer.Side wall above electrically conducting contact and insulating layer, in processing hole Upper formed stacks for the storage grid of the second storage unit, and the storage grid for the second storage unit are then formed on side wall Filling is used for the active semiconductor layer of the second storage unit in the processing hole of stacking.Then, the active of the second storage unit is partly led Body layer can extend along the extending direction (vertical direction) in processing hole, and the storage grid of the second storage unit stack can be along adding The side wall (vertical direction) in work hole extends, and forms concentric ring structure around active semiconductor layer.
Here, on the side wall in processing hole, another first gate dielectric layer for the second storage unit, another can be only formed One electric charge capture layer and another second gate dielectric layer, without being additionally formed grid conductor layer.As described above, the first storage unit Grid stacking is filled at the position in the gap between source drain i.e. where script channel layer.Then, the grid of the first storage unit The side-walls of grid conductor layer in stacking in processing hole are exposed, and therefore with another first gate dielectric layer of the second storage unit, Another electric charge capture layer and the physical contact of another second gate dielectric layer, so as to serve as the grid conductor layer of the second storage unit. Therefore, within the same layer, the grid conductor of the first storage unit and the grid conductor of the second storage unit can be integrated.
In addition, the extending direction of grid conductor layer in the first storage unit is (that is, the extending direction of channel layer, such as substantially Be parallel to the direction of substrate surface) with another first gate dielectric layer, another electric charge capture layer and another in the second storage unit Extending direction (that is, the extending direction in processing hole, vertical direction) intersection (for example, vertical) of second gate dielectric layer.Then, grid are led Body layer, corresponding to channel region is defined at the position of channel layer, and (can have in active semiconductor layer in the two sides of channel region The position of the first, second source drain is corresponded respectively in the semiconductor layer of source) form source/drain region.
The disclosure can be presented in a variety of manners, some of them example explained below.
Fig. 1~19 (b) shows the schematic diagram of the process of the manufacture memory device according to the embodiment of the present disclosure.
As shown in Figure 1, providing substrate 1001.The substrate 1001 can be various forms of substrates, including but not limited to body Semiconductive material substrate such as body Si substrate, semiconductor-on-insulator (SOI) substrate, compound semiconductor substrate such as SiGe substrate Deng.In the following description, for convenience of description, it is described by taking body Si substrate as an example.
In substrate 1001, such as by ion implanting, form well region 1001w.Well region 1001w may then act as depositing The common ground potential face of memory device, the source/drain region of the respective lower layer of lowest level storage unit may be coupled to this in memory device Common ground potential face.If storage unit is n-type device, well region 1001w can be doped to N-shaped；If storage unit is p-type Device, then well region 1001w can be doped to p-type；If storage unit is no junction device, well region 1001w can be doped to The identical polarity of channel region.
On substrate 1001, the first source drain 1003, the first channel layer can be sequentially formed for example, by epitaxial growth 1005, the second source drain 1007, the second channel layer 1009 and third source drain 1011.For example, for p-type device, the first source/ Drop ply 1003, the second source drain 1007 and third source drain 1011 respectively may include suitable semiconductor material such as SiGe (atomic percent of Ge can be about 10-40%), with a thickness of about 20-50nm；First channel layer 1005 and the second channel layer 1009 respectively may include the semiconductor material such as Si different from source drain 1003,1007,1011, with a thickness of about 10-100nm. Lattice constant of SiGe in the case where no strain is greater than lattice constant of Si in the case where no strain.Source drain and The material selection of channel layer is without being limited thereto, may include other semiconductor materials for being capable of providing appropriate Etch selectivity.For example, For n-type device, each source drain may include Si:C (atomic percent of C can be about 0.1-5%), with a thickness of about 20- 50nm；Each channel layer may include Si, with a thickness of about 10-100nm.Lattice constant of Si:C in the case where no strain is less than Lattice constant of Si in the case where no strain.Certainly, the present disclosure is not limited thereto.For example, each channel layer may include with source/ The identical component of drop ply, but semiconductor material that constituent content is different (for example, be all SiGe, but the wherein atom hundred of Ge Divide than different), as long as channel layer has Etch selectivity relative to source drain.
When growing each source drain 1003,1007,1011, they can be carried out with doping in situ, to subsequently form Source/drain region.For example, n-type doping can be carried out for n-type device；For p-type device, p-type doping can be carried out；For no knot Device can be doped to polarity identical with channel layer.
In addition, they can also be carried out with doping in situ, so as to adjusting means threshold when growing channel layer 1005,1009 Threshold voltage (Vt).For example, p-type doping can be carried out for n-type device；For p-type device, n-type doping can be carried out；For Without junction device, polarity identical with source drain area can be doped to.
In this example, the first source drain 1003 is in addition grown on substrate 1001.But the present disclosure is not limited to This.For example, the first source drain can be formed by substrate 1001 itself.Further, it is also possible to formed more source drains and Channel layer, to form the storage unit of more layers.
In addition, the purpose of for the convenience of composition in subsequent processes and offer stop-layer appropriate, in this grown A little semiconductor layers can also form hard mask.For example, it is (thick to sequentially form oxide (for example, silica) layer 1013 Degree for example, about 2-10nm) and nitride (for example, silicon nitride) layer 1015 (thickness is, for example, about 10-100nm).
Then, processing hole can be limited.As shown in the top view of Fig. 2, photoresist can be formed on the structure shown in figure 1 1017.By photoetching (exposure and imaging), photoresist 1017 is patterned into the nitride under exposing at the position in processing hole Layer 1015.About the position setting in processing hole, illustrate in detail further below.
Then, as shown in Fig. 3 (a) (sectional view of AA ' line along Fig. 2) and 3 (b) (sectional views of BB ' line along Fig. 2), Photoresist, downward aperture can be passed through.It specifically, can successively selective etch such as reactive ion etching (RIE) nitride Layer 1015, oxide skin(coating) 1013, third source drain 1011, the second channel layer 1009, the second source drain 1007, the first channel layer 1005 and first source drain 1003, to form processing hole.For example, RIE can along be approximately perpendicular to the direction of substrate surface into Row, to obtain the processing hole extended along the direction for being approximately perpendicular to substrate surface.Later, photoresist 1017 can be removed.? In the example, a part of first source drain 1003 is left in the bottom in processing hole, to better contact with earth potential face. But the present disclosure is not limited thereto.For example, processing hole can run through the lamination of channel layer and source drain.These processing holes are formed pair The processing channel that each layer is handled in stacking.
Then, it is formed as shown in Fig. 4 (a) and 4 (b), such as through deposit, in the structure shown in Fig. 3 (a) and 3 (b) solid Phase dopant active layer 1201.For example, dopant active layer 1201 may include oxide, and for example pass through doping in situ in deposit And dopant is had, with a thickness of about 2-10nm.Impurity in dopant is, for example, B, P or As, preferably As, and concentration can be about 0.01%-10%.Here, the selection of dopant is to facilitate the subsequent selective etch to channel layer.If necessary In addition words, can also cover one layer of diffusion barrier layer (not shown), in dopant active layer 1201 to prevent in subsequent annealing Dopant is to external diffusion in processing.
Then, as shown in Fig. 5 (a) and 5 (b), selective etch RIE can be carried out to dopant active layer 1201.RIE can be with It carries out along the direction for being approximately perpendicular to substrate surface, so as to remove the lateral extension portions of dopant active layer 1201, and stays Its lower vertical extension.Then, dopant active layer 1201 is stayed in side wall (spacer) form on the side wall in processing hole.It connects , it can be made annealing treatment, the dopant in dopant active layer 1201 be driven in channel layer 1005,1009, in figure Arrow shown in.Later, dopant active layer 1201 can be removed.Certainly, dopant can also enter source drain 1003,1007, In 1011.It can control the concentration and diffusing capacity of dopant, so that the doping pole of source drain 1003,1007,1011 will not be changed Property.
Here, can control dopant drives in degree, it is dense to form certain transverse direction in each channel layer 1005,1009 Degree distribution.Here, by the setting in conjunction with the description processing of Figure 20 (a) and 20 (b) hole and corresponding diffusion effect.
As shown in Figure 20 (a), substrate may include memory cell areas and contact zone, and it is single that storage is formed in memory cell areas Member, and various electrical contacts are formed in contact zone.Certainly, substrate can also include other regions, such as be used to form correlation Circuit region of circuit etc..
In accordance with an embodiment of the present disclosure, on memory cell areas, process hole density can be set such that via Processing hole was driven in into channel layer after dopant given time, formed in the part that channel layer is located at memory cell areas etc. Concentration face can limit the island portion of isolation.As shown in the arrow in Figure 20 (a), diffusion will from each processing hole towards surrounding into Row.Do not consider directionality (i.e., it is believed that diffusion is isotropic), then at any one time, spread range achieved (or Say diffusingsurface) it is circle centered on processing hole, as shown in the virtual coil in figure.The size of the range of scatter is (that is, the half of circle Diameter) it can be controlled by diffusing capacity (for example, diffusion time).By controlling diffusing capacity, can to exist in channel layer The lateral concentration distribution being gradually reduced from from each processing hole towards the position between them.Thus it is possible to exist such etc. dense Degree face is relatively high doping concentration on the outside of the isoconcentration face, and is relatively low doping on the inside of the isoconcentration face Concentration.Here, so-called " relatively high " and " relatively low " is depending on Etch selectivity, that is, doping concentration is relatively High part can be relatively low relative to doping concentration part by selective etch.In this example, Si channel layer with And in the case that As is adulterated, such as the isoconcentration face can be about 1E18-1E19cm-3Isoconcentration face.
In addition, the density for processing hole can be set such that in the given period septal fossula channel layer position on contact zone It is substantially all in the part of contact zone with relatively high doping concentration.More specifically, relative to memory cell areas, in contact zone It more thickly arranges in upper processing hole.Certainly, in order to provide support in subsequent processes for source drain, in certain parts of contact zone In, it also can reduce the density in processing hole, so that there may be the isoconcentrations being similar in memory cell areas in these sections Face.
The array (lattice array in figure) and island portion defined by isoconcentration face that Figure 20 (b) diagrammatically illustrates processing hole Array (the "×" array in figure) between relationship.The conventional two-dimensional storage cell array being arranged in rows the case where Under, processing hole can be arranged as corresponding two-dimensional array.The two arrays can be nested with one another.More specifically, island portion is located at The approximate centre of corresponding processing grid of holes, and process the approximate centre that hole is located at corresponding island portion grid.
In this example, processing grid of holes is quadrangle.But the present disclosure is not limited thereto.Processing grid of holes can also be with It is other shapes, such as triangle or other polygons, corresponding island portion can be at its substantially geometric center.Certainly, Processing hole is also not necessarily limited to circle, is also possible to other shapes, preferably regular polygon, more convenient in design layout in this way.
Then, as (Fig. 6 (a) is top view, and Fig. 6 (b) is the section of the AA ' line along Fig. 6 (a) for Fig. 6 (a), 6 (b) and 6 (c) Figure, Fig. 6 (c) is the sectional view of the BB ' line along Fig. 6 (a)) shown in, it can be via processing hole, (relative to source drain) selectivity Etch the part that doping concentration is relatively high in channel layer 1005,1009.For example, can choose suitable etchant, to ditch The etching (much) of the relatively high part of doping concentration is greater than to source drain (in the example in channel layer (in this example, Si) In, SiGe) etching and (much) be greater than the part relatively low to doping concentration in channel layer etching.
Thus it is possible to form the multiple portions being separated from each other in each channel layer 1005,1009 (referring to the vertical view of Fig. 6 (a) The sectional view in dotted line frame and Fig. 6 (c) in figure), these parts correspond to above-mentioned isoconcentration face, and may then serve as depositing The cell channel portion of storage unit.
As described above, the major part of channel layer 1005,1009 is removed, and is only stayed after the etching by certain time Under some isolation island portion, being used as cell channel portion (may be used for structure branch in contact zone there is also some island portions Support).Since processing hole passes vertically through lamination, so island portion left in each channel layer position (referring to fig. 20 (b), Positioned at corresponding processing hole pattern center of a lattice) it is roughly the same, therefore these island portions are substantially right each other in the vertical direction It is quasi-.
In addition, leaving space (space occupied by script channel layer) between source drain 1003,1007,1009. Grid stacking can be formed in these spaces.To which grid stacking can be self-aligned to corresponding cell channel portion.
It, can be via processing hole, (relative to channel layer) selectivity as shown in Fig. 7 (a) and 7 (b) for the convenience of processing Etch source drain 1003,1007,1011.Removal due to channel layer as described above between source drain so that leave sky Between, so etching agent can enter in these spaces via processing hole.Therefore, it is carved around with when etching channel layer from processing hole Erosion is different, and source drain is mainly by abatement thickness in the etch step.Thus it is possible to increase the gap between source drain, Facilitate the then packing material in these gaps.
Then, as shown in Fig. 8 (a) and 8 (b), storage grid heap can be formed in the gap in stacking via processing hole It is folded.For example, the first gate dielectric layer 1019, floating gate layer or electric charge capture layer 1021, the second gate dielectric layer 1023 can be sequentially formed And grid conductor layer 1025.For example, the first gate dielectric layer 1019 may include high-K gate dielectric such as HfO2, with a thickness of about 1-10nm； Floating gate layer or electric charge capture layer 1021 may include floating gate material such as metal or charge-trapping material such as nitride, with a thickness of about 1- 20nm；Second gate dielectric layer 1023 includes high-K gate dielectric such as HfO2, with a thickness of about 1-10nm；Grid conductor layer 1025 may include Metal gate conductor.Here, the first gate dielectric layer 1019, floating gate layer or electric charge capture layer 1021, the formation of the second gate dielectric layer 1023 Ground is relatively thin, can substantially be conformally formed；Grid conductor layer 1025 formed it is thicker, so as to fill up stack in gap.In addition, Between second gate dielectric layer 1023 and grid conductor layer 1025, work function regulating course (not shown) can also be formed.
As shown in Fig. 8 (b), the grid being thusly-formed stack the position for occupying channel layer, to be self-aligned to each unit channel Portion 1005,1009.Moreover, in same channel layer, since cell channel portion 1005,1009 is isolated island portion, and the layer In occupied by remaining position stacks by grid.Therefore, from top view, grid are stacked in the channel layer integrally, and are surrounded Each unit groove 1005,1009.
Alternatively, grid stacking may include ferroelectric material.For example, grid stacking may include the first metal being sequentially stacked Layer, ferroelectric material layer, second metal layer, gate dielectric layer and grid conductor layer (not shown).For example, ferroelectric material may include oxygen Change hafnium such as HfO2, zirconium oxide such as ZrO2, tantalum oxide such as TaO2, hafnium oxide zirconium HfxZr1-xO2(the wherein range that x value is (0,1)) Such as Hf0.5Zr0.5O2, hafnium oxide tantalum HfxTa1-xO2(the wherein range that x value is (0,1)) such as Hf0.5Ta0.5O2, HfO containing Si2、 HfO containing Al2、BaTiO3、KH2PO4Or SBTi, the first metal layer and second metal layer respectively may each comprise TiN.This feelings Under condition, the first metal layer, ferroelectric material layer, second metal layer, gate dielectric layer can be sequentially formed via processing hole, these layers can To be formed relatively thin, can substantially be conformally formed.Furthermore it is possible to form grid conductor layer via processing hole, which can be formed Must be thicker, to fill up the gap in stacking.
It is equally filled by grid stacking in processing hole.For further operating, as shown in Fig. 9 (a) and 9 (b), it can empty and add Work hole.It specifically, can successively selective etch such as RIE grid conductor layer 1025, the second gate dielectric layer 1023, floating gate layer or charge Trapping layer 1021 and the first gate dielectric layer 1019.Due to the presence of hard mask 1015, the grid stacking processed in hole is removed, and its Grid stacking at remaining position especially in memory cell areas is retained.
Next, the source/drain portion of each storage unit can be separated.It, can be via processing as shown in Figure 10 (a) and 10 (b) Hole, (being stacked relative to channel layer and grid) selective etch source drain 1003,1007,1011.Figure 20 (a) can also be referred to. As shown in the arrow in Figure 20 (a), etching will be carried out from each processing hole towards surrounding.Do not consider directionality (i.e., it is believed that etching is It is isotropic), then at any one time, etching range achieved is the circle centered on processing hole, such as the void in figure Shown in coil.The size (that is, radius of circle) of the etching range can be controlled by etch amount (for example, etch period).It is logical Control etch amount is crossed, the etching range in each processing hole can be made to limit the island residual asked for being located at processing hole.In addition, connecing It touches in area, the density for processing hole is larger, so that the part that source drain is located at contact zone can substantially be completely removed.
Certainly, in order to preferably control the etching to source drain, can have and similarly drive in dopant into source drain. For example, dopant active layer can be formed on the side wall in processing hole, and pass through annealing in the structure described in Fig. 9 (a) and 9 (b) To drive in dopant into source drain.The similar of dopant can be identical as the doping type of source drain.For example, for N-shaped Device, can be used n-type dopant such as As or P, and concentration can be about 0.01%-5%；For p-type device, p-type can be used Dopant such as B, concentration can be about 0.01%-5%.Later, dopant active layer can be removed.Driving in for dopant can be The dopant profiles as described in above in conjunction with Figure 20 (a) and 20 (b) are formed in source drain, to help to be formed in source drain The island portion of isolation.Certainly, dopant can also enter in channel layer 1005,1009.It can control the concentration and expansion of dopant Amount is dissipated, so that the doping polarity of channel layer 1005,1009 will not be changed.
Then, in each source drain 1003,1007,1011, some isolated island portions are left, they, which are subsequently acted as, deposits The unit source/drain portion of storage unit.As described above, the position in these island portions is determined by the position for processing hole, therefore their position It sets substantially consistent with the position in cell channel portion.That is, unit source/drain portion is substantially right in the vertical direction with cell channel portion It is quasi-.In addition, can be relatively fewer to the etch amount of source drain 1003,1007,1011, so that cell channel portion is relative to corresponding Unit source/drain portion it is horizontally recessed.
For p-type device, after rie, do not having since lattice constant of SiGe in the case where no strain is greater than Si There is the lattice constant in the case where strain, strain is generated in Si, this strain, which can make the hole mobility of Si be greater than it, not to be had The effective mass of the light hole of hole mobility or Si in the case where strain is less than its light sky in the case where no strain The concentration of the light hole of the effective mass or Si in cave is greater than the concentration of its light hole in the case where no strain, and then makes p The on-state current of type device increases and therefore enhances the performance of p-type device.Alternatively, for n-type device, after rie, by It is less than lattice constant of Si in the case where no strain in lattice constant of Si:C in the case where no strain, is produced in Si Raw strain, this strain can make the electron mobility of Si greater than the electricity of its electron mobility or Si in the case where no strain The effective mass of son is less than the effective mass of its electronics in the case where no strain, and then makes the on-state current of n-type device Increase and the performance of n-type device is enhanced with this.
In addition, this selection can increase if SiGe is selected to use Si as source drain material as channel layer materials The on-state current of p-type device, and can reduce the off-state current of p-type device, to enhance the performance of p-type device.Reason exists It is greater than the forbidden bandwidth of SiGe in the forbidden bandwidth of Si, and SiGe hole mobility is greater than the hole mobility of Si.
As shown in Figure 10 (b), the island portion being aligned on vertical direction in each source drain and channel layer constitutes a series of Column active area (1003/1005/1007/1009/1011), these column active areas are formed as shown in "×" in Figure 19 (b) Array.Around each column active area, forms multilayered memory grid and stack (1019/1021/1023/1025).As described above, each layer is deposited Storage grid stacking is self-aligned to corresponding channel layer 1005,1009.
Therefore, in memory cell areas, the vertical string of storage unit is formd, each storage unit includes being sequentially stacked Unit source/drain portion, cell channel portion and unit source/drain portion.Due to shared cell source/drain portion between adjacent storage unit, institute It is serially connected together with every a string of storage units.
In this way, completing the manufacture of storage unit in memory cell areas.But at this point, the space in processing hole is waste 's.In order to avoid this waste, in accordance with an embodiment of the present disclosure, additional storage unit can also be formed in processing hole.Example Such as, this can be carried out as follows.
Since there are still a large amount of gaps in currently stacking, as shown in Figure 10 (a) and 10 (b), electric Jie can be filled thereto Material, to realize structural support and required electric isolution.For example, as Figure 11 (a) and 11 (b) shown in, can via processing hole, Filling dielectric material in gap into stacking, to form interlevel dielectric layer 1027.For example, can by techniques such as ALD, Carry out deposited oxide.Here, interlevel dielectric layer 1027 preferably exceeds the top surface of hard mask 1015, and it can be carried out flat Smoothization processing such as chemically mechanical polishing (CMP).
It is equally filled by interlevel dielectric layer 1027 in processing hole.In order to make additional storage unit in processing hole, Processing hole can be emptied.Additionally, it is desirable that forming additional storage unit in memory cell areas, and do not formed in contact zone Storage unit, it is possible to only empty the processing hole in memory cell areas.For this purpose, such as Figure 12 (a), 12 (b) and 12 (c) (Figure 12 (a) be the AA ' line along Figure 12 (c) sectional view, Figure 12 (b) is the sectional view of the BB ' line along Figure 12 (c), and Figure 12 (c) is to overlook Figure) shown in, it can use photoresist 1101 and cover contact zone (processing hole especially therein), and expose memory cell areas.So Afterwards, the property of can choose etching such as RIE interlevel dielectric layer 1027.Then, processing hole is exposed.Later, photoresist can be removed 1101。
Then, as shown in figure 13, insulating layer 1301 can be formed on the side wall in processing hole.For example, insulating layer 1031 can To include low-K dielectric such as oxide, nitride etc., with a thickness of about 3-10nm.This insulation layers can such as pass through side wall shape It is formed on the side wall in processing hole at technique letter.It is then possible to be formed with the bottom in the processing hole of insulating layer 1301 on side wall Portion forms electrically conducting contact 1303.For example, can be then etched back by filling such as depositing conductive material into processing hole 1301 Conductive material, to form electrically conducting contact 1303.Conductive material is for example suitable for the metal such as W or Cu of contact portion, and/or doping Semiconductor such as Si, SiGe or Ge.Semiconductor such as polysilicon can deposit while carry out doping in situ, and doping type can be with Identical as the doping type of the active semiconductor layer subsequently formed, concentration is, for example, about 1E18-5E21cm-3.Electrically conducting contact 1303 top surface can be between two layers adjacent of grid conductor layer, i.e. the grid conductor top surface of the grid conducting bottom side on upper layer and lower layer Between.
Then, as (Figure 14 (a) is the sectional view of the AA ' line along Figure 14 (b) to Figure 14 (a) and 14 (b), and Figure 14 (b) is to overlook Figure) shown in, the additional memory units of vertical-type can be formed in processing hole.For example, can select insulating layer 1301 Property etching.Due to the presence of electrically conducting contact 1303, insulating layer 1301 can be with electrically conducting contact 1303 substantially with high after etching. It is then possible to which the side wall around processing hole sequentially forms the additional first grid above insulating layer 1301 and electrically conducting contact 1303 Dielectric layer 1103, additional electric charge capture layer 1105 and the second additional gate dielectric layer 1107.Side wall of these layers in processing hole Upper extension, such as can be formed according to side wall (spacer) technique.For example, the first additional gate dielectric layer 1103 may include High-K gate dielectric such as HfO2, with a thickness of about 1-10nm；Additional electric charge capture layer 1105 may include charge-trapping material as nitrogenized Object, with a thickness of about 1-20nm；The second additional gate dielectric layer 1107 includes high-K gate dielectric such as HfO2, with a thickness of about 1-10nm.Such as Shown in top view in Figure 14 (b), these layers can be formed as concentric ring knot (around the active semiconductor layer 1109 subsequently formed) Structure.It is then possible to form active semiconductor layer 1109.For example, can deposit one layer is not enough to fill up remaining space in processing hole Polysilicon layer (for example, with a thickness of about 4-15nm).It is depositing simultaneously, doping in situ, doping concentration can be carried out to polysilicon For example, about 1E17-1E19cm-3.Later hollow structure can be filled up with dielectric substance 1305 such as oxide or nitride.Then, Can carry out planarization process such as CMP (stopping at nitride layer 1015), thus remove polysilicon and dielectric substance be located at plus Part except work hole, remaining polysilicon form active semiconductor layer 1109.
Here, active semiconductor layer 1109 is hollow.But the present disclosure is not limited thereto.For example, can will process in hole Remaining space in fill up source semiconductor layer 1109, thus active semiconductor layer 1109 can be it is solid.
Grid conductor layer 1025 is via the second additional gate dielectric layer 1107, additional electric charge capture layer 1105 and additional the One gate dielectric layer 1103 can limit channel region in active semiconductor layer 1109, as shown in the dotted line frame in figure.And in channel The two sides (for example, position corresponding with the interlevel dielectric layer 1027 i.e. source drain of script) in area, can form source/drain region. Then, the source/drain region of channel region and its upper and lower two sides forms additional storage unit, as shown in the virtual coil in Figure 14 (a). Due to being stacked multi-layer gate conductor layer 1025 on substrate, it is correspondingly led in the active semiconductor layer 1109 extended vertically Caused multiple stacked additional memory units, their own active area integrally extends, thus it is concatenated with one another together.
As shown in Figure 14 (a) and 14 (b), since semiconductor layer 1109 forms a series of column active areas, these columns Active area forms the array as shown in " " in Figure 20 (b).Around each column active area, forms multilayered memory grid and stack (1107/ 1105/1103/1025；Here, the layer that storage grid stack is limited by grid conductor layer 1025, although 1107/1105/1103 around column The surface of shape active area 1109 integrally extends).
Alternatively, the storage grid stacking of additional memory units also may include ferroelectric material.For example, grid stacking may include The first metal layer, ferroelectric material layer, second metal layer, gate dielectric layer and the grid conductor layer (not shown) being sequentially stacked.For example, Ferroelectric material may include hafnium oxide such as HfO2, zirconium oxide such as ZrO2, tantalum oxide such as TaO2, hafnium oxide zirconium HfxZr1-xO2(wherein x Value is the range of (0,1)) such as Hf0.5Zr0.5O2, hafnium oxide tantalum HfxTa1-xO2(wherein x value be (0,1) range) such as Hf0.5Ta0.5O2, HfO containing Si2, HfO containing Al2、BaTiO3、KH2PO4Or SBTi, the first metal layer and second metal layer are respectively It may each comprise TiN.In this case, gate dielectric layer, second metal layer, ferroelectricity can be sequentially formed on the side wall in processing hole Material layer and the first metal layer, for example formed as the form of side wall.Furthermore it is possible to be filled in the space that these layers are surrounded Source semiconductor layer such as polysilicon.
In this way, just completing the manufacture of storage unit in memory cell areas.Then, various electrical contacts can be manufactured with reality Existing required electrical connection.
In addition, form the channel layer island portion for structural support in contact zone if as discussed above, then can be with These channel layer island portions are removed, to reduce possible leakage between capacitor or grid.For example, the processing in contact zone can be emptied Hole, and separation layer is removed via processing hole, channel layer island portion is then removed again.Then, then via processing hole filling dielectric Material is to complete separation layer.
In order to protect storage unit, the additional memory units especially formed in processing hole are (because the upper end is currently sudden and violent It is exposed to outer), can be in Figure 14 as shown in Figure 15 (a) and 15 (b) (they being the section of AA ' line and BB ' line along Figure 14 (b) respectively) (a) and in structure shown in 14 (b) protective layer 1111 is formed.For example, can be the nitride of about 5-150nm, shape with deposition thickness At the protective layer 1111.
Next, electrical contacts can be formed in interlevel dielectric layer 1027.For cubical array, this field exists more Kind mode interconnects to make.It is patterned into ladder-like for example, the grid in contact zone can be stacked, be stacked to form each layer grid Electrical contacts.A specific example is described below.
For example, as shown in Figure 16 (a) and 16 (b), such as using photoresist (not shown), selective etch such as RIE is most upper Each material layer on the grid conductor layer 1025 of layer.Then, as shown in Figure 17 (a) and 17 (b), modify photoresist, make its towards Memory cell areas retraction, and each material layer on the grid conductor layer 1025 of selective etch such as RIE top layer.Then, as schemed Shown in 18 (a) and 18 (b), photoresist is further modified, it is made further to bounce back towards memory cell areas, and selective etch is such as Each material layer on the grid conductor layer 1025 of RIE top layer.In this way, grid conductor layer is just formed as stairstepping.This field skill Art personnel know that multilayer stacked up and down is formed as stairstepping in edge by multiple technologies, and this is not described in detail here.
It, can be with deposit dielectric material (for example, the material with interlevel dielectric layer 1027 as shown in Figure 19 (a) and 19 (b) It is identical), to constitute interlevel dielectric layer 1029 together with remaining interlevel dielectric layer 1027.In interlevel dielectric layer 1029 In, the electrical contact of (and the source/drain region for therefore arriving all lowest level storage units) common ground potential face 1001w can be formed Portion 1031-1,1131-1 to electrical contacts 1031-2,1031-3,1131-2,1131-3 of each layer grid conductor 1025, and are arrived Electrical contacts 1031-4,1031-5,1131-4,1131-5,1131-6 of the source/drain region of each top layer's storage unit.This electricity Contact portion can fill conductive material such as W by the formation contact hole in interlevel dielectric layer and wherein to make.
Then, memory device according to this embodiment has been obtained.As shown in Figure 19 (a) and 19 (b), which can be with It (in this example, is illustrated only two layers), each memory cell layers include the first storage unit including multiple memory cell layers The second array of first array and the second storage unit (does not include in this example, second depositing in undermost memory cell layers Storage unit).As combined shown in Figure 20 (a) and 20 (b) above, the first array and second array can be nested with one another.
As shown in Figure 19 (b), every one first storage unit includes unit source/drain portion, cell channel portion, unit source/drain The lamination in portion.First storage unit connects bunchiness in the vertical direction, is connected to corresponding electrical contacts in upper end, connects in lower end It is connected to common ground potential plane.The respective grid stacking of the first storage unit in each layer is integrated.
As shown in Figure 19 (a), every one second storage unit includes by corresponding grid conductor 1025 in active semiconductor layer The channel region limited in 1109 and the source/drain region positioned at channel region two sides.The same active semi-conductor extended along the vertical direction Each second storage unit connects bunchiness in the vertical direction in layer 1109, corresponding electrical contacts is connected in upper end, in lower end It is connected to common ground potential plane.The grid conductor of the second storage unit in each layer is led by the grid of the first storage unit in this layer Body provides.
By arriving the electrical contacts of grid conductor, it can choose a certain memory cell layers.In addition, by source and drain contacts, it can To select a certain memory cell string.
Here, the grid stacking of two kinds of storage units can be same type or different type.For example, the first storage unit Grid stacking can be floating gate or charge trap-type, and the grid stacking of the second storage unit can be charge trap-type；First storage is single The grid stacking of member can be floating gate or charge trap-type, and the grid stacking of the second storage unit can be ferroelectric type；First storage is single The grid stacking of member can be ferroelectric type, and the grid stacking of the second storage unit can be charge trap-type；Or first storage unit It may each be ferroelectric type with the grid stacking of the second storage unit.
In this example, for the source/drain region of each storage unit of top layer, electrical contacts are respectively formed.Due to storage The density of unit is larger, so the density of this source and drain contacts is larger.According to another embodiment, it can be formed and lowest level Storage unit source/drain region electrical connection the electrode by row (or column) arrangement, and formed with the source of the storage unit of top layer/ The electrode by column (or row) arrangement of drain region electrical connection.In this way, (being crossed each other to form by the electrode of upside and the electrode of downside Array corresponding with memory cell array), it can choose corresponding memory cell string.
Figure 21 (a)~23 show part stage in the process according to the manufacture memory device of another embodiment of the disclosure Schematic diagram.Hereinafter, the difference that will mainly describe the embodiment and above-described embodiment.
After above in conjunction with the processing hole emptied in memory cell areas of Figure 12 (a), 12 (b) and 12 (c), such as Figure 21 It (a), can be via processing hole, the first gate dielectric layer 1019 of difference selectivity eatch-back, floating gate layer or charge-trapping and shown in 21 (b) The 1021, second gate dielectric layer 1023 of layer, so that they are relatively transverse recessed.It then, as shown in figure 22, can be in recessed middle filling Grid conductor material 1203.Grid conductor material 1203 can be identical material with grid conductor layer 1025.This filling for example can be with It is then etched back by deposit to realize.
Next, additional storage unit can be formed in processing hole as described above, as shown in figure 23.In the example In, grid conductor layer 1025 can be in contact with each other with grid conductor material 1203, so that the grid conductor of the second storage unit is constituted together, The grid conductor is via the second additional gate dielectric layer 1107, additional electric charge capture layer 1105 and the first additional gate dielectric layer 1103, channel region can be limited in active semiconductor layer 1109, as shown in the dotted line frame in figure.Compared to above-described embodiment, Increase the grid width of the second storage unit.
Figure 24 (a)~30 (b) shows sublevel in the middle part of the process according to the manufacture memory device of another embodiment of the disclosure The schematic diagram of section.
During the storage grid stacking for the first storage unit is formed in conjunction with described in Fig. 8 (a) and 8 (b) above, Instead of forming grid conductor layer 1025, but form sacrificial gate conductor layer 1025 ', such as polysilicon (for example, un-doped polysilicon). Then, can same process as described above carry out.Combine Figure 12 (a), 12 (b) and 12 (c) described clear more than experience It is processed in empty memory cell areas after the operation in hole, as shown in Figure 24 (a) and 24 (b), processing hole is exposed in memory cell areas. At this point, exposing the side wall of sacrificial gate conductor layer 1025 ' in processing hole.Later, photoresist 1101 can be removed.
Then, can be via processing hole as shown in Figure 25 (a) and 25 (b), such as by selective etch, eatch-back is sacrificed Grid conductor layer 1025 ' keeps its relatively transverse recessed.Then, the second gate dielectric layer of selective etch 1023, floating gate layer can be distinguished Or electric charge capture layer 1021, the first gate dielectric layer 1019.Due to the presence of sacrificial gate conductor layer 1025 ' after eatch-back, second gate is situated between Matter layer 1023, floating gate layer or electric charge capture layer 1021, the first gate dielectric layer 1019 can be with relatively transverse recessed roughly the same journeys Degree.
It then, can be via processing hole, in the material of recessed middle filling sacrificial gate conductor layer as shown in Figure 26 (a) and 26 (b) Material, therefore it is integrally shown as 1025 ' (boundaries for being shown schematically in phantom them) with sacrificial gate conductor layer herein.This Then kind filling can be for example etched back by deposit to realize.
Next, additional storage unit can be formed in processing hole as described above, as shown in Figure 27 (a) and 27 (b). Structure shown in Figure 27 (a) and 27 (b) is substantially the same with the structure with shown in Figure 23, in addition to sacrificial gate conductor layer 1025 ' takes Except grid conductor layer 1025.
It is then possible to carry out replacement gate process, sacrificial gate conductor layer is replaced using final grid conductor layer.
In order to remove sacrificial gate conductor layer 1025 ', need to reach the processing channel of each sacrificial gate conductor layer 1025 '.For this purpose, It, can be in the part except active area, it is preferable that in the edge of memory cell areas such as shown in Figure 28 (a) and 28 (b) Such as the boundary between memory cell areas and contact zone, formed through the ditch respectively stacked for the storage grid of the first storage unit Slot.For example, this can be realized by photoetching.Before this, it in order to protect storage unit, is especially formed in processing hole Additional memory units (because the upper end be currently exposed to outer), can be initially formed protective layer 1111, such as combine above Figure 15 (a) and 15 (b) is described.
It then, can be via above-mentioned groove, selective etch sacrificial gate conductor layer as shown in Figure 29 (a) and 29 (b) 1025 ', to remove sacrificial gate conductor layer 1025 '.It, can be via in the space left due to sacrificial gate conductor layer 1025 ' Above-mentioned groove fills final grid conductor layer 1025 ", such as metal gate conductor such as W.For example, this can by deposit such as ALD or CVD fills W into the space left due to sacrificial gate conductor layer 1025 ', and the W of deposit is enough, to fill up the space And groove.Later, planarization process such as CMP can be carried out to the W of deposit, CMP can stop at protective layer 1111.It is depositing Before metal gate conductor layer, can also deposit thin barrier layer such as TiN (not shown).
In this example, grid conductor layer 1025 " catch via the second additional gate dielectric layer 1107, additional charge by grid conductor Layer 1105 and the first additional gate dielectric layer 1103 are obtained, channel region can be limited in active semiconductor layer 1109, such as Figure 29 (a) In dotted line frame shown in.Compared to above-described embodiment, the grid width of the second storage unit is increased.The case where first storage unit with It is identical in above-described embodiment, as shown in Figure 29 (b).
Later, as shown in Figure 30 (a) and 30 (b), the grid conductor layer filled in groove can be removed, to make each layer grid Conductor layer it is separated.This can by grid conductor layer carry out selective etch such as RIE, RIE can in the vertical direction into Row.This RIE removes the grid conductor layer in above-mentioned groove, so that each grid conductor layer is separated.Furthermore it is possible to via " (and barrier layer, if present) is further etched back above-mentioned groove, to grid conductor layer 1025, to ensure each layer grid It can be fully disconnected between conductor layer.Later, (" it can be etched back and release for example, above-mentioned groove and grid conductor layer 1025 in gap The space put) in filling dielectric layer 1027 ' such as oxide.
Later, contact portion can be formed as described above, details are not described herein.
In the embodiment above, the second storage grid, which stack, is shown as on the side wall in processing hole (other than grid conductor) It is extended continuously.But the present disclosure is not limited thereto, for example, the multilayer being separated from each other can be formed it into, each layer and equivalent layer First storage grid stacking is corresponding, especially in the case where it includes ferroelectric material or floating gate layer that the second storage grid, which stack,.
Figure 31 (a)~36 (b) shows sublevel in the middle part of the process according to the manufacture memory device of another embodiment of the disclosure The schematic diagram of section.Hereinafter, the difference that will mainly describe the embodiment and above-described embodiment.
It, can be via after above in conjunction with the source/drain portions of each first storage units of the separation of Figure 10 (a) and 10 (b) A protective layer 1051 is formed on the surface for stacking internal pore with regard to processing hole, as shown in Figure 31 (a) and 31 (b).For example, can form sediment Product a thin layer nitride, with a thickness of about 1-5nm.The protective layer 1051 can be stacked in the subsequent grid to the second storage unit and be carried out The grid of the first storage unit are protected to stack when processing.It later, can be via processing as described in combining Figure 11 (a) and 11 (b) above Hole, filling dielectric material in the gap into stacking, to form interlevel dielectric layer 1027.
In conjunction with as described in Figure 12 (a), 12 (b) and 12 (c), the processing hole in memory cell areas can be emptied above.Here, As shown in Figure 32 (a) and 32 (b), added using 1101 selective etch of mask such as RIE interlevel dielectric layer 1027 to expose It, can further selective etch such as RIE protective layer 1051 after work hole.In this way, protective layer 1051 is (in memory cell areas ) part that extends on the side wall in processing hole can be removed, and rest part retains due to being blocked.In particular, As shown in Figure 32 (b), the grid of the first storage unit stack (1019/1021/1023) and are covered by protective layer 1051.Later, may be used To remove photoresist 1101.
Then, as shown in Figure 33 (a) and 33 (b), the additional memory units of vertical-type can be formed in processing hole.It is formed The operation of additional memory units is substantially the same with Figure 13, the operation of 14 (a) and 14 (b) descriptions is combined above.But show at this In example, forms different grid and stack.For example, gate dielectric layer 1503, the first metal can be sequentially formed around the side wall in processing hole Layer 1505, ferroelectric material layer 1507 and second metal layer 1509.For example, gate dielectric layer 1503 may include high-K gate dielectric, thickness It is about 1-10nm；The first metal layer 1505 may include TiN, with a thickness of about 1-10nm；Ferroelectric material layer 1507 may include Hf1-xZrxO2, with a thickness of about 1-20nm；Second metal layer 1509 may include TiN, with a thickness of about 1-10nm.In addition, processing hole The active semiconductor layer 1109 of middle filling may include polysilicon, and doping concentration is about 1E16-1E19cm-3。
Here, the metal layer 1505,1509 integrally extended may cause the problem on electrical property as shown in Figure 33 (a).For This, they can be separated from each other.
It is similar to combine figure Figure 28 (a) and 28 above in order to handle the grid stacking for additional memory units (b) shown in, can be in the part except active area, it is preferable that the edge such as memory cell areas of memory cell areas with connect The boundary between area is touched, the groove that the side wall of each interlevel dielectric layer 1027 in capable of making to stack exposes is formed, for use as adding Work channel.It is then possible to via the groove, selective etch (for example, isotropic etching) interlevel dielectric layer 1027, to go Except interlevel dielectric layer 1027, as shown in Figure 34 (a) and 34 (b).Here, protective layer 1051 can protect most material Layer.In addition, between each first storage grid stack, exposing the second storage grid stacking as shown in Figure 34 (a).
Then, as shown in figure 35, can via the groove, selective etch gate dielectric layer 1503, the first metal layer 1505, Ferroelectric material layer 1507 and second metal layer 1509.It is stacked relatively in this way, second gate stack can be separated into each layer first grid The multilayer answered.Due to the presence of protective layer 1051, etching can not influence first grid stacking.
Then, can be via the groove as shown in Figure 36 (a) and 36 (b), filling dielectric material in the gap into stacking Material forms interlevel dielectric layer 1027 ', to realize structural support and required electric isolution.In this regard, may refer to the above combination figure 11 (a) and 11 (b) is described.
Subsequent operation can be same as the previously described embodiments, and details are not described herein.
In addition, in accordance with an embodiment of the present disclosure, can also the first column active area and/or the second column active area most Upper end and/or bottom increase selection transistor, and details are not described herein.This selection transistor is also possible to vertical-type device.
It can be applied to various electronic equipments according to the memory device of the embodiment of the present disclosure.For example, memory device can be deposited Various programs, application and data needed for storing up electronic device.Electronic equipment can also include matching with memory device Processor.For example, processor can operate electronic equipment by allowing the program stored in memory device.This electronic equipment Such as smart phone, computer, tablet computer (PC), wearable smart machine, mobile power source etc..
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method. In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous Ground is used in combination.
Embodiment of the disclosure is described above.But the purpose that these embodiments are merely to illustrate that, and It is not intended to limit the scope of the present disclosure.The scope of the present disclosure is limited by appended claims and its equivalent.This public affairs is not departed from The range opened, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in the disclosure Within the scope of.

Claims (43)

1. a kind of memory device, comprising:
The multiple first column active areas and multiple second column active areas formed on a substrate upwardly extended from substrate, In,
First column active area is arranged as the first array, and the second column active area is arranged as second array,
Every one first column active area includes being alternately stacked for source drain and channel layer, and the bottom of the stacking is source drain, The top is source drain, and corresponding channel layer is in substantially the same plane in each first column active area, and corresponding Source drain is in substantially the same plane,
Every one second column active area includes the active semiconductor layer integrally extended；
Post-like conductive contact portion positioned at each second column active area lower part；
The insulating layer formed around the periphery of each post-like conductive contact portion；
The multilayer first being in respectively with each plane where channel layer in substantially the same plane stores grid and stacks, wherein Each layer first stores grid and stacks respectively around the periphery of each channel layer in respective planes；And
Multilayer second around each second column active area periphery stores grid and stacks.
2. memory device according to claim 1, wherein the first array and second array are nested with one another.
3. memory device according to claim 1, wherein each layer second stores first storage grid of the grid stacking with equivalent layer Stacking includes public grid conductor layer, which extends in the plane where respective channels layer.
4. memory device according to claim 1, wherein each channel layer is mixed in the presence of what is be gradually reduced from periphery towards center Miscellaneous distribution.
5. memory device according to claim 1, wherein
It includes the first gate dielectric layer, floating gate layer or electric charge capture layer, the second gate dielectric layer being sequentially stacked that first storage grid, which stack, With grid conductor layer,
Second storage grid stack another first gate dielectric layer, another electric charge capture layer, another second gate for including to be sequentially stacked and are situated between Matter layer, and the grid conductor layer in the first storage grid stacking in identical layer is used as the grid conductor layer of the second storage grid stacking simultaneously,
Wherein, another first gate dielectric layer, another electric charge capture layer, another second gate dielectric layer are around each second column active area Periphery extends,
Wherein, the periphery substantial alignment of the periphery of another second gate dielectric layer and insulating layer.
6. memory device according to claim 1, wherein first storage grid stack and second storage grid stack at least it One includes ferroelectric material.
7. memory device according to claim 6, wherein
It includes the first metal layer, the ferroelectric material being sequentially stacked that first storage grid, which stack and store at least one of grid stacking with second, Layer, second metal layer and gate dielectric layer, wherein the periphery of the gate dielectric layer in the second storage grid stacking and the periphery of insulating layer Substantial alignment.
8. memory device according to claim 7, wherein
It includes the first gate dielectric layer, floating gate layer or electric charge capture layer, the second gate dielectric layer being sequentially stacked that first storage grid, which stack, With grid conductor layer, it includes the first metal layer, ferroelectric material layer, second metal layer and the grid being sequentially stacked that the second storage grid, which stack, Dielectric layer, wherein the periphery of the gate dielectric layer in the second storage grid stacking and the periphery substantial alignment of insulating layer；Or
It includes the first gate dielectric layer, electric charge capture layer, the second gate dielectric layer being sequentially stacked, the first storage that second storage grid, which stack, It includes the first metal layer, ferroelectric material layer, second metal layer, gate dielectric layer and the grid conductor layer being sequentially stacked that grid, which stack, In, the periphery of the second gate dielectric layer in the second storage grid stacking and the periphery substantial alignment of insulating layer,
Wherein, the grid conductor layer that the first storage grid stack in same layer is used as the grid conductor layer of the second storage grid stacking simultaneously.
9. memory device according to claim 7 or 8, wherein ferroelectric material includes hafnium oxide, zirconium oxide, tantalum oxide, oxygen Change hafnium zirconium or hafnium oxide tantalum, the first metal layer and second metal layer include TiN.
10. memory device according to claim 9, wherein hafnium oxide includes HfO2, zirconium oxide includes ZrO2, tantalum oxide packet Include TaO2, hafnium oxide zirconium includes HfxZr1-xO2, hafnium oxide tantalum includes HfxTa1-xO2, wherein x value is the range of (0,1).
11. memory device according to claim 7 or 8, wherein ferroelectric material includes the HfO containing Si2, HfO containing Al2、 BaTiO3、KH2PO4Or SBTi, the first metal layer and second metal layer include TiN.
12. memory device according to claim 1, wherein each channel layer includes single-crystal semiconductor material, each source drain Including single-crystal semiconductor material.
13. memory device according to claim 12, wherein the single-crystal semiconductor material of channel layer and the list of source drain Brilliant semiconductor material is eutectic.
14. memory device according to claim 13, wherein
The single-crystal semiconductor material of channel layer is Si, and the single-crystal semiconductor material of source drain is SiGe；Or
The single-crystal semiconductor material of channel layer is Si, and the single-crystal semiconductor material of source drain is Si:C；Or
The single-crystal semiconductor material of channel layer is SiGe, and the single-crystal semiconductor material of source drain is Si.
15. memory device according to claim 1, wherein the first storage grid stacking is self-aligned to corresponding channel layer.
16. memory device according to claim 1, wherein in each first column active area, the periphery of channel layer is opposite It is inwardly concaved in the periphery of source drain.
17. memory device according to claim 2, wherein two-dimensional array is arranged in rows into the first column active area, And second column active area two-dimensional array is arranged in rows into, wherein each first column active area is located at the second column active area Two-dimensional array grid approximate centre, each second column active area is located at the grid of the two-dimensional array of the first column active area Approximate centre.
18. memory device according to claim 1, wherein post-like conductive contact portion includes tungsten or copper, and/or is mixed Miscellaneous semiconductor Si, SiGe or Ge, doping concentration 1E18-5E21em-3。
19. memory device according to claim 3, wherein the second storage grid stack further include: are located at common gate and lead Two sides and the additional grid conductor to connect with common gate conductor layer above and below body layer.
20. memory device according to claim 19, wherein the additional grid conductor and the common gate conductor layer are one Body.
21. memory device according to claim 1, further includes: be used as the doped region in earth potential face in substrate, wherein each The source drain of bottom and each post-like conductive contact portion are commonly connected to earth potential face in first column active area.
22. memory device according to claim 3, wherein the top surface of electrically conducting contact is located between two layers of grid conductor layer.
23. memory device according to claim 1, wherein the second column active area has ring structure.
24. a kind of method for manufacturing memory device, comprising:
Being alternately stacked for source drain and channel layer be set on substrate, the bottom of the stacking is source drain, the top be source/ Drop ply；
Several processing holes are formed in the stacking；
Via processing hole, the side wall exposed in processing hole from channel layer drives in dopant into channel layer, in channel layer Form lateral dopant distribution；
Via hole is processed, the channel layer in selective etch stacking is separated from each other with formation in each channel layer in a stack The array in multiple cell channel portions；
Via processing hole, is formed in the gap in the stacking and stacked for the storage grid of the first storage unit；
Material in removal processing hole, to expose processing hole；
Via hole is processed, the source drain in selective etch stacking is respectively formed with the upper side and lower side in each unit groove Unit source/drain portion, wherein it is single that the corresponding units source/drain portion of each unit groove and its upper side and lower side constitutes the first storage Member；
Via processing hole, separation layer is formed in the gap in the stacking；
Material in removal processing hole, to expose processing hole；
The electrically conducting contact surrounded by insulating layer is formed in the bottom in processing hole；And
Above electrically conducting contact and insulating layer, the storage grid heap for being used for the second storage unit is formed on the side wall in processing hole It is folded, and be formed with filling in the processing hole stacked for the storage grid of the second storage unit on side wall and be used for the second storage unit Active semiconductor layer.
25. according to the method for claim 24, wherein the alternating of source drain and channel layer is arranged by epitaxial growth It stacks.
26. according to the method for claim 25, wherein carry out doping in situ to source drain when growing source drain, mix Miscellany type corresponds to device conducts type.
27. according to the method for claim 25, wherein carry out doping in situ, doping to channel layer when growing channel layer Type is opposite with device conducts type.
28. according to the method for claim 24, wherein
Being formed for the storage grid stacking of the first storage unit includes: to sequentially form the first gate dielectric layer, floating gate layer or charge prisoner Layer, the second gate dielectric layer and grid conductor layer are obtained,
Being formed for the storage grid stacking of the second storage unit includes: to sequentially form another first gate dielectric layer, another charge prisoner Obtain layer and another second gate dielectric layer.
29. according to the method for claim 24, further includes: formed in the substrate for most under the first storage unit with And the well region of electrically conducting contact electrical contact.
30. according to the method for claim 24, wherein substrate includes memory cell areas and contact zone,
On memory cell areas, process hole density be provided so that via processing hole to channel layer selective etch to After fixing time, the part that channel layer is located at memory cell areas is separated into the island portion of isolation, these island portion Component units Groove,
On contact zone, the density for processing hole is provided so as to be located at the part of contact zone in the given time septal fossula channel layer Substantially completely removed.
31. according to the method for claim 30, wherein two dimension is arranged in rows into the cell channel portion in each channel layer Array, and on memory cell areas, processing hole is arranged to two-dimensional array corresponding with the two-dimensional array, each unit groove The approximate center of grid in the two-dimensional array in processing hole.
32. according to the method for claim 24, wherein in selective etch channel layer and formed for the first storage list Before the storage grid of member stack, this method further include:
Selective etch source drain, to increase the gap between source drain.
33. according to the method for claim 24, further includes: the selective etch to source drain is controlled, so that unit source/ The periphery in leakage portion is protruded outward relative to the periphery in corresponding cell channel portion.
34. according to the method for claim 24, wherein stack and expose for the storage grid of the first storage unit being formed It processes after hole, and before selective etch source drain, this method further include:
Via processing hole, the side wall exposed in processing hole from source drain drives in dopant into source drain, in source drain It is middle to form lateral dopant distribution.
35. according to the method for claim 34, wherein driving in dopant includes:
Dopant active layer is formed on the side wall in processing hole；And
By annealing, drive in the dopant in dopant active layer in channel layer or source drain.
36. according to the method for claim 28, wherein after forming separation layer and exposing processing hole, and forming the Before the storage grid of two storage units stack, this method further include:
Selective etch is carried out to the first gate dielectric layer, floating gate layer or electric charge capture layer, the second gate dielectric layer via processing hole, is made It is relatively recessed；And
Additional grid conductor layer is formed in the female.
37. according to the method for claim 28, wherein the grid conductor layer for the first storage unit of formation is sacrificial gate Conductor layer,
It wherein, should after forming separation layer and exposing processing hole, and before the storage grid for forming the second storage unit stack Method further include: be etched back sacrificial gate conductor layer, and the first gate dielectric layer of selective etch, floating gate layer or charge prisoner via processing hole Layer, the second gate dielectric layer are obtained, keeps these layers relatively recessed；Additional sacrificial gate conductor layer is formed in the female,
Wherein, after forming the active semiconductor layer for the second storage unit, this method further include: in source drain and ditch In the lamination of channel layer and the region except active semiconductor layer, formed through respectively for the storage grid stacking of the first storage unit Groove；Via the groove, sacrificial gate conductor layer is removed；Via the groove, most wire grid conductor layer is formed；It removes in the groove Grid conductor layer portion, and dielectric layer is formed wherein.
38. according to the method for claim 24, wherein formed and by the electrically conducting contact that insulating layer surrounds include:
Insulating layer is formed on the side wall in processing hole；
It is formed on side wall in the processing hole of insulating layer and fills conductive material；
It is etched back conductive material；And
Selective etch insulating layer.
39. according to the method for claim 24, wherein form depositing for the second storage unit on the side wall in processing hole It includes: that the storage grid stacking for being used for the second storage unit is formed as corresponding with each layer first storage grid stacking that storage grid, which stack, The storage grid that multilayer is separated from each other stack.
40. according to the method for claim 39, wherein
After the source drain in selective etch stacking and before forming separation layer, this method further include: via processing Hole forms protective layer,
It is formed on the side wall in processing hole and includes: for the storage grid stacking of the second storage unit
Via processing hole selective etch separation layer and the protective layer part extended on processing hole side；
The gate dielectric layer, the first metal layer, ferroelectric material layer for the second storage unit are sequentially formed on the side wall in processing hole And second metal layer；
It is formed such that the groove that the side wall of separation layer exposes；
Via the groove, remove separation layer, and selective etch for the gate dielectric layer of the second storage unit, the first metal layer, Ferroelectric material layer and second metal layer；
Via the groove, separation layer is formed in the gap into the stacking.
41. a kind of electronic equipment, including as the memory device as described in any one of claim 1~23.
42. electronic equipment according to claim 41 further includes the processor matched with the memory device.
43. electronic equipment according to claim 41, the electronic equipment include smart phone, computer, tablet computer, can Dress smart machine, mobile power source.
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