CN111613584B - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
CN111613584B
CN111613584B CN202010494871.9A CN202010494871A CN111613584B CN 111613584 B CN111613584 B CN 111613584B CN 202010494871 A CN202010494871 A CN 202010494871A CN 111613584 B CN111613584 B CN 111613584B
Authority
CN
China
Prior art keywords
layer
doped material
material layer
channel
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010494871.9A
Other languages
Chinese (zh)
Other versions
CN111613584A (en
Inventor
王桂磊
亨利·H·阿达姆松
孔真真
李俊杰
刘金彪
李俊峰
殷华湘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN202010494871.9A priority Critical patent/CN111613584B/en
Publication of CN111613584A publication Critical patent/CN111613584A/en
Application granted granted Critical
Publication of CN111613584B publication Critical patent/CN111613584B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer

Abstract

The embodiment of the application provides a semiconductor device and a manufacturing method thereof, wherein a stacked layer of a first doped material layer, a channel layer and a second doped material layer is formed on a substrate, the stacked layer is etched to obtain a vertical through hole and an isolation groove, an insulating layer is formed in the vertical through hole, then the channel layer can be etched from the lateral direction through the isolation groove, the channel layer on the side wall of the insulating layer is reserved, so that a gap between the first doped material layer and the second doped material layer is formed, and a gate dielectric layer and a gate electrode are formed in the gap. In this way, the source electrode and the drain electrode are horizontal film layers parallel to the surface of the substrate, the channel layer reserved on the side wall of the insulating layer is used as a channel in the vertical direction between the source electrode and the drain electrode, the length of the channel is related to the thickness of the film layer, and high-cost and high-precision etching is not needed, so that a small-size high-performance device can be obtained by using lower cost and simple process.

Description

Semiconductor device and manufacturing method thereof
Technical Field
The present disclosure relates to semiconductor devices and methods of fabricating the same, and more particularly, to a semiconductor device and a method of fabricating the same.
Background
Along with the update and iteration of the semiconductor manufacturing process technology, the size of the semiconductor device is continuously reduced, the integration level is continuously improved, however, along with the miniaturization of the process node, the process node can reach a limit point, the size of the process node cannot be continuously reduced, and the performance is more and more difficult to improve. How to obtain small-sized high-performance devices is an important problem facing the field.
Disclosure of Invention
In view of the above, an object of the present application is to provide a semiconductor device and a method for manufacturing the same, which can achieve higher performance with a smaller device size.
In order to achieve the above purpose, the present application has the following technical scheme:
the embodiment of the application provides a manufacturing method of a semiconductor device, which comprises the following steps:
forming a stacked layer of a first doped material layer, a channel layer, and a second doped material layer on a substrate;
etching the stacked layer to obtain a vertical through hole and an isolation groove, and forming an insulating layer in the vertical through hole;
etching the channel layer laterally through the isolation trench, and reserving the channel layer on the side wall of the insulating layer to form a gap between the first doped material layer and the second doped material layer;
and forming a gate dielectric layer and a gate layer in the gap through the isolation trench.
Optionally, the etching the channel layer from the lateral direction through the isolation trench includes:
performing a multiple oxidation removal process; the oxidation removal process comprises the following steps: performing an oxidation process of the channel layer to form an oxide layer on the exposed channel layer surface in the isolation trench; and removing the oxide layer.
Optionally, the performing an oxidation process of the channel layer includes:
the channel layer is self-limiting oxidized using plasma or chemistry.
Optionally, the etching the stacked layer to obtain a vertical through hole and an isolation trench, forming an insulating layer in the vertical through hole, including:
etching the stacked layer to obtain an isolation groove, and forming an isolation layer in the isolation groove;
etching the stacked layer to obtain a vertical through hole, and forming an insulating layer in the vertical through hole;
and removing the isolation layer in the isolation trench.
Optionally, the first doped material layer, the channel layer and the second doped material layer are silicon germanium, silicon germanium, or silicon, silicon germanium, silicon, or germanium, germanium tin, germanium, respectively.
Optionally, a buffer layer is formed between the substrate and the first doped material layer.
Optionally, an intrinsic layer of the first doped material layer is formed between the first doped material layer and the channel layer, and an intrinsic layer of the second doped material layer is formed between the barrier layer and the second doped material layer.
Optionally, forming a gate dielectric layer and a gate layer in the gap through the isolation trench includes:
and depositing a gate dielectric layer and a gate electrode layer, and removing the gate electrode layer and the gate dielectric layer outside the gap through the isolation groove.
Optionally, the insulating layer includes a strained material layer for providing compressive or tensile stress to the channel layer.
The embodiment of the application also provides a semiconductor device, which comprises:
a substrate;
a stacked layer of a first doped material layer, a channel layer, and a second doped material layer on the substrate;
a vertical via and an isolation trench in the stacked layer, the vertical via having an insulating layer formed therein;
the channel layer is recessed in the isolation trench from the first doped material layer and the second doped material layer, so that a gap is formed between the first doped material layer and the second doped material layer;
and a gate dielectric layer and a gate layer are formed in the gap.
Optionally, the first doped material layer, the channel layer and the second doped material layer are silicon germanium, silicon germanium, or silicon, silicon germanium, silicon, or germanium, germanium tin, germanium, respectively.
Optionally, a buffer layer is formed between the substrate and the first doped material layer.
Optionally, an intrinsic layer of the first doped material layer is formed between the first doped material layer and the channel layer, and between the first doped material layer and the gate dielectric layer, and an intrinsic layer of the second doped material layer is formed between the channel layer and the second doped material layer, and between the gate dielectric layer and the second doped material layer.
Optionally, the insulating layer includes a strained material layer for providing compressive or tensile stress to the channel layer.
The embodiment of the application provides a semiconductor device and a manufacturing method thereof, wherein a stacked layer of a first doped material layer, a channel layer and a second doped material layer is formed on a substrate, the stacked layer is etched to obtain a vertical through hole and an isolation groove, an insulating layer is formed in the vertical through hole, then the channel layer can be etched from the lateral direction through the isolation groove, the channel layer on the side wall of the insulating layer is reserved, so that a gap between the first doped material layer and the second doped material layer is formed, and a gate dielectric layer and a gate electrode are formed in the gap. In this way, the source electrode and the drain electrode are horizontal film layers parallel to the surface of the substrate, the channel layer reserved on the side wall of the insulating layer is used as a channel in the vertical direction between the source electrode and the drain electrode, the length of the channel is related to the thickness of the film layer, and high-cost and high-precision etching is not needed, so that a small-size high-performance device can be obtained by using lower cost and simple process.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;
fig. 2-17 illustrate schematic structural diagrams during formation of a semiconductor device according to a fabrication method according to an embodiment of the present application.
Detailed Description
In order to make the above objects, features and advantages of the present application more comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the schematic drawings, wherein the cross-sectional views of the device structure are not to scale for the sake of illustration, and the schematic drawings are merely examples, which should not limit the scope of protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
As described in the background art, with the update and iteration of the semiconductor manufacturing process technology, the size of the semiconductor device is continuously reduced, and the integration level is continuously improved, however, with the miniaturization of the process node, the size of the semiconductor device is limited by the process and cannot be continuously reduced, so that the performance improvement of the device is more and more difficult. How to obtain small-sized high-performance devices is an important problem facing the field.
For example, a memory layer and a gate layer may be formed on a substrate, and a source and a drain are doped in the substrate at two sides of the gate layer, so that a channel layer between the source and the drain is limited by the size of the gate layer, and the size of the gate layer is limited by a photolithography process, thereby limiting the overall size of the device.
Based on the above technical problems, the embodiments of the present application provide a semiconductor device and a manufacturing method thereof, in which a stacked layer of a first doped material layer, a channel layer and a second doped material layer is formed on a substrate, a vertical via and an isolation trench are obtained by etching the stacked layer, an insulating layer is formed in the vertical via, then the channel layer can be etched from the lateral direction through the isolation trench, the channel layer on the sidewall of the insulating layer is reserved, so as to form a gap between the first doped material layer and the second doped material layer, and a gate dielectric layer and a gate are formed in the gap. In this way, the source electrode and the drain electrode are horizontal film layers parallel to the surface of the substrate, the channel layer reserved on the side wall of the insulating layer is used as a channel in the vertical direction between the source electrode and the drain electrode, the length of the channel is related to the thickness of the film layer, and high-cost and high-precision etching is not needed, so that a small-size high-performance device can be obtained by using lower cost and simple process.
For a better understanding of the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application is shown, where the method may include the following steps:
s101, a stacked layer of a first doped material layer 101, a channel layer 102, and a second doped material layer 103 is formed on a substrate 100, as shown with reference to fig. 2 and 3.
In the embodiment of the present application, the substrate 100 may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (silicon on insulator ) or GOI (germanium on insulator, germanium On Insulator), a group iii-v compound, a group ii-iv compound semiconductor, or the like. In other embodiments, the substrate 100 may also be a substrate including other elemental or compound semiconductors, such as GaAs, inP, siC, or the like, a stacked structure, such as Si/SiGe, or the like, and other epitaxial structures, such as SGOI (silicon germanium on insulator), or the like. In this embodiment, the substrate 100 is a bulk silicon substrate.
In this embodiment, a stacked layer may be formed on the substrate 100, and the stacked layer may include a first doped material layer 101, a channel layer 102 and a second doped material layer 103, as shown in fig. 2 and fig. 3, where fig. 2 is a schematic diagram of a semiconductor device in a manufacturing process according to the embodiment of the present application, and fig. 3 is a schematic structural diagram of a semiconductor device in a horizontal plane in which a dotted line in the semiconductor device shown in fig. 2 is located. Wherein the first doped material layer 101 and the second doped material layer 103 may be used as a source and a drain, i.e. one is a source and the other is a drain. The materials of the first doping material layer 101, the channel layer 102, and the second doping material layer 103 may be determined according to actual situations.
Specifically, when the substrate 100 is a silicon substrate, the materials of the first doped material layer 101, the channel layer 102 and the second doped material layer 103 may be silicon germanium, silicon, or silicon germanium, that is, silicon germanium is used as a source drain, and silicon is used as a channel, so that the first doped material layer 101 and the silicon substrate have similar lattice constants, which is beneficial to forming the first doped material layer 101 with better quality.
Specifically, when the substrate 100 is a silicon substrate, the materials of the first doped material layer 101, the channel layer 102 and the second doped material layer 103 may be silicon, silicon germanium, i.e. silicon is used as a source drain, and silicon germanium is used as a channel, and at this time, the first doped material layer 101 and the silicon substrate have the same material, which is beneficial to forming the first doped material layer 101 with better quality. Wherein the electron mobility of silicon is about 1600cm 2 V -1 s -1 Hole mobility is about 430cm 2 V -1 s -1 The electron mobility of germanium is about 3900cm 2 V -1 s -1 Hole mobility was about 1900cm 2 V -1 s -1 I.e., silicon germanium has better carrier mobility than silicon, and thus the resulting device may have better performance.
Specifically, when the substrate 100 is a silicon substrate, the materials of the first doped material layer 101, the channel layer 102 and the second doped material layer 103 may be germanium, germanium tin, or germanium, that is, germanium is used as a source drain, and germanium tin is used as a channel, where the first doped material layer 101 and the silicon substrate have a certain lattice difference, so a buffer layer may be formed between the first doped material layer 101 and the silicon substrate, and the buffer layer may be a germanium layer formed at a low temperature, or may be a stack of a germanium layer formed at a low temperature and a germanium layer formed at a high temperature, which is used to balance lattice constants between the first doped material layer 101 and the silicon substrate, so as to form the first doped material layer 101 with better quality. Since germanium has higher carrier mobility than silicon and tin also has higher carrier mobility, the resulting device has better performance.
Of course, the first doped material layer 101, the channel layer 102 and the second doped material layer 103 in the embodiment of the present application may also be other materials, for example, gaAs, inAs, inAb or a group iii-v material, which have higher carrier mobility, so as to be beneficial to improving the device performance, and a person skilled in the art may select a suitable material for the first doped material layer 101, the channel layer 102 and the second doped material layer 103 according to practical situations.
The thickness of the first doped material layer 101, the channel layer 102 and the second doped material layer 103 may range from 10 nm to 30nm, where the first doped material layer 101 and the second doped material layer 103 are doped materials, and the doping types of the first doped material layer 101 and the second doped material layer 103 may be the same, and the doping manner may be in-situ doping or other doping manners. A diffusion barrier layer may be formed between the first doped material layer 101 and the channel layer 102, and may be an intrinsic layer of the first doped material, so as to block the doped elements in the first doped material layer 101 from diffusing into the channel layer 102, and similarly, a diffusion barrier layer may be formed between the channel layer 102 and the second doped material layer 103, and may be an intrinsic layer of the second doped material layer 103, so as to block the doped elements in the second doped material layer 103 from diffusing into the channel layer 102.
As one example, the stacked layer may include a doped silicon layer, an intrinsic silicon layer, a silicon germanium layer, an intrinsic silicon layer, a doped silicon layer, wherein the intrinsic silicon layer acts as a diffusion barrier; or the stacked layers may include a doped silicon germanium layer, an intrinsic silicon germanium layer, a silicon layer, an intrinsic silicon germanium layer, a doped silicon germanium layer, wherein the intrinsic silicon germanium layer acts as a diffusion barrier; or the stacked layers may include doped germanium layers, intrinsic germanium layers, germanium tin layers, intrinsic germanium layers, doped germanium layers.
The first doped material layer 101, the channel layer 102, and the second doped material layer 103 may be formed by epitaxial growth, for example, by chemical vapor deposition (Chemical Vapor Deposition, CVD), molecular beam epitaxy (Molecular Beam Epitaxy, MBE), atomic layer deposition (Atomic Layer Deposition, ALD), or the like.
In particular, in the process of epitaxially growing silicon, the temperature can be 500-700 ℃ and the cavity pressure can be increasedThe silicon epitaxial layer is formed by using a precursor containing silicon under the condition of 10-20Torr, and the time for epitaxially growing silicon can be in the range of 20s-240 s. Wherein the silicon-containing precursor may be Si 2 H 2 Cl 2 The flow rate can be 20-500sccm; the silicon-containing precursor may also be SiH 4 The flow rate can be 20-300sccm; the silicon-containing precursor may also be Si 2 H 6 And H 2 The flow rate of the mixed gas of (2) can be 20-300sccm. When epitaxially grown silicon is used as source and drain, the doped silicon can be grown in situ by doping, specifically, doping gas can be used to provide doping element and is input into the cavity together with the precursor containing silicon, the doping gas can be PH 3 And H 2 Or AsH 3 And H 2 Is a mixed gas of (a) and (b).
Specifically, in the process of epitaxially growing silicon germanium, the epitaxial layer can be generated by using a precursor containing silicon and a precursor containing germanium under the conditions that the temperature is 500-700 ℃ and the cavity pressure is 10-20Torr, and the time for epitaxially growing the silicon germanium can be in the range of 20s-240 s. Wherein the silicon-containing precursor may be Si 2 H 2 Cl 2 The flow rate can be 20-500sccm; the silicon-containing precursor may also be SiH 4 The flow rate can be 20-300sccm; the silicon-containing precursor may also be Si 2 H 6 And H 2 The flow rate of the mixed gas of (2) can be 20-300sccm; the germanium-containing precursor may be GeH 4 And H 2 Or Ge) 2 H 6 And H 2 The flow rate of the mixed gas of (2) can be 20-300sccm. When epitaxially grown silicon germanium is used as the source and drain, the doped silicon can be grown in situ by doping, specifically, doping gas can be used to provide doping element, and the doping gas can be PH 3 And H 2 Or AsH 3 And H 2 Is a mixed gas of (a) and (b).
Specifically, in the process of epitaxially growing germanium, an epitaxial layer can be generated by using a precursor containing germanium under the conditions that the temperature is 350-700 ℃ and the cavity pressure is 10-20Torr, and the epitaxial layer is epitaxially grownThe germanium time may be in the range of 20s-240 s. Wherein the germanium-containing precursor may be GeH 4 And H 2 Or Ge) 2 H 6 And H 2 The flow rate of the mixed gas of (2) can be 20-1000sccm. When epitaxially grown germanium is used as the source and drain, the doped silicon can be grown in situ by doping, specifically, doping gas can be used to provide doping element and is input into the cavity together with germanium-containing precursor, the doping gas can be PH 3 And H 2 Or AsH 3 And H 2 Is a mixed gas of (a) and (b).
Specifically, in the process of epitaxially growing germanium tin, the epitaxial layer can be generated by utilizing a tin-containing precursor and a germanium-containing precursor under the conditions that the temperature is 250-400 ℃ and the cavity pressure is 10-20Torr, and the time for epitaxially growing germanium tin can be in the range of 20s-240 s. Wherein the tin-containing precursor may be SnCl 4 (H 2 Carried) with a flow rate of 20-500sccm; the germanium-containing precursor may be GeH 4 And H 2 Or Ge) 2 H 6 And H 2 The flow rate of the mixed gas of (2) can be 20-1000sccm. When epitaxially grown germanium-tin is used as source and drain, doped silicon can be grown in situ, specifically, doping gas can be used to provide doping element, and the doping element, tin-containing precursor and germanium-containing precursor can be input into the cavity together, and the doping gas can be PH 3 And H 2 Or AsH 3 And H 2 Is a mixed gas of (a) and (b).
In the specific implementation, the composition of germanium in the silicon germanium layer can be determined according to practical situations, and the composition of germanium in the silicon germanium layer can be less than or equal to 30% by integrating the carrier mobility in the silicon germanium layer and the lattice constant between the silicon germanium layer and silicon; the composition of tin in the germanium tin can be determined according to practical conditions, and the composition of tin in the tin germanium layer can be 0.5% -20% by integrating the carrier mobility in the tin germanium layer and the lattice constant between the tin germanium layer and the germanium layer; the ion doping concentration in the source and drain is 1E19-3E20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thicknesses of the first doped material layer 101, the second doped material layer 103 and the channel layer 102 in the device may be according to practical situationsIt is determined that, as an example, the thicknesses thereof may be 10-30nm each; a diffusion barrier layer may be formed between the source and the channel, and between the channel layer 102 and the drain, and may have a thickness of 1-5nm, and the diffusion barrier layer is typically an intrinsic layer formed by stopping the input of the doping gas after the formation of the first doping material layer 101, or an intrinsic layer formed by not having the input of the doping gas before the formation of the second doping material layer 103.
It should be noted that, a plurality of stacked layers stacked in a vertical direction may be included on the substrate, and each stacked layer may include a first doped material layer, a channel layer and a second doped material layer, so that the integration level of the device may be improved, and the plurality of stacked layers may be separated by using an insulating material.
S102, etching the stacked layer to obtain a vertical via 104 and an isolation trench 110, and forming an insulating layer 105 in the vertical via 104, as shown in fig. 4-11.
After forming the stacked layers of the first doped material layer 101, the channel layer 102 and the second doped material layer 103, the stacked layers may be etched to obtain a vertical via 104 and an isolation trench 110, the vertical via 104 is used to form an insulating layer 105, the stacked layers are fixed in a subsequent process, the isolation trench 110 may isolate the stacked layers where different devices are located, as shown in fig. 6 and fig. 7, which include four independent stacked layers isolated by the isolation trench 110, and each independent stacked layer isolated by the isolation trench 110 may be formed with a vertical via 104, where fig. 6 is a schematic diagram of a semiconductor device provided in an embodiment of the present application in a manufacturing process, and fig. 7 is a schematic structural diagram of the semiconductor device in a horizontal plane where a dotted line is located in the semiconductor device shown in fig. 6. Of course, a plurality of vertical vias 104 (not shown) may also be formed in each individual stacked layer to increase the structural robustness of the device.
Specifically, the shape of the vertical via 104 may be determined according to practical situations, for example, the vertical via 104 may be rectangular, or may be circular, or may be other shapes, and when the upper surface of the stacked layer isolated by the isolation trench 110 is rectangular, the vertical via 104 may also be rectangular, so that the channel layer remaining subsequently is relatively uniform. The vertical via 104 may be formed in a central location of the separate stacked layers to make the channel layer remaining later more uniform or may not be in a central location of the stacked layers. A plurality of vertical vias 104 may be gathered in a central location of the stacked layers.
As a possible implementation manner, the stacked layer may be etched to obtain the vertical via 104, and the insulating layer 105 is formed in the vertical via 104, and then the stacked layer is etched to obtain the isolation trench 110, where the isolation trench 110 and the vertical via 104 have no overlapping area, and the isolation trench 110 may be formed between adjacent vertical vias 104.
As another possible implementation manner, the stacked layer may be etched to obtain the isolation trench 110, the stacked layer where each device is located is isolated, the isolation trench 110 is filled with the isolation layer 111, and the isolation layer 111 may be an insulating layer, for example, silicon oxide, silicon nitride, or the like, as shown in fig. 4 and fig. 5, where fig. 4 is a schematic view of a semiconductor device in a manufacturing process provided in the embodiment of the present application, and fig. 5 is a schematic view of a structure in a horizontal plane where a dotted line in the semiconductor device shown in fig. 4 is located; then, the patterned mask layer 120 may be used as a mask, and the vertical through holes 104 are etched in each independent stacked layer, as shown in fig. 6 and 7, the mask layer 120 may be a photoresist layer, or may be a hard mask layer, where the hard mask layer may be silicon oxide, silicon nitride, or the like, and then, the mask layer 120 may be removed, where the mask layer 120 is a hard mask layer, or where the removal of the mask layer 120 is not performed, so that the stacked layer is protected by the mask layer 120; filling the vertical through hole 104 with an insulating layer 105, referring to fig. 5, the filled insulating layer 105 may be flush with the stacked layer, and when the stacked layer has a mask layer 120 left thereon, the insulating layer 105 may be flush with the hard mask layer, referring to fig. 8 and 9, wherein fig. 8 is a schematic diagram of a semiconductor device provided in an embodiment of the present application in a manufacturing process, and fig. 9 is a schematic diagram of a structure of the semiconductor device shown in fig. 8 in a horizontal plane in which a dotted line is located; thereafter, the isolation layer 111 in the isolation trench 110 may be removed, as shown in fig. 10 and 11, where fig. 10 is a schematic view of a semiconductor device provided in an embodiment of the present application during a manufacturing process, and fig. 11 is a schematic view of a structure of the semiconductor device shown in fig. 10 in a horizontal plane in which a dotted line is located.
Among them, the insulating layer 105 serves to increase structural stability of the device, and its material may include silicon oxide, silicon nitride, and the like. In one implementation, the insulating layer 105 may further include a strained material layer to provide compressive or tensile stress to the channel layer 102 in contact with the strained material layer to increase carrier mobility of the channel layer 102. The insulating layer 105 may include only a strained material layer, i.e. the strained material layer fills the vertical via 104, and the insulating layer 105 may also include a strained material layer and other insulating layers, where the strained material layer is located outside the other insulating layers and is in contact with the channel layer 102, e.g. the strained material layer may be located outside the silicon oxide, and in a specific implementation, the strained material layer may be formed on the sidewall of the vertical via 104, after which the vertical via 104 is filled with silicon oxide.
In particular, the hole mobility of the channel layer 102 may be improved when the strained material layer provides compressive stress to the channel layer 102, and thus, a strained material layer capable of providing compressive stress to the channel layer 102 may be selected in a PMOS device, and in particular, a strained material layer having a lattice constant greater than that of the channel layer material may be selected, for example, when the channel layer 102 is silicon germanium, the strained material layer may be monocrystalline silicon.
In particular, when the strained material layer provides tensile stress to the channel layer 102, the electron mobility of the channel layer 102 may be improved, and thus, a strained material layer capable of providing tensile stress to the channel layer 102 may be selected in an NMOS device, and in particular, a strained material layer having a lattice constant smaller than that of the channel layer material may be selected, for example, when the channel layer 102 is silicon, the strained material layer may be silicon germanium, and when the channel layer 102 is germanium tin, the strained material layer may be monocrystalline germanium.
Etching of the stacked layers may be achieved by a photolithography technique, specifically, a photoresist may be formed on the stacked layers, the patterned photoresist may be obtained by photolithography and development, etching of the stacked layers may be performed using the photoresist as a mask to obtain the vertical via holes 104 or the isolation trenches 110, and then the photoresist layer may be removed.
The etched vertical via 104 may extend through to the substrate 100, or may over-etch a portion of the substrate 100, and the etched isolation trench 110 may extend through only the stacked layers, or may extend through to the substrate 100, or may over-etch a portion of the substrate 100. When a buffer layer is formed between the first doped material layer 101 and the substrate 100, the vertical via 104 may extend only through the stacked layers, i.e., stop on top of the buffer layer, although some or all of the buffer layer may be etched.
S103, the channel layer 102 is etched from the side direction through the isolation trench 110, leaving the channel layer 102 on the sidewall of the insulating layer 105 to form a gap 1021 between the first doped material layer 101 and the second doped material layer 103, as shown with reference to fig. 12 and 13.
Since the isolation trench 110 penetrates through the stacked layers, the sidewalls of the first doped material layer 101, the channel layer 102 and the second doped material layer 103 in the stacked layers are exposed, at this time, the channel layer 102 may be etched from the side direction through the isolation trench 110 to remove a portion of the channel layer 102, so as to form a gap 1021 between the first doped material layer 101 and the second doped material layer, the channel layer 102 is remained on the sidewall of the insulating layer 105, the remained channel layer 102 is connected to the first doped material layer 101 and the second doped material layer 103, the channel length is consistent with the thickness of the channel layer 102, and referring to fig. 12 and 13, fig. 12 is a schematic diagram of a semiconductor device in a manufacturing process provided in an embodiment of the present application, and fig. 13 is a schematic structural diagram of the semiconductor device in a horizontal plane where a dotted line is located in the semiconductor device shown in fig. 12.
The channel layer 102 is etched laterally through the isolation trench 110, and may be etched by a wet etching process, for example, a portion of the channel layer 102 may be etched by an acid method, or may be etched by a gas molecular reaction, or may be etched by a multiple oxidation removal process. Specifically, the oxidation removal process may be performed by first performing an oxidation process of the channel layer 102 to form an oxide layer on the surface of the channel layer 102 exposed in the isolation trench 110, and then removing the oxide layer on the surface of the channel layer 102.
Wherein the channel layer 102 is performedThe oxidation process may specifically be a plasma or chemical self-limiting oxidation of the channel layer 102, during which the channel layer 102 may be oxidized more than the first and second doped material layers 101 and 103. Wherein the oxidant may be oxygen O 2 Ozone O may be used 3 . After the oxide layer is formed on the channel layer 102, the formed oxide may be precisely etched using an etching gas. Specifically, dry etching may be used to remove the oxide layer.
In the oxidation removal process, the channel layer 102 is oxidized within a certain thickness, the generated oxide of the channel layer 102 can be etched, the oxide can be oxidized and removed for multiple times, rapid and precise etching can be realized, and generally, the etching precision can be accurate to the quasi-atomic level. More preferably, the thickness of the oxidized layer after each oxidation can be controlled to be 1-10A by controlling the technological parameters in the oxidation process, and the etching precision can be accurate to the quasi-atomic level by repeating the steps of oxidation and etching through etching with high selectivity.
For example, when the first doped material layer 101, the channel layer 102 and the second doped material layer 103 are silicon, silicon germanium and silicon respectively, oxidation of silicon germanium may be performed first, then oxide of silicon germanium may be etched and removed, and lateral removal of silicon germanium layer may be achieved through multiple oxidation and etching processes; when the first doped material layer 101, the channel layer 102 and the second doped material layer 103 are silicon germanium, silicon and silicon germanium respectively, oxidation of silicon can be performed first, then silicon oxide obtained by oxidation can be etched and removed, and lateral removal of the silicon layer can be realized through multiple oxidation and etching processes.
When the channel layer 102 is laterally etched by using the oxidation removal process, the strain of the channel layer 102 may be changed to a certain extent, so as to further improve the carrier mobility of the channel layer 102. For example, along with the etching of the silicon layer, the tensile stress of the silicon layer also becomes larger, and the electron mobility of the NMOS tube is further improved; along with the etching of the silicon germanium layer, the silicon germanium layer is subjected to compressive stress, so that the hole mobility of the PMOS tube is further improved.
S104, a gate dielectric layer 106 and a gate layer 107 are formed in the gap 1021, see fig. 14 to 17.
After the lateral etching of the channel layer 102, a gap 1021 may be formed between the first doped material layer 101 and the second doped material layer 103, where a side of the gap 1021 near the insulating layer 105 is a surface of the channel layer 102, and then a gate dielectric layer 106 and a gate layer 107 may be formed in the gap 1021, as shown in fig. 14 and 15, where fig. 14 is a schematic view of a semiconductor device in a manufacturing process according to an embodiment of the present application, and fig. 15 is a schematic view of a structure of the semiconductor device in a horizontal plane where a dotted line is shown in fig. 14.
Specifically, the gate dielectric layer 106 may be a high-K material, such as HfO 2 、HfSiO、HfSiON、HfTaO、HfTiO，La 2 O 3 The gate dielectric layer 106 may be formed by ALD, CVD, or the like, for example, such that the gate dielectric layer 106 is formed to cover the sidewall of the gap 1021, the surface of the channel layer 102 in the gap 1021, the sidewall of the stack layer outside the gap 1021, the upper surface of the stack layer, and the bottom of the isolation trench 110.
The gate layer 107 may be made of metal material, other conductor material, or a combination of metal material and other conductor material, such as Ti, tiAl x 、TiN、TaN x 、HfN、TiC x 、TaC x W, co, etc. or a laminate thereof. The gate layer 107 may be formed by ALD, CVD, or the like, so that the gate layer 107 covering the gate dielectric layer 106 may be formed.
Thereafter, the gate layer 107 and the gate dielectric layer 106 may be removed at other locations than the gap 1021 to obtain the gate dielectric layer 106 and the gate layer 107 in the gap 1021. Specifically, the gate dielectric layer 106 and the gate layer 107 on the upper surface of the stacked layer and the bottom of the isolation trench 110 may be removed by anisotropic etching, and then the gate dielectric layer 106 and the gate layer 107 on the sidewalls of the stacked layer may be removed by isotropic etching.
Thereafter, the stacked layers and the isolation trenches 110 may be covered by using the interlayer dielectric layer 130, as shown in fig. 16 and 17, where fig. 16 is a schematic view of a semiconductor device in a manufacturing process according to an embodiment of the present application, and fig. 17 is a schematic view of a structure of the semiconductor device shown in fig. 16 in a horizontal plane in which a dashed line is located. The extraction of the connection lines (not shown) may then take place.
The embodiment of the application provides a manufacturing method of a semiconductor device, wherein a stacked layer of a first doped material layer, a channel layer and a second doped material layer is formed on a substrate, one of the first doped material layer and the second doped material layer is a source electrode, the other is a drain electrode, the stacked layer is etched to obtain a vertical through hole and an isolation groove, an insulating layer is formed in the vertical through hole, then the channel layer can be etched from the side direction through the isolation groove, the channel layer on the side wall of the insulating layer is reserved, so that a gap between the first doped material layer and the second doped material layer is formed, and a gate dielectric layer and a gate electrode are formed in the gap. In this way, the source electrode and the drain electrode are horizontal film layers parallel to the surface of the substrate, the channel layer reserved on the side wall of the insulating layer is used as a channel in the vertical direction between the source electrode and the drain electrode, the length of the channel is related to the thickness of the film layer, and high-cost and high-precision etching is not needed, so that a small-size high-performance device can be obtained by using lower cost and simple process.
Based on the method for manufacturing the semiconductor device structure provided in the above embodiment, the embodiment of the present application further provides a semiconductor structure, referring to fig. 14, the semiconductor structure includes:
a substrate;
a stacked layer of a first doped material layer, a channel layer, and a second doped material layer on the substrate;
a vertical via and an isolation trench in the stacked layer, the vertical via having an insulating layer formed therein;
the channel layer is recessed in the isolation trench from the first doped material layer and the second doped material layer, so that a gap is formed between the first doped material layer and the second doped material layer;
and a gate dielectric layer and a gate layer are formed in the gap.
Optionally, the first doped material layer, the channel layer and the second doped material layer are silicon germanium, silicon germanium, or silicon, silicon germanium, silicon, or germanium, germanium tin, germanium, respectively.
Optionally, a buffer layer is formed between the substrate and the first doped material layer.
Optionally, an intrinsic layer of the first doped material layer is formed between the first doped material layer and the channel layer, and between the first doped material layer and the gate dielectric layer, and an intrinsic layer of the second doped material layer is formed between the channel layer and the second doped material layer, and between the gate dielectric layer and the second doped material layer.
Optionally, the insulating layer includes a strained material layer for providing compressive or tensile stress to the channel layer.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for device embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see the section of the method embodiments.
The foregoing is merely a preferred embodiment of the present application, and although the present application has been disclosed in the preferred embodiment, it is not intended to limit the present application. Any person skilled in the art may make many possible variations and modifications to the technical solution of the present application, or modify equivalent embodiments, using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present application, which do not depart from the content of the technical solution of the present application, still fall within the scope of the technical solution of the present application.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:
forming a stacked layer of a first doped material layer, a channel layer, and a second doped material layer on a substrate;
etching the stacked layer to obtain a vertical through hole and an isolation groove, and forming an insulating layer in the vertical through hole;
etching the channel layer from the side direction through the isolation trench, and reserving the channel layer on the side wall of the insulating layer to form a gap between the first doped material layer and the second doped material layer;
and forming a gate dielectric layer and a gate layer in the gap through the isolation trench.
2. The method of claim 1, wherein the laterally etching the channel layer through the isolation trench comprises:
performing a multiple oxidation removal process; the oxidation removal process comprises the following steps: performing an oxidation process of the channel layer to form an oxide layer on the exposed channel layer surface in the isolation trench; and removing the oxide layer.
3. The method of claim 2, wherein the performing an oxidation process of the channel layer comprises:
the channel layer is self-limiting oxidized using plasma or chemistry.
4. The method of claim 1, wherein etching the stacked layers to obtain vertical vias and isolation trenches, forming an insulating layer in the vertical vias, comprises:
etching the stacked layer to obtain an isolation groove, and forming an isolation layer in the isolation groove;
etching the stacked layer to obtain a vertical through hole, and forming an insulating layer in the vertical through hole;
and removing the isolation layer in the isolation trench.
5. The method of any of claims 1-4, wherein the first doped material layer, the channel layer, and the second doped material layer are silicon germanium, silicon germanium, or silicon, silicon germanium, silicon, or germanium, germanium tin, germanium, respectively.
6. The method of any of claims 1-4, wherein a buffer layer is formed between the substrate and the first doped material layer.
7. The method of any of claims 1-4, wherein an intrinsic layer of the first doped material layer is formed between the first doped material layer and the channel layer, and an intrinsic layer of the second doped material layer is formed between the channel layer and the second doped material layer.
8. The method of any of claims 1-4, wherein forming a gate dielectric layer and a gate layer in the gap through the isolation trench comprises:
and depositing a gate dielectric layer and a gate electrode layer, and removing the gate electrode layer and the gate dielectric layer outside the gap through the isolation groove.
9. The method of any of claims 1-4, wherein the insulating layer comprises a layer of strained material for providing compressive or tensile stress to the channel layer.
10. A semiconductor device, comprising:
a substrate;
a stacked layer of a first doped material layer, a channel layer, and a second doped material layer on the substrate;
a vertical via and an isolation trench in the stacked layer, the vertical via having an insulating layer formed therein;
the channel layer is recessed in the isolation trench from the first doped material layer and the second doped material layer, so that a gap is formed between the first doped material layer and the second doped material layer; the channel layer is positioned on the side wall of the insulating layer;
and a gate dielectric layer and a gate layer are formed in the gap.
CN202010494871.9A 2020-06-03 2020-06-03 Semiconductor device and manufacturing method thereof Active CN111613584B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010494871.9A CN111613584B (en) 2020-06-03 2020-06-03 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010494871.9A CN111613584B (en) 2020-06-03 2020-06-03 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN111613584A CN111613584A (en) 2020-09-01
CN111613584B true CN111613584B (en) 2023-07-25

Family

ID=72202305

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010494871.9A Active CN111613584B (en) 2020-06-03 2020-06-03 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN111613584B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115954381B (en) * 2023-03-13 2023-06-06 合肥晶合集成电路股份有限公司 Semiconductor device and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012174836A (en) * 2011-02-21 2012-09-10 Fujitsu Ltd Vertical field effect transistor, manufacturing method of the same and electronic apparatus
CN106158877A (en) * 2016-09-30 2016-11-23 中国科学院微电子研究所 Memory device and manufacture method thereof and include the electronic equipment of this memory device
CN107749421A (en) * 2017-09-30 2018-03-02 中国科学院微电子研究所 Ring gate nano line transistor of vertical stacking and preparation method thereof
CN111106160A (en) * 2019-12-06 2020-05-05 中国科学院微电子研究所 Semiconductor device, method of manufacturing the same, and electronic apparatus including the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012174836A (en) * 2011-02-21 2012-09-10 Fujitsu Ltd Vertical field effect transistor, manufacturing method of the same and electronic apparatus
CN106158877A (en) * 2016-09-30 2016-11-23 中国科学院微电子研究所 Memory device and manufacture method thereof and include the electronic equipment of this memory device
CN107749421A (en) * 2017-09-30 2018-03-02 中国科学院微电子研究所 Ring gate nano line transistor of vertical stacking and preparation method thereof
CN111106160A (en) * 2019-12-06 2020-05-05 中国科学院微电子研究所 Semiconductor device, method of manufacturing the same, and electronic apparatus including the same

Also Published As

Publication number Publication date
CN111613584A (en) 2020-09-01

Similar Documents

Publication Publication Date Title
US7154118B2 (en) Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
KR101729439B1 (en) Finfet with buried insulator layer and method for forming
US10269964B2 (en) FinFETs with source/drain cladding
KR100856437B1 (en) Transistor gate electrode having conductor material layer
KR101637718B1 (en) Fin structure of semiconductor device
US8835936B2 (en) Source and drain doping using doped raised source and drain regions
US20140239354A1 (en) FinFETs and Methods for Forming the Same
US8062938B2 (en) Semiconductor device and method of fabricating the same
US20070132034A1 (en) Isolation body for semiconductor devices and method to form the same
US20160049489A1 (en) Integrated circuits with nanowires and methods of manufacturing the same
US9496395B2 (en) Semiconductor device having a strain feature in a gate spacer and methods of manufacture thereof
KR20110038594A (en) Semiconductor device having silicon on stressed liner(sol)
JP2009105163A (en) Semiconductor device
CN111613584B (en) Semiconductor device and manufacturing method thereof
US9306033B2 (en) Semiconductor device and fabrication method thereof
US20150235906A1 (en) Methods for etching dielectric materials in the fabrication of integrated circuits
CN111599760B (en) Semiconductor device and manufacturing method thereof
CN111599758B (en) Semiconductor device and manufacturing method thereof
CN111599757B (en) Semiconductor device and manufacturing method thereof
KR102549844B1 (en) Semiconductor device and method
CN110729360B (en) Nanotube device and manufacturing method thereof
CN111599759B (en) Semiconductor device and manufacturing method thereof
US11456218B2 (en) Semiconductor device and method for manufacturing the same
CN115719707A (en) Fence device and manufacturing method thereof
KR20020008535A (en) Method of manufacturing a semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant