KR20020008535A - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR20020008535A KR20020008535A KR1020000041873A KR20000041873A KR20020008535A KR 20020008535 A KR20020008535 A KR 20020008535A KR 1020000041873 A KR1020000041873 A KR 1020000041873A KR 20000041873 A KR20000041873 A KR 20000041873A KR 20020008535 A KR20020008535 A KR 20020008535A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 238000000034 method Methods 0.000 claims abstract description 73
- 239000010410 layer Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 238000000407 epitaxy Methods 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 238000007517 polishing process Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 claims description 3
- 229910021193 La 2 O 3 Inorganic materials 0.000 claims description 2
- 229910004491 TaAlN Inorganic materials 0.000 claims description 2
- 229910010037 TiAlN Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 2
- 239000002994 raw material Substances 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 229910002616 GeOx Inorganic materials 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 238000005204 segregation Methods 0.000 abstract description 2
- 229910006990 Si1-xGex Inorganic materials 0.000 abstract 1
- 229910007020 Si1−xGex Inorganic materials 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000013590 bulk material Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 다마신 게이트 패턴을 형성한 후 선택적 에피택시 성장법을 이용하여 Si1-xGex채널을 형성하고, 고유전 게이트 절연막 및 도전층을 형성하여 게이트를 형성함으로써 Ge의 외부 확산에 의한 분리, 프로파일 변형 및 GeOx 형성등의 문제점을 해결할 수 있고, 누설 전류, 전하 이동 특성을 개선하여 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, after forming a damascene gate pattern, a Si 1-x Ge x channel is formed using a selective epitaxy growth method, a high-k gate insulating film and a conductive layer are formed. The present invention relates to a method of manufacturing a semiconductor device capable of solving problems such as separation due to external diffusion of Ge, profile deformation, and formation of GeOx by forming a gate, and improving device reliability by improving leakage current and charge transfer characteristics. .
실리콘 반도체 소자에서 현재 개발 및 연구중인 DRAM 및 논리 소자의 경우 소자의 신호 전달 속도를 최대화하기 위해 워드라인 하부의 채널의 길이를 최소화하는 연구가 주종을 이루고 있다. 한편, Ⅲ-Ⅴ족 반도체의 경우 높은 채널 이동도 (channel mobility)를 이용하는 연구가 주종을 이루고 있다.In the case of DRAM and logic devices, which are currently being developed and studied in silicon semiconductor devices, researches for minimizing the channel length under the word line are mainly performed to maximize the signal transmission speed of the device. On the other hand, in the case of III-V semiconductors, researches using high channel mobility have been mainly used.
실리콘 기판 상부에 SiGe의 채널을 이용하는 이종 접합 바이폴라 트랜지스터 (heterojunction bipolar transtor; HBT)와 같은 구조들은 이종 접합의 전하 억류 (charge confinement) 또는 밴드갭 엔지니어링(bandgap engineering)을 통하여 빠른 신호 전달 속도를 구현하고 있다. 이는 HBT의 경우 후속 열공정이 그리 높지 않고 집적(integration) 또한 DRAM 소자에 비하여 간단하기 때문에 가능하다.Structures such as heterojunction bipolar transistors (HBTs) that use SiGe channels on top of silicon substrates enable fast signal transfer rates through charge confinement or bandgap engineering of heterojunctions. have. This is possible because in the case of HBT, the subsequent thermal process is not so high and integration is also simpler than DRAM devices.
최근, SiGe의 채널을 갖는 MOS 구조도 중요한 연구 과제로 부상되고 있다. 특히 논리 소자의 경우 활성 영역인 소오스 및 드레인을 제외한 후속 열공정의 부담이 적기 때문에 SiGe 채널에 관한 연구가 진행되고 있다. 이와 같은 경우 웰이형성된 반도체 기판을 미리 식각하고 선택적 에피택시 성장법으로 SiGe 또는 델타 도핑 Si 또는 SiGe 채널을 형성하고, 그 상부에 임의 두께의 실리콘 캡핑을 형성하여 후속 게이트 산화와 같은 공정들을 준비하고 있다.In recent years, MOS structures having channels of SiGe have also emerged as important research subjects. In particular, in the case of logic devices, studies on SiGe channels are being conducted because the burden of subsequent thermal processes is reduced except for the active regions of source and drain. In this case, the well-formed semiconductor substrate is etched in advance, and SiGe or delta doped Si or SiGe channels are formed by selective epitaxy growth, and silicon capping of any thickness is formed thereon to prepare processes such as subsequent gate oxidation. have.
그러나, 열산화 공정에 의해 형성된 SiO2막으로 게이트 산화막을 형성할 경우 또는 후속 소오스/드레인 활성화 공정을 실시할 때 고온 공정이 진행된다. 이때 채널에 노출 또는 매립된 SiGex에서 Ge(x)의 양이 일정량(>0.3) 이상일 때, Ge 외부 확산과 같은 질량 이동(mass transport)에 의하여 분리(segregation), 프로파일 변형(profile deformation), GeOx형성과 같은 문제들을 발생시킨다. 이에 의해 누설 전류의 증가 등 소자 구동에 치명적인 악영향을 미칠 수 있다.However, a high temperature process proceeds when a gate oxide film is formed from a SiO 2 film formed by a thermal oxidation process or when a subsequent source / drain activation process is performed. In this case, when the amount of Ge (x) in the SiGe x exposed or buried in the channel is greater than or equal to a certain amount (> 0.3), segregation, profile deformation, Problems such as GeO x formation. This can have a fatal adverse effect on the device driving, such as an increase in leakage current.
본 발명의 목적은 Ge의 외부 확산에 의한 분리, 프로파일 변형 및 GeOx 형성등의 문제점을 해결할 수 있는 반도체 소자의 제조 방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of solving problems such as separation due to external diffusion of Ge, profile deformation and GeOx formation.
본 발명의 다른 목적은 누설 전류, 전하 이동 특성을 개선하여 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조 방법을 제공하는데 있다.Another object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the reliability of the device by improving leakage current, charge transfer characteristics.
본 발명은 다마신 게이트 구조를 이용하여 선택적 에피택시 성장법으로 Si 및 Si1-xGex채널을 형성하고, 고유전 게이트 절연막을 형성하는 방법을 제시한다. 에피택셜 성장 방법에 의해 형성된 막은 주입되는 불순물의 농도를 조절할 수 있고벌크 물질에 존재하는 결함 레벨(defect level)보다 낮은 결함 밀도를 구현할 수 있는 장점이 있다.The present invention proposes a method of forming Si and Si 1-x Ge x channels by a selective epitaxy growth method using a damascene gate structure and forming a high-k gate insulating film. The film formed by the epitaxial growth method has the advantage of controlling the concentration of the implanted impurities and realizing a defect density lower than the defect level present in the bulk material.
본 발명에서는 고온의 열공정들이 대부분 진행된 다마신 구조를 이용하고 저온에서 증착에서 게이트 절연막을 적용한다. 특히, 채널 영역에 Ge의 양이 15∼20% 정도의 Si0.8Ge0.2을 적용할 경우 일반적으로 Si에 비해 전자 이동도는 8∼10% 정도, 홀 이동도는 20% 정도 개선할 수 있다. 또한, 게이트 산화막으로 알루미늄 산화막과 같은 고유전막을 증착 적용함으로써 소자의 누설 전류, 전하 전달 특성들을 개선할 수 있다. 뿐만 아니라, 상기한 장점들과 결합될 때 CMOSFET에서 전자와 홀의 이동도를 증가시켜 소자의 신호 전달 속도를 극대화할 수 있다.In the present invention, a damascene structure in which high temperature thermal processes are mostly used, and a gate insulating film is applied in a deposition at low temperature. In particular, when Si 0.8 Ge 0.2 having an amount of Ge of about 15 to 20% is applied to the channel region, electron mobility can be improved by about 8 to 10% and hole mobility by about 20% compared to Si. In addition, by applying a high-k dielectric film such as an aluminum oxide film to the gate oxide film, leakage current and charge transfer characteristics of the device may be improved. In addition, when combined with the above advantages, it is possible to maximize the device's signal transmission speed by increasing the mobility of electrons and holes in the CMOSFET.
도 1(a) 내지 도 1(d)는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (d) are cross-sectional views of devices sequentially shown to explain a method for manufacturing a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
101 : 반도체 기판 102 : 소자 분리막101 semiconductor substrate 102 device isolation film
103 : 더미 산화막 104 : 더미 폴리실리콘막103: dummy oxide film 104: dummy polysilicon film
105 : 스페이서 106 : 접합부105: spacer 106: junction
107 : 층간 절연막 108 : Si1-xGex막107: interlayer insulating film 108: Si 1-x Ge x film
109 : 게이트 산화막 110 : 도전층109: gate oxide film 110: conductive layer
본 발명에 따른 반도체 소자의 제조 방법은 소정 영역에 소자 분리막이 형성된 반도체 기판의 활성 영역 상부에 더미 산화막 및 더미 폴리실리콘막이 적층된 게이트 패턴을 형성하고 그 측벽에 스페이서를 형성하는 단계와, 불순물 이온 주입 공정을 실시하여 상기 반도체 기판 상에 접합부를 형성하는 단계와, 전체 구조 상부에 층간 절연막을 형성한 후 연마 공정을 실시하여 상기 게이트 패턴을 노출시키는 단계와, 상기 노출된 게이트 패턴을 제거하고, 상기 반도체 기판을 소정 깊이로 식각하는 단계와, 상기 식각된 반도체 기판에 선택적 에피택시 성장법을 이용하여 Si1-xGex막을 형성하여 채널을 형성하는 단계와, 전체 구조 상부에 게이트 산화막 및도전층을 형성한 후 연마 공정에 의해 상기 층간 절연막을 노출시켜 게이트를 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention includes forming a gate pattern in which a dummy oxide film and a dummy polysilicon film are stacked on an active region of a semiconductor substrate in which a device isolation film is formed in a predetermined region, and forming spacers on sidewalls thereof; Performing an implantation process to form a junction on the semiconductor substrate, forming an interlayer insulating film over the entire structure, and then performing a polishing process to expose the gate pattern, and removing the exposed gate pattern, Etching the semiconductor substrate to a predetermined depth, forming a channel by forming a Si 1-x Ge x film on the etched semiconductor substrate using a selective epitaxy growth method, and forming a channel on the entire structure, and forming a gate oxide film and a conductive layer After forming the layer, exposing the interlayer insulating layer to form a gate by a polishing process. Characterized in that made in box.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1(a) 내지 도 1(d)는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) to 1 (d) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a semiconductor device according to the present invention.
도 1(a)를 참조하면, 반도체 기판(101) 상의 소정 영역에 소자 분리막(102)을 형성한다. 소자 분리막(102)는 LOCOS 방법을 이용하거나 트렌치형으로 형성할 수 있다. 전체 구조 상부에 더미 산화막(103) 및 더미 폴리실리콘막(104)을 형성한 후 게이트 마스크를 이용한 리소그라피 공정 및 식각 공정으로 패터닝하여 게이트 패턴을 형성한다. 더미 산화막(103)은 650∼950℃의 온도를 유지하는 반응로에서 습식 또는 건식 산화 방법을 이용하여 20∼80Å의 두께로 형성한다. 또한, 더미 폴리실리콘막(104)은 도프트 또는 언도프트 폴리실리콘막을 이용하여 700∼3500Å의 두께로 형성한다. 저농도 불순물 이온 주입 공정을 실시하여 반도체 기판상에 저농도 불순물 영역을 형성한다. 전체 구조 상부에 절연막을 형성한 후 전면 식각 공정을 실시하여 게이트 전극 측벽에 스페이서(105)를 형성한다. 스페이서(105)를 형성하기 위한 절연막은 SiO2, SiON, Al2O3, SiC, AlN중 어느 하나를 사용한다. 고농도 불순물 이온 주입 공정을 실시하여 반도체 기판 상에 소오스 및 드레인 접합부(106)를 형성한다. 그리고, 접합부(106)를 활성화시키기 위해 800∼1000℃의온도에서 열처리 공정을 실시한다. 전체 구조 상부에 층간 절연막(107)을 형성한 후 연마 공정을 실시하여 게이트 패턴의 상부를 노출시킨다. 층간 절연막(107)으로는 BPSG막, HDP PSG막, APL막중 어느 하나를 이용한다.Referring to FIG. 1A, the device isolation layer 102 is formed in a predetermined region on the semiconductor substrate 101. The device isolation layer 102 may be formed using a LOCOS method or in a trench type. After forming the dummy oxide film 103 and the dummy polysilicon film 104 on the entire structure, the gate pattern is formed by a lithography process and an etching process using a gate mask. The dummy oxide film 103 is formed to a thickness of 20 to 80 kPa using a wet or dry oxidation method in a reactor maintaining a temperature of 650 to 950 ° C. In addition, the dummy polysilicon film 104 is formed to a thickness of 700-3500 kPa using a dope or undoped polysilicon film. A low concentration impurity ion implantation process is performed to form a low concentration impurity region on the semiconductor substrate. After the insulating film is formed on the entire structure, the entire surface etching process is performed to form the spacers 105 on the sidewalls of the gate electrodes. As the insulating film for forming the spacer 105, any one of SiO 2 , SiON, Al 2 O 3 , SiC, and AlN is used. A high concentration impurity ion implantation process is performed to form the source and drain junctions 106 on the semiconductor substrate. And in order to activate the junction part 106, the heat processing process is implemented at the temperature of 800-1000 degreeC. After forming the interlayer insulating film 107 over the entire structure, a polishing process is performed to expose the upper portion of the gate pattern. As the interlayer insulating film 107, any one of a BPSG film, an HDP PSG film, and an APL film is used.
도 1(b)를 참조하면, 노출된 더미 폴리실리콘막(104) 및 더미 산화막(103)을 제거하고, 계속적인 식각 공정으로 반도체 기판(101)을 50∼500Å 정도 식각한다. 더미 폴리실리콘막(104)은 NH4OH:H20가 1:6으로 혼합된 용액 또는 TMAH[Tetra Methyl Ammonium Hydroxide; N(CH3)4OH]를 이용하여 제거하고, 더미 산화막(103)은 50:1 HF 또는 100:1 HF를 이용하여 제거한다. 이후 식각된 반도체 기판(101)의 손상을 보상하기 위해 희생 산화막을 성장시킨 후 제거하거나, 고온 환원성 분위기에서 열처리 공정을 실시한다.Referring to FIG. 1B, the exposed dummy polysilicon film 104 and the dummy oxide film 103 are removed, and the semiconductor substrate 101 is etched by about 50 to 500 kPa by a continuous etching process. The dummy polysilicon film 104 may be a solution in which NH 4 OH: H 2 O is 1: 6 mixed or TMAH [Tetra Methyl Ammonium Hydroxide; N (CH 3 ) 4 OH], and the dummy oxide film 103 is removed using 50: 1 HF or 100: 1 HF. Thereafter, in order to compensate for the damage of the etched semiconductor substrate 101, a sacrificial oxide film is grown and removed, or a heat treatment process is performed in a high temperature reducing atmosphere.
도 1(c)를 참조하면, 선택적 에피택시 성장법을 이용하여 Si1-xGex(x=0.05∼ 0.35)막(108)을 30∼1000Å의 두께로 성장시켜 채널을 형성한다. Si1-xGex막(108)은 UHUCVD 방법 또는 LPCVD 방법으로 형성한다. UHVCVD 방법으로 Si1-xGex막(108)을 형성하기 위해서는 1E-4∼1E-3Torr의 압력과 500∼700℃의 온도를 유지하는 챔버에 GeH4가스를 2∼10sccm, Si2H6가스를 2∼10sccm, Cl2가스를 2sccm 미만 유입시켜 10초∼3분 정도 공정을 실시한다. 또한, LPCVD 방법으로 Si1-xGex막(108)을 형성하기 위해서는 10∼100Torr의 압력과 650∼750℃의 온도를 유지하는 챔버에 GeH4가스를100∼500sccm, Si2H6가스를 100∼200sccm, HCl 가스를 100∼150sccm 유입시켜 20초∼10분 정도 공정을 실시한다. 한편, Si1-xGex막(108) 상부에 Si1-xGex막(108)이 노출됨으로써 발생될 수 있는 문제를 해결하기 위해 선택적 에피택시 성장법을 이용하여 Si막을 30∼100Å의 두께로 형성할 수 있는데, UHUCVD 방법 또는 LPCVD 방법을 이용한다. UHVCVD 방법으로 Si막을 형성하기 위해서는 1E-4∼1E-3Torr의 압력과 500∼700℃의 온도를 유지하는 챔버에 Si2H6가스를 2∼10sccm, Cl2가스를 2sccm 미만 유입시켜 10초∼3분 정도 공정을 실시한다. 또한, LPCVD 방법으로 Si막을 형성하기 위해서는 10∼100Torr의 압력과 750∼850℃의 온도를 유지하는 챔버에 Si2H6가스를 100∼200sccm, HCl 가스를 100∼150sccm 유입시켜 20초∼10분 정도 공정을 실시한다. 한편, Si1-xGex막과 Si막을 교대로 적층하여 다중 양자 우물(multiple quantum well) 구조를 갖는 채널을 형성할 수 있다. 이 경우 Si1-xGex막을 10∼50Å 정도의 두께로 성장시키고, Si막을 10∼50Å의 두께로 성장시키는 공정을 반복하여 채널 전체 두께가 30∼1000Å 정도되도록 한다.Referring to FIG. 1C, a channel is formed by growing a Si 1-x Ge x (x = 0.05 to 0.35) film 108 to a thickness of 30 to 1000 하여 using a selective epitaxy growth method. The Si 1-x Ge x film 108 is formed by the UHUCVD method or the LPCVD method. In order to form the Si 1-x Ge x film 108 by the UHVCVD method, 2-10 sccm of GeH 4 gas and Si 2 H 6 were placed in a chamber maintained at a pressure of 1E-4 to 1E-3 Torr and a temperature of 500 to 700 ° C. 2 to 10 sccm of gas and less than 2 sccm of Cl 2 gas are introduced to perform the process for 10 seconds to 3 minutes. In addition, in order to form the Si 1-x Ge x film 108 by the LPCVD method, 100-500 sccm of GeH 4 gas and Si 2 H 6 gas were added to a chamber maintained at a pressure of 10-100 Torr and a temperature of 650-750 ° C. 100-200 sccm and 100-150 sccm of HCl gas are introduced, and a process is performed for 20 second-about 10 minutes. On the other hand, the 30~100Å Si film by using a selective epitaxial growth method to solve a problem that may be emitted by Si 1-x Ge x layer 108 is exposed to the top Si 1-x Ge x film 108 It can be formed in a thickness, using the UHUCVD method or LPCVD method. In order to form a Si film by the UHVCVD method, 2 to 10 sccm of Si 2 H 6 gas and less than 2 sccm are introduced into a chamber maintaining a pressure of 1E-4 to 1E-3 Torr and a temperature of 500 to 700 ° C. Run the process for about 3 minutes. In addition, in order to form a Si film by the LPCVD method, 100 to 200 sccm of Si 2 H 6 gas and 100 to 150 sccm of HCl gas were introduced into a chamber maintaining a pressure of 10 to 100 Torr and a temperature of 750 to 850 ° C. for 20 seconds to 10 minutes. Carry out the degree process. Meanwhile, the Si 1-x Ge x film and the Si film may be alternately stacked to form a channel having a multiple quantum well structure. In this case, the Si 1-x Ge x film is grown to a thickness of about 10 to 50 GPa, and the Si film is grown to a thickness of 10 to 50 GPa, so that the total channel thickness is about 30 to 1000 GPa.
도 1(d)를 참조하면, 전체 구조 상부에 게이트 산화막(109)을 형성한 후 도전층(110)을 형성한다. 게이트 산화막(109)은 SiO2막, Al2O3막, Ta2O5막, ZrO2막, HfO2막 및 La2O3막중 어느 하나로 형성하거나, 상기 막들을 형성하기 위한 원료 물질을 혼합된 막으로 형성한다. 또한, 게이트 산화막(109)은 10∼45Å의 유효 두께 (effectove thickness)를 갖도록 형성한다. 도전층(110)은 텅스텐막, 텅스텐 폴리사이드막 및 폴리실리콘막중 어느 하나로 300∼2000Å의 두께로 형성한다. 게이트 산화막(109)을 형성한 후 도전층(110)을 형성하기 전에 장벽 금속층을 형성한다. 장벽 금속층으로는 ZrN막, HfN막, TiAlN막, TaAlN막, TiN막, TaN막, WN막 및 Ta막중 어느 하나를 사용하며, 50∼1000Å의 두께로 형성한다. 도전층(110) 및 게이트 산화막(109)을 연마하여 게이트 전극을 형성한다.Referring to FIG. 1D, a gate oxide layer 109 is formed over an entire structure, and then a conductive layer 110 is formed. The gate oxide film 109 is formed of any one of SiO 2 film, Al 2 O 3 film, Ta 2 O 5 film, ZrO 2 film, HfO 2 film and La 2 O 3 film, or a mixture of raw materials for forming the films. To form a film. In addition, the gate oxide film 109 is formed to have an effective thickness of 10 to 45 kPa. The conductive layer 110 is formed of any one of a tungsten film, a tungsten polyside film, and a polysilicon film to a thickness of 300 to 2000 micrometers. A barrier metal layer is formed after the gate oxide film 109 is formed and before the conductive layer 110 is formed. As the barrier metal layer, any one of a ZrN film, an HfN film, a TiAlN film, a TaAlN film, a TiN film, a TaN film, a WN film, and a Ta film is used. The barrier metal layer is formed to a thickness of 50 to 1000 GPa. The conductive layer 110 and the gate oxide film 109 are polished to form a gate electrode.
상술한 바와 같이 본 발명에 의하면 다마신 게이트 구조를 형성한 후 선택적 에피택시 성장법을 이용하여 Si1-xGex막 채널을 형성하고, 고유전 게이트 산화막 및 게이트 전극을 형성함으로써 Ge의 외부 확산에 의한 분리, 프로파일 변형 및 GeOx 형성등의 문제점을 해결할 수 있고, 누설 전류, 전하 이동 특성을 개선하여 소자의 신뢰성을 향상시킬 수 있다. 또한, 고속 소자의 개발을 조기에 달성할 수 있다.As described above, according to the present invention, after the damascene gate structure is formed, the Si 1-x Ge x film channel is formed using the selective epitaxy growth method, and the high-dielectric gate oxide film and the gate electrode are formed to diffuse out of Ge. Problems such as separation, profile deformation and GeOx formation can be solved, and the reliability of the device can be improved by improving leakage current and charge transfer characteristics. In addition, the development of a high speed device can be achieved early.
Claims (27)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100451038B1 (en) * | 2000-12-13 | 2004-10-02 | 주식회사 하이닉스반도체 | Method of manufacturing a transistor in a semiconductor device |
| KR100680505B1 (en) * | 2005-12-14 | 2007-02-08 | 동부일렉트로닉스 주식회사 | Manufacturing method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100451038B1 (en) * | 2000-12-13 | 2004-10-02 | 주식회사 하이닉스반도체 | Method of manufacturing a transistor in a semiconductor device |
| KR100680505B1 (en) * | 2005-12-14 | 2007-02-08 | 동부일렉트로닉스 주식회사 | Manufacturing method of semiconductor device |
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