CN104020601A - 彩膜基板及显示装置 - Google Patents

彩膜基板及显示装置 Download PDF

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CN104020601A
CN104020601A CN201410235518.3A CN201410235518A CN104020601A CN 104020601 A CN104020601 A CN 104020601A CN 201410235518 A CN201410235518 A CN 201410235518A CN 104020601 A CN104020601 A CN 104020601A
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吕启标
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to PCT/CN2014/079610 priority patent/WO2015180207A1/zh
Priority to US14/383,014 priority patent/US20160252767A1/en
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    • GPHYSICS
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    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78663Amorphous silicon transistors
    • H01L29/78669Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/13396Spacers having different sizes

Abstract

本发明公开了一种彩膜基板及显示装置,属于显示技术领域,解决了由于阵列基板与彩膜基板在对盒过程中出现对位偏差,而导致漏光的技术问题。该彩膜基板,包括多个间隙子;其中,对应于阵列基板上的数据线的两侧设置各至少一个所述的间隙子。本发明可用于液晶电视、液晶显示器、手机、平板电脑等。

Description

彩膜基板及显示装置
技术领域
本发明涉及显示技术领域,具体地说,涉及一种彩膜基板及显示装置。
背景技术
随着显示技术的发展,液晶显示器已经成为最为常见的平板显示装置。在液晶显示器的制造过程中,都是先独立制造好阵列基板和彩膜基板,再将阵列基板和彩膜基板进行对盒,形成液晶盒。其中,彩膜基板上的黑矩阵与阵列基板上的扫描线(栅线)、数据线、薄膜晶体管(TFT)等部件的位置相对应,以遮挡住扫描线、数据线、薄膜晶体管等部件。
但是,在阵列基板和彩膜基板进行对盒的过程中,特别是对于大尺寸的液晶显示器,阵列基板与彩膜基板之间经常会出现对位偏差,使黑矩阵与扫描线、数据线、薄膜晶体管等部件之间发生错位。其中,黑矩阵与数据线之间发生错位的情况较多,导致数据线的一侧出现漏光,而发生串扰(V-Crosstalk)现象,影响液晶显示器的显示效果。
发明内容
本发明的目的在于提供一种彩膜基板及显示装置,以解决由于阵列基板与彩膜基板在对盒过程中出现对位偏差,而导致漏光的技术问题。
本发明提供一种彩膜基板,包括多个间隙子;
其中,对应于阵列基板上的数据线的两侧设置各至少一个所述的间隙子。
优选的,对应于所述数据线的两侧设置的间隙子之间的间距与所述数据线的宽度之差在2至5微米之间。
优选的,对应于所述数据线的两侧设置有成对设置的间隙子,一对间隙子分别对应于所述数据线的两侧。
可选的,所述成对设置的间隙子为成对设置的主间隙子或成对设置的次间隙子。
优选的,所述成对设置的间隙子均为成对设置的次间隙子,所述彩膜基板还包括设置于所述衬底基板上的主间隙子;
所述主间隙子与阵列基板上的凸台的位置对应。
或者,所述成对设置的间隙子均为成对设置的主间隙子,所述彩膜基板还包括设置于所述衬底基板上的次间隙子;
所述主间隙子的高度大于所述次间隙子的高度。
本发明还提供一种显示装置,包括阵列基板和上述的彩膜基板。
其中,所述阵列基板上设置有纵横交错的扫描线和数据线,对应于所述数据线两侧设置的间隙子的位置,还对应于所述扫描线与所述数据线的交叠处;
在所述交叠处,所述数据线位于所述扫描线之上,且所述数据线与所述扫描线之间设置有栅绝缘层。
或者,所述数据线与所述栅绝缘层之间还设置有半导体层和掺杂半导体层。
进一步,所述阵列基板上设置有凸台。
进一步,所述凸台由半导体层、掺杂半导体层和金属层形成。
本发明带来了以下有益效果:本发明提供的彩膜基板包括多个间隙子,并且对应于阵列基板上的数据线的两侧,各有至少一个间隙子。因为阵列基板上的数据线本身具有一定的厚度,所以数据线自身会高出其两侧区域。在阵列基板与彩膜基板对盒的过程中,数据线就会嵌入分别位于其两侧的间隙子之间形成的凹槽中,使数据线卡在两个间隙子中间。这样就能够利用对应于数据线两侧的间隙子对数据线进行限位,使数据线与黑矩阵能够准确对位,从而解决了由于阵列基板与彩膜基板在对盒过程中出现对位偏差,而导致漏光的技术问题。
本发明的其它特征和优点将在随后的说明书中阐述,并且,部分地从说明书中变得显而易见,或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例描述中所需要的附图做简单的介绍:
图1是本发明实施例一提供的显示装置的示意图;
图2是图1中沿A-A方向的剖视图;
图3是本发明实施例二提供的显示装置的剖视图;
图4是本发明实施例三提供的显示装置的示意图;
图5是图4中沿A-A方向的剖视图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式,借此对本发明如何应用技术手段来解决技术问题,并达成技术效果的实现过程能充分理解并据以实施。需要说明的是,只要不构成冲突,本发明中的各个实施例以及各实施例中的各个特征可以相互结合,所形成的技术方案均在本发明的保护范围之内。
实施例一:
如图2所示,本发明实施例提供的彩膜基板1包括衬底基板10,以及设置于衬底基板10上的滤光层(图中未示出)、黑矩阵11、公共电极12和多个间隙子14。其中,对应于阵列基板2上的数据线22的两侧设置各至少一个的间隙子14。
因为阵列基板2上的数据线22本身具有一定的厚度,所以数据线22自身会高出其两侧区域。本发明实施例提供的彩膜基板1在与阵列基板2对盒的过程中,数据线22就会嵌入分别位于其两侧的间隙子14之间形成的凹槽中,使数据线22卡在两个间隙子14中间。这样就能够利用对应于数据线22两侧的间隙子14对数据线22进行限位,使数据线22与黑矩阵11能够准确对位,从而解决了由于阵列基板与彩膜基板在对盒过程中出现对位偏差,而导致漏光的技术问题。
作为一个优选方案,对应于数据线22的两侧设置有成对设置的间隙子14,一对间隙子14分别对应于数据线22的两侧。
对应于数据线22的两侧设置的一对间隙子14之间的间距取决于阵列基板上数据线的宽度。若要使一对间隙子14之间的间距恰好等于数据线的宽度,在实际的制造过程中难度很大。因此,可以使一对间隙子14之间的间距略大于数据线的宽度,一对间隙子14之间的间距与数据线的宽度之差优选在2至5微米之间,使一对间隙子14能够尽可能紧的卡住数据线,以保证数据线与黑矩阵11之间的对位更加精准。
如图1和图2所示,本发明实施例还提供一种显示装置,可以是液晶电视、液晶显示器、手机、平板电脑等。该显示装置包括阵列基板2和上述本实施例提供的彩膜基板1。彩膜基板1上的间隙子通常可分为主间隙子和次间隙子两种。本实施例中,成对设置的间隙子为成对设置的次间隙子14,而主间隙子13可以零散的(不成对的)设置于衬底基板10上。
阵列基板2包括设置在衬底基板20上的纵横交错的扫描线21、数据线22,以及栅绝缘层23、钝化层24等结构。彩膜基板1上的主间隙子13和次间隙子14均对应位于扫描线21的范围之内,并且对应于数据线22两侧的成对设置次间隙子14的位置,还对应于扫描线21与数据线22的交叠处。本实施例中,在扫描线21与数据线22的交叠处,数据线22位于扫描线21之上,数据线22与扫描线21之间依次设置有栅绝缘层23、半导体层25(非晶硅层)和掺杂半导体层26(n型非晶硅层),此种结构的阵列基板2通常是经过四次掩膜板构图工艺制成的。
此外,阵列基板2上还设置有用于支撑主间隙子13的凸台27,且主间隙子13与阵列基板2上的凸台27的位置对应。凸台27由位于栅绝缘层23上的半导体层25、掺杂半导体层26和金属层220形成。其中,金属层220与数据线22位于同层,所以在阵列基板2的制造过程中,金属层220与数据线22可以同步形成,并且凸台27的高度与数据线22的高度是相等的。
本实施例中,在彩膜基板1与阵列基板2进行对盒之前,主间隙子13与次间隙子14的高度是相等的,以便于主间隙子13和次间隙子14能够同步的形成于衬底基板10上。
在彩膜基板1与阵列基板2的对盒过程中,主间隙子13的末端会抵靠住阵列基板2上的凸台27。主间隙子13在压力的作用下会被压缩,而次间隙子14还未与阵列基板2接触,所以主间隙子13的高度会变得小于次间隙子14的高度。又因为凸台27与数据线22的高度相等,所以此时次间隙子14的末端会低于数据线22的上沿,数据线22就会嵌入成对设置的次间隙子14之间形成的凹槽中,使数据线22卡在一对次间隙子14中间。这样就能够利用成对设置的次间隙子14对数据线22进行限位,使数据线22与黑矩阵11能够准确对位,从而解决了由于阵列基板与彩膜基板在对盒过程中出现对位偏差,而导致漏光的技术问题。
在彩膜基板1与阵列基板2对盒之后,在一般情况下,仅主间隙子13与阵列基板2上的凸台27接触,起到主要支撑作用,保持彩膜基板1与阵列基板2之间的盒厚,而次间隙子14与阵列基板2不接触。当彩膜基板1受到外部压力时,次间隙子14才会与阵列基板2相接触,从而起到辅助支撑作用。
通常情况下,彩膜基板上次间隙子的数量较多,而主间隙子的数量较少。并且,现有技术中,在每个扫描线与数据线的交叠处,都会在数据线的一侧设置一个次间隙子,或设置一个主间隙子。本发明实施例提供的彩膜基板,可以在不改变现有的主间隙子和次间隙子的数量的前提下实现,只需要改变次间隙子的位置,使原有的零散设置的次间隙子重新组合为成对设置的次间隙子,即可利用成对设置的次间隙子对数据线进行限位,从而解决了由于阵列基板与彩膜基板在对盒过程中出现对位偏差,而导致漏光的技术问题。
当然,为达到更好的技术效果,也可以适当增加次间隙子的数量。例如,可以在每个扫描线与数据线的交叠处,设置两对或更多对次间隙子,以增强成对设置的次间隙子对数据线的限位作用。
实施例二:
本实施例与实施例一基本相同,其不同点在于,如图3所示,本实施例的阵列基板2中,在扫描线21与数据线22的交叠处,数据线22位于扫描线21之上,而数据线22与扫描线21之间仅设置有栅绝缘层23,此种结构的阵列基板2通常是经过五次掩膜板构图工艺制成的。
因为半导体层和掺杂半导体层的厚度(相比于数据线)非常小,所以本实施例中数据线22的高度,与实施例一中数据线的高度是基本相等的。因此,本实施例中,成对设置的次间隙子14也能够很好的起到对数据线22的限位作用,使数据线22与黑矩阵11能够准确对位,以达到与实施例一相同的技术效果。
实施例三:
如图4和图5所示,本发明实施例提供的彩膜基板1包括衬底基板10,以及设置于衬底基板10上的滤光层(图中未示出)、黑矩阵11、公共电极12和多个间隙子13。其中,对应于阵列基板2上的数据线22的两侧设置有成对设置的间隙子13,一对间隙子13分别对应于数据线22的两侧。
本实施例中,成对设置的间隙子为成对设置的主间隙子13,而彩膜基板1上还包括设置于衬底基板10上的零散的(不成对的)次间隙子14,并且主间隙子13的高度大于次间隙子14的高度。
本发明实施例还提供一种显示装置,包括阵列基板2和上述本实施例提供的彩膜基板1。
其中,阵列基板2包括设置在衬底基板20上的纵横交错的扫描线21、数据线22,以及栅绝缘层23、钝化层24等结构。彩膜基板1上的主间隙子13和次间隙子14均对应位于扫描线21的范围之内,并且对应于数据线22两侧的成对设置次间隙子14的位置,还对应于扫描线21与数据线22的交叠处。本实施例中,在扫描线21与数据线22的交叠处,数据线22位于扫描线21之上,数据线22与扫描线21之间依次设置有栅绝缘层23、半导体层25和掺杂半导体层26。在其他实施方式中,在扫描线与数据线的交叠处,数据线与扫描线之间也可以仅设置有栅绝缘层(与实施例二相似)。
在彩膜基板1与阵列基板2的对盒过程中,因为主间隙子13的高度大于次间隙子14的高度,所以主间隙子13的末端会抵靠住阵列基板2上。并且,数据线22会嵌入成对设置的主间隙子13之间形成的凹槽中,使数据线22卡在一对主间隙子13中间。这样就能够利用成对设置的主间隙子13对数据线22进行限位,使数据线22与黑矩阵11能够准确对位,从而解决了由于阵列基板与彩膜基板在对盒过程中出现对位偏差,而导致漏光的技术问题。
在彩膜基板1与阵列基板2对盒之后,在一般情况下,仅主间隙子13与阵列基板2接触,起到主要支撑作用,保持彩膜基板1与阵列基板2之间的盒厚,而次间隙子14与阵列基板2不接触。当彩膜基板1受到外部压力时,次间隙子14才会与阵列基板2相接触,从而起到辅助支撑作用。
应当说明的是,在其他实施方式中,还可以将实施例三与实施例一(或实施例二)相结合。也就是,彩膜基板上可以同时包括成对设置的主间隙子和成对设置的次间隙子,则该彩膜基板可以包括以下四种间隙子。
①成对设置的主间隙子,其高度较大。该成对设置的主间隙子,在彩膜基板与阵列基板的对盒过程中,起到对数据线限位的作用;在彩膜基板与阵列基板的对盒之后,起主要支撑作用。
②成对设置的次间隙子,其高度较小(小于第①种主间隙子)。该成对设置的次间隙子,在彩膜基板与阵列基板的对盒过程中,起到对数据线限位的作用;在彩膜基板与阵列基板的对盒之后,起辅助支撑作用。
③零散(不成对)设置的次间隙子,其高度较小(可以与第②种次间隙子相同)。该零散设置的次间隙子,在彩膜基板与阵列基板的对盒之后,起辅助支撑作用。
④零散(不成对)设置的主间隙子,其高度可以与第①种主间隙子相同;或者也可以与第②种、第③种次间隙子的高度相同,并且在阵列基板上对应设置凸台。该零散设置的主间隙子,在彩膜基板与阵列基板的对盒之后,起主要支撑作用。
虽然本发明所公开的实施方式如上,但所述的内容只是为了便于理解本发明而采用的实施方式,并非用以限定本发明。任何本发明所属技术领域内的技术人员,在不脱离本发明所揭露的精神和范围的前提下,可以在实施的形式上及细节上作任何的修改与变化,但本发明的专利保护范围,仍须以所附的权利要求书所界定的范围为准。

Claims (11)

1.一种彩膜基板,包括多个间隙子;
其中,对应于阵列基板上的数据线的两侧设置各至少一个所述的间隙子。
2.如权利要求1所述的彩膜基板,其特征在于,对应于所述数据线的两侧设置的间隙子之间的间距与所述数据线的宽度之差在2至5微米之间。
3.如权利要求1所述的彩膜基板,其特征在于,对应于所述数据线的两侧设置有成对设置的间隙子,一对间隙子分别对应于所述数据线的两侧。
4.如权利要求3所述的彩膜基板,其特征在于,所述成对设置的间隙子为成对设置的主间隙子或成对设置的次间隙子。
5.如权利要求4所述的彩膜基板,其特征在于,所述成对设置的间隙子均为成对设置的次间隙子,所述彩膜基板还包括设置于所述衬底基板上的主间隙子;
所述主间隙子与阵列基板上的凸台的位置对应。
6.如权利要求4所述的彩膜基板,其特征在于,所述成对设置的间隙子均为成对设置的主间隙子,所述彩膜基板还包括设置于所述衬底基板上的次间隙子;
所述主间隙子的高度大于所述次间隙子的高度。
7.一种显示装置,包括阵列基板和如权利要求1至6任一项所述的彩膜基板。
8.如权利要求7所述的显示装置,其特征在于,所述阵列基板上设置有纵横交错的扫描线和数据线,对应于所述数据线两侧设置的间隙子的位置,还对应于所述扫描线与所述数据线的交叠处;
在所述交叠处,所述数据线位于所述扫描线之上,且所述数据线与所述扫描线之间设置有栅绝缘层。
9.如权利要求8所述的显示装置,其特征在于,所述数据线与所述栅绝缘层之间还设置有半导体层和掺杂半导体层。
10.如权利要求7所述的显示装置,其特征在于,所述阵列基板上设置有凸台。
11.如权利要求10所述的显示装置,其特征在于,所述凸台由半导体层、掺杂半导体层和金属层形成。
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