CN103969676A - Controllable multi-channel charge reader - Google Patents
Controllable multi-channel charge reader Download PDFInfo
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- CN103969676A CN103969676A CN201410199336.5A CN201410199336A CN103969676A CN 103969676 A CN103969676 A CN 103969676A CN 201410199336 A CN201410199336 A CN 201410199336A CN 103969676 A CN103969676 A CN 103969676A
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Abstract
The invention relates to the technical field of multi-channel charge front-end reading circuits for beam monitoring, in particular to a controllable multi-channel charge reader. The controllable multi-channel charge reader is characterized by comprising a speed-sensitive switch, integrators with a releasing function, a multiplexer, a control logic circuit, a differential output driving circuit and a data acquisition card which are connected in sequence, the charge reader is used for reading charge (current) signals of a beam monitoring stripping ionization chamber, the measuring range is controllable, the integration duration is controllable, the working mode (continuous reading/intermittent reading) is controllable, and using is flexible; each channel contains two integrators (A and B), the two integrators can work in a time-sharing mode, and then signal processing efficiency is improved; due to the fact that a multiplexing circuit is adopted for serial output of signals, the complexity of data acquisition and the manufacturing cost of a processing system can be effectively reduced, and the accuracy of a heavy ion cancer treatment system is improved. The circuit is high in accuracy, linearity and flexibility and simple in structure.
Description
Technical field
The present invention relates to the hyperchannel electric charge front end sensing circuit technical field for beam monitoring, especially relate to a kind of controllable type hyperchannel charger-reader.
Background technology
Along with the development of heavy-ion cancer therapy technology, in order to reach better result for the treatment of, treatment terminal is more and more higher to the requirement of quality of beam.In heavy-ion cancer therapy device, the real-time control measurement of line space distribution is one of key component in this device.The line of heavy-ion cancer therapy device is exported multichannel faint electric charge (electric current) signal by the itemize ionization chamber for the treatment of terminal, then can realize the Real-Time Monitoring of line space distribution by hyperchannel electric charge (electric current) sensing circuit.Under normal circumstances, terminal for cancer is less for electric charge (electric current) signal of the itemize ionization chamber output of beam monitoring, port number is more, adopt the real-time change-over circuit of current/voltage of prior art can cause data volume very large, real-time data transmission and processing requirements to rear class are higher, cause like this manufacturing cost quite expensive, secondly neighbourhood noise is also larger to the interference of circuit, affects the accuracy of beam monitoring.
Summary of the invention
The object of the invention is to avoid the deficiencies in the prior art that a kind of controllable type hyperchannel charger-reader is provided, thereby effectively solve the problem of prior art.
For achieving the above object, the technical scheme that the present invention takes is: described a kind of controllable type hyperchannel charger-reader, be characterized in comprising connected successively speed-sensitive switch, integrator, multiplexer, control logic circuit, difference output driving circuit and data collecting card with drainage function, described speed-sensitive switch comprises 16 groups of speed-sensitive switches that Yu Shi six road input signals are connected, and every group of speed-sensitive switch is by the two-way speed-sensitive switch S being connected side by side
aiand S
bi, two-way speed-sensitive switch S
aiand S
bibe connected with integrator A sum-product intergrator B respectively; The output terminal of integrator A is connected to multiplexer A, and the output terminal of integrator B is connected to multiplexer B; The output terminal of multiplexer A and multiplexer B is connected respectively to difference output driving circuit, and the output terminal of difference output driving circuit is connected to the analog differential input end of data collecting card; Data collecting card is connected with control logic circuit and carries out two-way communication, and control logic circuit is connected with speed-sensitive switch.
The digital output end of described data collecting card sends external trigger signal to control logic circuit, and control logic circuit transmission collection clock signal and trigger collection signal are to the digital input end of data collecting card; The control signal control multiplexer A of described control logic circuit after by light-coupled isolation and channel selecting and the switching of multiplexer B; The disconnection of the control signal control speed-sensitive switch of control logic circuit after by light-coupled isolation is with closed.
Described integrator A output 16 road V
aisignal is corresponding to be connected with 16 analog input end S0-S15 of 16 tunnels analogy multiplexer A, and 16 tunnels analogy multiplexer A are exported through light-coupled isolation Hou tetra-tunnel control signal C by control logic circuit CPLD
a0～C
a3control it and switch, the voltage signal V of the output terminal output serial of 16 tunnels analogy multiplexer A
oUTA, V
oUTAbe connected the differential voltage signal of difference output driving device circuit output and the analog differential input end AI of data collecting card with difference output driving circuit
0-1connect; Integrator B exports 16 road V
bisignal is corresponding to be connected with 16 analog input end S0-S15 of 16 tunnels analogy multiplexer B, and 16 tunnels analogy multiplexer B are exported through light-coupled isolation Hou tetra-tunnel control signal C by control logic circuit CPLD
b0～C
b3control it and switch, the voltage signal V of the output terminal output serial of 16 tunnels analogy multiplexer B
oUTB, V
oUTBbe connected the differential voltage signal of difference output driving device output and the analog differential input end AI of data collecting card with difference output driving device
2-3connect.
Described control logic circuit realization is communicated by letter with data collecting card, and controls speed-sensitive switch S
a/Bithe switch S of releasing in sum-product intergrator
hA/Bibreak-make and the switching of multiplexer.
Digital output D0, D1, D2, the D3 of described data collecting card are connected with four I/O mouths of control logic circuit CPLD respectively, corresponding transmission B passage work trigger pip Trig-B
in, A channel work trigger pip Trig-A
in, data acquisition enables trigger pip DAQ-trig, data acquisition clock signal DAQ-sclk.
The described integrator with drainage function is made up of amplifier OP, adjustable integrating capacitor and the switch of releasing, the output terminal of speed-sensitive switch is connected with the inverting input of amplifier OP, the positive input end grounding of amplifier OP, the inverting input of amplifier OP is connected with adjustable integrating capacitor, the other end of electric capacity is connected to the output terminal of amplifier OP, the switch of releasing in parallel in adjustable integrating capacitor, the output terminal output voltage signal of amplifier OP; Described speed-sensitive switch S
aioutput terminal be connected with the inverting input of amplifier OP, the positive input end grounding of amplifier OP, the inverting input of amplifier OP and adjustable integrating capacitor C
aiconnect capacitor C
aithe other end be connected to the output terminal of amplifier OP, adjustable integrating capacitor C
aithe upper switch S of releasing in parallel
hAi, the output terminal output voltage signal V of amplifier OP
ai; Speed-sensitive switch S
bioutput terminal be connected with the inverting input of amplifier OP, the positive input end grounding of amplifier OP, the inverting input of amplifier OP and adjustable integrating capacitor C
biconnect capacitor C
bithe other end be connected to the output terminal of amplifier OP, adjustable integrating capacitor C
bithe upper switch S of releasing in parallel
hBi, the output terminal output voltage signal V of amplifier OP
bi; The switch S of releasing
hAiwith the switch S of releasing
hBiwhether it releases to export control signal control after light-coupled isolation by CPLD, the switch S of releasing
hAiwith the switch S of releasing
hBiactuation time be all less than 20ns.
Described control logic circuit CPLD output simulation multiplexer A Si road control signal CTRL-A is to optical coupling isolator, and output simulation multiplexer B Si road control signal CTRL-B, to optical coupling isolator, exports No. 16 speed-sensitive switch S
aicontrol signal to optical coupling isolator, output No. 16 speed-sensitive switch S
bicontrol signal to optical coupling isolator, the output 16 tunnels switch S of releasing
hAicontrol signal to optical coupling isolator, the output 16 tunnels switch S of releasing
hBicontrol signal to optical coupling isolator.Due to all S
aisignal is synchronous, can also adopt fan-out circuit to obtain the S of corresponding 16 passages
aisignal is to reduce the use of control logic circuit CPLD device I/O mouth, and this kind of method is applicable to obtain all S too
bi, S
hAiand S
hBisignal.
The invention has the beneficial effects as follows: described a kind of controllable type hyperchannel charger-reader, its electric charge for beam monitoring itemize ionization chamber (electric current) signal is read, range is controlled, integration duration is controlled, working method (read continuously/intermittently read) is controlled, use that can be flexible and changeable; Every passage contains two-way (A and B) integrator, and they can time-sharing work, has improved signal treatment effeciency; Adopt multiplex electronics, realize train of signal line output, can effectively reduce complexity and the manufacturing cost of data acquisition and processing (DAP) system, improve the accuracy of heavy-ion cancer therapy system.This circuit precision is high, good linearity, dirigibility are strong, simple in structure.
Brief description of the drawings
Fig. 1 is theory diagram of the present invention;
Fig. 2 is circuit theory schematic diagram of the present invention;
Fig. 3 is working timing figure of the present invention.
Embodiment
Below in conjunction with accompanying drawing, principle of the present invention and feature are described, example, only for explaining the present invention, is not intended to limit scope of the present invention.
As shown in Figures 1 to 3, described a kind of controllable type hyperchannel charger-reader, feature is to comprise connected successively speed-sensitive switch, integrator, multiplexer, control logic circuit, difference output driving circuit and data collecting card with drainage function, described speed-sensitive switch comprises 16 groups of speed-sensitive switches that Yu Shi six road input signals are connected, and every group of speed-sensitive switch is by the two-way speed-sensitive switch S being connected side by side
aiand S
bi, two-way speed-sensitive switch S
aiand S
bibe connected with integrator A sum-product intergrator B respectively; The output terminal of integrator A is connected to multiplexer A, and the output terminal of integrator B is connected to multiplexer B; The output terminal of multiplexer A and multiplexer B is connected respectively to difference output driving circuit, and the output terminal of difference output driving circuit is connected to the analog differential input end of data collecting card; Data collecting card is connected with control logic circuit and carries out two-way communication, and control logic circuit is connected with speed-sensitive switch.
The digital output end of described data collecting card sends external trigger signal to control logic circuit, and control logic circuit transmission collection clock signal and trigger collection signal are to the digital input end of data collecting card; The control signal control multiplexer A of described control logic circuit after by light-coupled isolation and channel selecting and the switching of multiplexer B; The disconnection of the control signal control speed-sensitive switch of control logic circuit after by light-coupled isolation is with closed.
Described integrator A output 16 road V
aisignal is corresponding to be connected with 16 analog input end S0-S15 of 16 tunnels analogy multiplexer A, and 16 tunnels analogy multiplexer A are exported through light-coupled isolation Hou tetra-tunnel control signal C by control logic circuit CPLD
a0～C
a3control it and switch, the voltage signal V of the output terminal output serial of 16 tunnels analogy multiplexer A
oUTA, V
oUTAbe connected the differential voltage signal of difference output driving device circuit output and the analog differential input end AI of data collecting card with difference output driving circuit
0-1connect; Integrator B exports 16 road V
bisignal is corresponding to be connected with 16 analog input end S0-S15 of 16 tunnels analogy multiplexer B, and 16 tunnels analogy multiplexer B are exported through light-coupled isolation Hou tetra-tunnel control signal C by control logic circuit CPLD
b0～C
b3control it and switch, the voltage signal V of the output terminal output serial of 16 tunnels analogy multiplexer B
oUTB, V
oUTBbe connected the differential voltage signal of difference output driving device output and the analog differential input end AI of data collecting card with difference output driving device
2-3connect.
Described control logic circuit realization is communicated by letter with data collecting card, and controls speed-sensitive switch S
a/Bithe switch S of releasing in sum-product intergrator
hA/Bibreak-make and the switching of multiplexer.
Digital output D0, D1, D2, the D3 of described data collecting card are connected with four I/O mouths of control logic circuit CPLD respectively, corresponding transmission B passage work trigger pip Trig-B
in, A channel work trigger pip Trig-A
in, data acquisition enables trigger pip DAQ-trig, data acquisition clock signal DAQ-sclk.
The described integrator with drainage function is made up of amplifier OP, adjustable integrating capacitor and the switch of releasing, the output terminal of speed-sensitive switch is connected with the inverting input of amplifier OP, the positive input end grounding of amplifier OP, the inverting input of amplifier OP is connected with adjustable integrating capacitor, the other end of electric capacity is connected to the output terminal of amplifier OP, the switch of releasing in parallel in adjustable integrating capacitor, the output terminal output voltage signal of amplifier OP; Described speed-sensitive switch S
aioutput terminal be connected with the inverting input of amplifier OP, the positive input end grounding of amplifier OP, the inverting input of amplifier OP and adjustable integrating capacitor C
aiconnect capacitor C
aithe other end be connected to the output terminal of amplifier OP, adjustable integrating capacitor C
aithe upper switch S of releasing in parallel
hAi, the output terminal output voltage signal V of amplifier OP
ai; Speed-sensitive switch S
bioutput terminal be connected with the inverting input of amplifier OP, the positive input end grounding of amplifier OP, the inverting input of amplifier OP and adjustable integrating capacitor C
biconnect capacitor C
bithe other end be connected to the output terminal of amplifier OP, adjustable integrating capacitor C
bithe upper switch S of releasing in parallel
hBi, the output terminal output voltage signal V of amplifier OP
bi; The switch S of releasing
hAiwith the switch S of releasing
hBiwhether it releases to export control signal control after light-coupled isolation by CPLD, the switch S of releasing
hAiwith the switch S of releasing
hBiactuation time be all less than 20ns.
Described control logic circuit CPLD output simulation multiplexer A Si road control signal CTRL-A is to optical coupling isolator, and output simulation multiplexer B Si road control signal CTRL-B, to optical coupling isolator, exports No. 16 speed-sensitive switch S
aicontrol signal to optical coupling isolator, output No. 16 speed-sensitive switch S
bicontrol signal to optical coupling isolator, the output 16 tunnels switch S of releasing
hAicontrol signal to optical coupling isolator, the output 16 tunnels switch S of releasing
hBicontrol signal to optical coupling isolator.Due to all S
aisignal is synchronous, can also adopt fan-out circuit to obtain the S of corresponding 16 passages
aisignal is to reduce the use of control logic circuit CPLD device I/O mouth, and this kind of method is applicable to obtain all S too
bi, S
hAiand S
hBisignal.
Described a kind of controllable type hyperchannel charger-reader, when its work, data collecting card output A series of channel work trigger pip Trig-A
inwith B series of channel work trigger pip Trig-B
in, work as Trig-A
infor high level and Trig-B
induring for low level, represent that electric charge (electric current) signal of ensuing time period will be read by A series of channel, 16 speed-sensitive switch S of A series of channel
aiclosure, the switch S of releasing in 16 integrator A
hAidisconnect 16 speed-sensitive switch S of B series of channel
bidisconnect, integrator A starts working, by electric charge (electric current) at integrating capacitor C
aion convert voltage signal to.Next may occur three kinds of states, the first state is Trig-A
infor high level and Trig-B
inbecome high level, the second state is Trig-A
inbecome low level and Trig-B
inalso, while being low level, when this two states occurs, represent that electric charge (electric current) signal of ensuing time period does not need to read, now 16 of A series of channel speed-sensitive switch S
aidisconnect the switch S of releasing in 16 integrator A
hAicontinue to disconnect 16 speed-sensitive switch S of B series of channel
biclosure, the switch S of releasing in 16 integrator B
hBicontinue closed, data acquisition enables trigger pip DAQ-trig and becomes the corresponding control 16 road simulation multiplexers switchings of high level control logic circuit CPLD, export 16 serial voltage signals, again through 16 serial differential voltage signals of difference output driving device output, the clock signal of data acquisition simultaneously DAQ-sclk sends 16 differential voltage signals in the corresponding A of collection of 16 acquisition pulse signals series of channel, when all completing the collection of A series of channel data, data acquisition enables trigger pip DAQ-trig and data acquisition clock signal DAQ-sclk all becomes low level, 16 speed-sensitive switch S of A series of channel
aidisconnect the switch S of releasing in 16 integrator A
hAiclosed, the third state is Trig-A
inbecome low level and Trig-B
inwhile becoming high level, represent that electric charge (electric current) signal of ensuing time period will be read by B series of channel, now 16 of A series of channel speed-sensitive switch S
aidisconnect the switch S of releasing in 16 integrator A
hAidisconnect 16 speed-sensitive switch S of B series of channel
biclosure, the switch S of releasing in 16 integrator B
hBidisconnect, integrator B starts working, by electric charge (electric current) at integrating capacitor C
bion convert voltage signal to, carry out the collection of the A series of channel data described in the first situation and the second situation simultaneously.There is the third state in the first state and the second state carry out time, the data acquisition of A series of channel is proceeded according to previous status again, and electric charge (electric current) signal starts to be read by B series of channel.The above has been realized A series of channel and has read into the transfer process that B series of channel is read, and B series of channel is read and is transformed into process that A series of channel reads and the above is similar.Thereby the work that A series of channel and B series of channel are gone round and begun again according to this workflow has realized reading of hyperchannel electric charge (electric current) signal.
Described a kind of controllable type hyperchannel charger-reader, can free of discontinuities read hyperchannel electric charge (electric current) signal, also can intermittently read hyperchannel electric charge (electric current) signal; Can be reading of 30fC～50uC positive and negative charge signal by regulating the integrating capacitor size of integrator to realize input range; Integration duration is by external control, but is limited to data acquisition time, if select the data collecting card of each passage 40MS/s sampling rate, integration duration must not be less than 500ns, and accessible like this example rate is up to 2*10
6counts/s; Output signal range is-5V～+ 5V; Can doubly combine and realize hyperchannel electric charge (electric current) and read by Zhe16 road element circuit arbitrary integer; Circuit working is stable, antijamming capability is strong, has realized reading of hyperchannel, wide dynamic range positive and negative charge (electric current).This invention can also be widely used in the front-end processing of other electric charge (electric current) signal of nuclear physics experiment and accelerator system.Can examine the positive/negative electric charge of hyperchannel (electric current) signal that monitoring itemize ionization chamber is exported by omnidistance unremitting reading beam, and have great dynamic range, good linearity, intelligent and can flexible operating etc. feature, thereby provide simple and reliable monitoring method and means for the line distributed intelligence in heavy-ion cancer therapy.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any amendment of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (7)
1. a controllable type hyperchannel charger-reader, it is characterized in that comprising connected successively speed-sensitive switch, integrator, multiplexer, control logic circuit, difference output driving circuit and data collecting card with drainage function, described speed-sensitive switch comprises 16 groups of speed-sensitive switches that Yu Shi six road input signals are connected, and every group of speed-sensitive switch is by the two-way speed-sensitive switch S being connected side by side
aiand S
bi, two-way speed-sensitive switch S
aiand S
bibe connected with integrator A sum-product intergrator B respectively; The output terminal of integrator A is connected to multiplexer A, and the output terminal of integrator B is connected to multiplexer B; The output terminal of multiplexer A and multiplexer B is connected respectively to difference output driving circuit, and the output terminal of difference output driving circuit is connected to the analog differential input end of data collecting card; Data collecting card is connected with control logic circuit and carries out two-way communication, and control logic circuit is connected with speed-sensitive switch.
2. a kind of controllable type hyperchannel charger-reader according to claim 1, it is characterized in that: the digital output end of described data collecting card sends external trigger signal to control logic circuit, control logic circuit transmission collection clock signal and trigger collection signal are to the digital input end of data collecting card; The control signal control multiplexer A of described control logic circuit after by light-coupled isolation and channel selecting and the switching of multiplexer B; The disconnection of the control signal control speed-sensitive switch of control logic circuit after by light-coupled isolation is with closed.
3. a kind of controllable type hyperchannel charger-reader according to claim 1, is characterized in that: described integrator A output 16 road V
aisignal is corresponding to be connected with 16 analog input end S0-S15 of 16 tunnels analogy multiplexer A, and 16 tunnels analogy multiplexer A are exported through light-coupled isolation Hou tetra-tunnel control signal C by control logic circuit CPLD
a0～C
a3control it and switch, the voltage signal V of the output terminal output serial of 16 tunnels analogy multiplexer A
oUTA, V
oUTAbe connected the differential voltage signal of difference output driving device circuit output and the analog differential input end AI of data collecting card with difference output driving circuit
0-1connect; Integrator B exports 16 road V
bisignal is corresponding to be connected with 16 analog input end S0-S15 of 16 tunnels analogy multiplexer B, and 16 tunnels analogy multiplexer B are exported through light-coupled isolation Hou tetra-tunnel control signal C by control logic circuit CPLD
b0～C
b3control it and switch, the voltage signal V of the output terminal output serial of 16 tunnels analogy multiplexer B
oUTB, V
oUTBbe connected the differential voltage signal of difference output driving device output and the analog differential input end AI of data collecting card with difference output driving device
2-3connect.
4. a kind of controllable type hyperchannel charger-reader according to claim 1 and 2, is characterized in that: described control logic circuit realization is communicated by letter with data collecting card, and controls speed-sensitive switch S
a/Bithe switch S of releasing in sum-product intergrator
hA/Bibreak-make and the switching of multiplexer.
5. according to a kind of controllable type hyperchannel charger-reader described in claim 1 or 2 or 3, it is characterized in that: digital output D0, D1, D2, the D3 of described data collecting card are connected with four I/O mouths of control logic circuit CPLD respectively corresponding transmission B passage work trigger pip Trig-B
in, A channel work trigger pip Trig-A
in, data acquisition enables trigger pip DAQ-trig, data acquisition clock signal DAQ-sclk.
6. a kind of controllable type hyperchannel charger-reader according to claim 1, it is characterized in that: the described integrator with drainage function is made up of amplifier OP, adjustable integrating capacitor and the switch of releasing, the output terminal of speed-sensitive switch is connected with the inverting input of amplifier OP, the positive input end grounding of amplifier OP, the inverting input of amplifier OP is connected with adjustable integrating capacitor, the other end of electric capacity is connected to the output terminal of amplifier OP, the switch of releasing in parallel in adjustable integrating capacitor, the output terminal output voltage signal of amplifier OP; Described speed-sensitive switch S
aioutput terminal be connected with the inverting input of amplifier OP, the positive input end grounding of amplifier OP, the inverting input of amplifier OP and adjustable integrating capacitor C
aiconnect capacitor C
aithe other end be connected to the output terminal of amplifier OP, adjustable integrating capacitor C
aithe upper switch S of releasing in parallel
hAi, the output terminal output voltage signal V of amplifier OP
ai; Speed-sensitive switch S
bioutput terminal be connected with the inverting input of amplifier OP, the positive input end grounding of amplifier OP, the inverting input of amplifier OP and adjustable integrating capacitor C
biconnect capacitor C
bithe other end be connected to the output terminal of amplifier OP, adjustable integrating capacitor C
bithe upper switch S of releasing in parallel
hBi, the output terminal output voltage signal V of amplifier OP
bi; The switch S of releasing
hAiwith the switch S of releasing
hBiwhether it releases to export control signal control after light-coupled isolation by CPLD, the switch S of releasing
hAiwith the switch S of releasing
hBiactuation time be all less than 20ns.
7. a kind of controllable type hyperchannel charger-reader according to claim 5, it is characterized in that: described control logic circuit CPLD output simulation multiplexer A Si road control signal CTRL-A is to optical coupling isolator, output simulation multiplexer B Si road control signal CTRL-B, to optical coupling isolator, exports No. 16 speed-sensitive switch S
aicontrol signal to optical coupling isolator, output No. 16 speed-sensitive switch S
bicontrol signal to optical coupling isolator, the output 16 tunnels switch S of releasing
hAicontrol signal to optical coupling isolator, the output 16 tunnels switch S of releasing
hBicontrol signal to optical coupling isolator.Due to all S
aisignal is synchronous, can also adopt fan-out circuit to obtain the S of corresponding 16 passages
aisignal is to reduce the use of control logic circuit CPLD device I/O mouth, and this kind of method is applicable to obtain all S too
bi, S
hAiand S
hBisignal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410199336.5A CN103969676B (en) | 2014-05-11 | A kind of controllable type multichannel charger-reader |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410199336.5A CN103969676B (en) | 2014-05-11 | A kind of controllable type multichannel charger-reader |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103969676A true CN103969676A (en) | 2014-08-06 |
| CN103969676B CN103969676B (en) | 2016-11-30 |
Family
ID=
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105067126A (en) * | 2015-08-31 | 2015-11-18 | 西安赛恒电子科技有限公司 | Infrared focal plane analog front-end circuit |
| CN109709595A (en) * | 2019-01-25 | 2019-05-03 | 成都理工大学 | Multi-parameter time synchronization spectrometer data-acquisition system and its application |
| CN111817717A (en) * | 2020-06-12 | 2020-10-23 | 中国科学院上海微系统与信息技术研究所 | Multichannel data reading circuit |
| CN115656027A (en) * | 2022-11-01 | 2023-01-31 | 哈尔滨工业大学 | Multi-functional wireless node is used in monitoring of steel-concrete structure corruption electrochemistry |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002094379A (en) * | 2000-09-19 | 2002-03-29 | Sharp Corp | Multi-channel analog to digital converter, system and x-ray sensor module |
| CN101533099A (en) * | 2009-03-22 | 2009-09-16 | 中国科学院近代物理研究所 | Charge frequency converter |
| TW201340593A (en) * | 2012-03-27 | 2013-10-01 | Academia Sinica | Accelerator beam speed monitor and its read out device |
| CN203825205U (en) * | 2014-05-11 | 2014-09-10 | 中国科学院近代物理研究所 | Controllable multichannel charge reading device |
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002094379A (en) * | 2000-09-19 | 2002-03-29 | Sharp Corp | Multi-channel analog to digital converter, system and x-ray sensor module |
| CN101533099A (en) * | 2009-03-22 | 2009-09-16 | 中国科学院近代物理研究所 | Charge frequency converter |
| TW201340593A (en) * | 2012-03-27 | 2013-10-01 | Academia Sinica | Accelerator beam speed monitor and its read out device |
| CN203825205U (en) * | 2014-05-11 | 2014-09-10 | 中国科学院近代物理研究所 | Controllable multichannel charge reading device |
Non-Patent Citations (3)
| Title |
|---|
| ZHIGUO XU等: "A newmulti-strip ionization chamber used as online beam monitor for heavy ion therapy", 《NUCLEARINSTRUMENTSANDMETHODSIN》, 21 November 2013 (2013-11-21), pages 895 - 899, XP028756015, DOI: doi:10.1016/j.nima.2013.08.069 * |
| 佘乾顺等: "束流均匀性测量前端读出电子学电路的设计", 《核电子学与探测技术》, 30 June 2011 (2011-06-30) * |
| 苏弘等: "一种束流强度监测电路设计", 《核电子学与探测技术》, 30 September 2009 (2009-09-30) * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105067126A (en) * | 2015-08-31 | 2015-11-18 | 西安赛恒电子科技有限公司 | Infrared focal plane analog front-end circuit |
| CN105067126B (en) * | 2015-08-31 | 2019-02-01 | 西安赛恒电子科技有限公司 | Infrared focus plane analog front circuit |
| CN109709595A (en) * | 2019-01-25 | 2019-05-03 | 成都理工大学 | Multi-parameter time synchronization spectrometer data-acquisition system and its application |
| CN111817717A (en) * | 2020-06-12 | 2020-10-23 | 中国科学院上海微系统与信息技术研究所 | Multichannel data reading circuit |
| CN111817717B (en) * | 2020-06-12 | 2023-11-28 | 中国科学院上海微系统与信息技术研究所 | Multichannel data reading circuit |
| CN115656027A (en) * | 2022-11-01 | 2023-01-31 | 哈尔滨工业大学 | Multi-functional wireless node is used in monitoring of steel-concrete structure corruption electrochemistry |
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