CN105932980A - Leap-frogging type multi-loop feedback switch current filter - Google Patents

Abstract

An embodiment of the present invention provides a jump-frog multi-loop feedback switch current filter, including: including: sequentially cascaded current mirror circuits, n-1 first switch current bilinear integrators and 1 second switch A current bilinear integrator; n is an integer greater than 1; the current mirror circuit is used to perform equivalent copying and inversion of external input signals to generate positive output signals and negative output signals; the second The switch current bilinear integrator is used to integrate the current. The input terminal includes: a positive input terminal and a negative input terminal; the positive input terminal and the first switch current bilinear integrator with the serial number n-1 The positive output terminal of the device is connected, and the negative input terminal is connected with the negative output terminal of the first switching current bilinear integrator whose serial number is n-1; the output terminal includes: positive feedback output terminal, negative feedback output and external output. The frequency response characteristic of the present invention is better.

Description

Leapfrog multi-loop feedback switching current filter

technical field

The invention relates to the field of analog integrated circuits, in particular to a leapfrog multi-loop feedback switch current filter.

Background technique

Analog filters can perform frequency-selective operations on input signals and play an important role in fields such as automatic control, aerospace, and instrumentation.

Early analog filters were mainly LC filters, which had the disadvantages of large size and heavy weight. With the rapid development of microelectronics technology, various non-inductive analog integrated filter implementation technologies have come out one after another, mainly focusing on continuous-time analog filters. Although it has advantages in terms of micro-volume and low-power implementation, the frequency response characteristics of continuous-time analog filters are determined by the absolute values of characteristic parameters, so the integration accuracy is poor, and complex on-chip tuning circuits are required to accurately achieve preset time constants . Switched capacitor filter technology can overcome the above shortcomings, and has been widely used in the industry. Switched capacitor filters are sampled data analog techniques whose time constant depends on the ratio of capacitors, can be precisely integrated, and the center frequency can be tuned by a clock. However, switched capacitor technology requires floating capacitors, is incompatible with standard CMOS digital processes, and is expensive to manufacture. In this context, switching current technology came into being. The time constant of the switching current filter depends on the ratio of the channel width to length of the transistor. It can be precisely integrated and does not require linear floating capacitors. It is compatible with the standard VLSI CMOS digital process and is a cutting-edge research in the field of analog integrated filter design today. direction.

At present, the realization structures of switching current filters mainly include cascading, LC trapezoidal simulation structure and following leading stage feedback structure. Among them, the switch current cascade structure has the disadvantages of high circuit sensitivity; although the LC trapezoidal simulation structure can reduce the circuit sensitivity, the implementation structure is complicated, which is not conducive to the rapid and accurate circuit design of relevant engineers; Long, poor frequency response characteristics and other shortcomings.

Contents of the invention

The embodiments of the present invention provide a leapfrog multi-loop feedback switched current filter, which can shorten the length of the filter feedback path, and has the advantages of simple structure and low circuit sensitivity.

In order to achieve the above object, the present invention adopts the following technical solutions.

A leapfrog multi-loop feedback switching current filter, comprising:

A current mirror circuit cascaded in sequence, n-1 first switched current bilinear integrators and a second switched current bilinear integrator; n is an integer greater than 1;

The current mirror circuit is used to perform equivalent copy and reverse on the external input signal respectively to generate a forward output signal and a negative output signal; the input end is connected to the external input signal, and the serial number of the forward output signal is 1 The positive input terminal of the first switched current bilinear integrator is connected, and the negative output signal is connected with the negative input terminal of the first switched current bilinear integrator whose serial number is 1;

The first switched current bilinear integrator is used to integrate the current; the input terminal includes: a positive input terminal and a negative input terminal; the output terminal of the first switched current bilinear integrator includes a positive input terminal. output terminal, negative output terminal, positive feedback output terminal, negative feedback output terminal and external output terminal; wherein, the positive direction of the first switching current bilinear integrator whose serial number is 1 to n-2 The output ends are respectively output to the positive input ends of the next cascaded first switched current bilinear integrator, and the negative outputs of the first switched current bilinear integrators whose serial numbers are 1 to n-2 terminals are respectively output to the negative input terminals of the next cascaded first switched current bilinear integrator; the positive output terminal of the first switched current bilinear integrator whose sequence number is n-1 is output to The positive input terminal of the second switched current bilinear integrator, the negative output terminal of the first switched current bilinear integrator with the serial number n-1 outputs to the cascaded second switched current bilinear integrator The negative input terminal of the linear integrator; the positive feedback output terminal of the first switch current bilinear integrator whose serial number is 2 to n-1 respectively outputs to the last first switch current bilinear integrator in the cascade The negative input terminal of the linear integrator, and the negative feedback output terminals of the first switch current bilinear integrator whose serial number is 2 to n-1 respectively output to the cascaded last first switch current bilinear The positive input terminal of the linear integrator, the positive feedback output terminal of the first switched current bilinear integrator whose sequence number is 1 outputs to the negative direction of the first switched current bilinear integrator whose sequence number is 1 The input terminal, the negative feedback output terminal of the first switched current bilinear integrator with serial number 1 is output to the positive input terminal of the first switched current bilinear integrator with serial number 1;

The second switch current bilinear integrator is used to integrate the current. The input terminals include: a positive input terminal and a negative input terminal; the positive input terminal and the first switch current with the serial number n-1 The positive output terminal of the bilinear integrator is connected, and the negative input terminal is connected to the negative output terminal of the first switching current bilinear integrator whose serial number is n-1; the output terminal includes: a positive feedback output terminal , the negative feedback output terminal and the external output terminal; wherein, the positive feedback output terminal outputs to the negative input terminal of the first switching current bilinear integrator whose serial number is n-1, and the negative feedback output terminal outputs to the serial number of the positive input terminal of the first switched current bilinear integrator of n-1;

The n-1 external output terminals of the first switched current bilinear integrator are connected to the external output terminals of the second switched current bilinear integrator, and they are used as the output of the switched current filter together.

A leapfrog multi-loop feedback switching current filter, comprising:

A current mirror circuit cascaded in sequence, n-1 first switched current bilinear integrators and a second switched current bilinear integrator; n is an integer greater than 1;

The current mirror circuit is used to respectively copy and reverse the external input signal to generate n positive output signals and n negative output signals; the input terminal is connected to the external input signal; the first n-1 positive output signals The negative output signals are respectively connected to the positive input terminals of the n-1 first switching current bilinear integrators corresponding to the sequence number, and the first n-1 negative output signals are respectively connected to the n-1 first switch current bilinear integrators corresponding to the sequence number. The negative input terminal of the switch current bilinear integrator is connected; the positive output signal of the nth one is connected with the positive input terminal of the second switch current bilinear integrator, and the negative output signal of the nth one is The signal is connected to the negative input terminal of the second switched current bilinear integrator;

The first switched current bilinear integrator is used to integrate the current; the input terminal includes: a positive input terminal and a negative input terminal; the output terminal of the first switched current bilinear integrator includes a positive input terminal. output terminal, negative output terminal, positive feedback output terminal, and negative feedback output terminal; wherein, the positive output terminals of the first switching current bilinear integrator whose sequence numbers are 1 to n-2 respectively output To the positive input terminal of the next first switched current bilinear integrator in the cascade, the negative output terminals of the first switched current bilinear integrator whose sequence numbers are 1 to n-2 are respectively output to The negative input terminal of the next first switch current bilinear integrator in the cascade; the positive output terminal of the first switch current bilinear integrator whose sequence number is n-1 is output to the second switch current The positive input terminal of the bilinear integrator, the negative output terminal of the first switched current bilinear integrator whose serial number is n-1 is output to the cascaded second switched current bilinear integrator Negative input terminals; the positive feedback output terminals of the first switched current bilinear integrators whose serial numbers are 2 to n-1 are respectively output to the cascaded last first switched current bilinear integrators. Negative input terminals, the negative feedback output terminals of the first switched current bilinear integrators whose serial numbers are 2 to n-1 respectively output to the cascaded last first switched current bilinear integrators The positive input terminal, the positive feedback output terminal of the first switched current bilinear integrator with the serial number 1 is output to the negative input terminal of the first switched current bilinear integrator with the serial number 1, the serial number The negative feedback output terminal of the first switched current bilinear integrator whose serial number is 1 is output to the positive input terminal of the first switched current bilinear integrator whose serial number is 1;

The second switch current bilinear integrator is used to integrate the current. The input terminals include: a positive input terminal and a negative input terminal; the positive input terminal and the first switch current with the serial number n-1 The positive output terminal of the bilinear integrator is connected, and the negative input terminal is connected to the negative output terminal of the first switching current bilinear integrator whose serial number is n-1; the output terminal includes: a positive feedback output terminal , the negative feedback output terminal and the external output terminal; wherein, the positive feedback output terminal outputs to the negative input terminal of the first switching current bilinear integrator whose serial number is n-1, and the negative feedback output terminal outputs to the serial number of The positive input terminal of the n-1 first switched current bilinear integrator, and the external output terminal is the output of the switched current filter.

It can be seen from the technical solutions provided by the above-mentioned embodiments of the present invention that in the embodiments of the present invention, the switched current filter is composed of cascaded switched current integrators, the circuit structure is simple, and through the introduction of the jump-frog negative feedback branch, The length of the feedback path of the switch current filter can be effectively shortened, and the circuit sensitivity of the switch current filter can be reduced.

Additional aspects and advantages of the invention will be set forth in part in the description which follows, and will become apparent from the description, or may be learned by practice of the invention.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort.

Fig. 1 is the realization circuit schematic diagram of the switching current filter of the present invention;

2-1 is a schematic diagram of a current mirror circuit of a switched current filter according to the present invention;

Fig. 2-2 is the simplified schematic diagram of circuit symbols of the current mirror circuit of the switching current filter of the present invention;

Fig. 3-1 is the implementation circuit diagram of the first switching current bilinear integrator of the switching current filter of the present invention;

Fig. 3-2 is a schematic diagram of simplified circuit symbols of the first switched current bilinear integrator of the switched current filter according to the present invention;

Fig. 4-1 is the realization circuit schematic diagram of the second switched current bilinear integrator of the switched current filter of the present invention;

Fig. 4-2 is a schematic diagram of simplified circuit symbols of the second switched current bilinear integrator of the switched current filter according to the present invention;

Fig. 5 is a schematic diagram of clock waveforms of the switched current filter according to the present invention.

Fig. 6 is the realization circuit schematic diagram of the switching current filter of the present invention;

7-1 is a schematic diagram of a current mirror circuit of a switched current filter according to the present invention;

Fig. 7-2 is a schematic diagram of simplified circuit symbols of the current mirror circuit of the switched current filter according to the present invention;

Fig. 8-1 is the realization circuit diagram of the first switched current bilinear integrator of the switched current filter according to the present invention;

Fig. 8-2 is a schematic diagram of simplified circuit symbols of the first switched current bilinear integrator of the switched current filter according to the present invention;

Fig. 9-1 is a schematic circuit diagram of a second switched current bilinear integrator of the switched current filter according to the present invention;

Fig. 9-2 is a schematic diagram of simplified circuit symbols of the second switched current bilinear integrator of the switched current filter according to the present invention;

Fig. 10 is a schematic diagram of clock waveforms of the switched current filter according to the present invention.

detailed description

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

Fig. 1 is the realization circuit schematic diagram of the switching current filter of the present invention; Fig. 2-1 is the current mirror circuit schematic diagram of the switching current filter of the present invention; Fig. 2-2 is the switching current filter of the present invention The schematic diagram of the simplified circuit symbol of the current mirror circuit of filter; Fig. 3-1 is the realization circuit schematic diagram of the first switched current bilinear integrator of the switched current filter of the present invention; Fig. 3-2 is described in the present invention The simplified circuit symbol schematic diagram of the first switched current bilinear integrator of the switched current filter; Fig. 4-1 is the realization circuit schematic diagram of the second switched current bilinear integrator of the switched current filter of the present invention; Fig. 4-2 is a schematic diagram of simplified circuit symbols of the second switched current bilinear integrator of the switched current filter of the present invention; FIG. 5 is a schematic diagram of clock waveforms of the switched current filter of the present invention. It will be described below in conjunction with FIGS. 1-5 .

As shown in Figure 1, it is a leapfrog multi-loop feedback switch current filter according to the present invention, including:

A current mirror circuit cascaded in sequence, n-1 first switched current bilinear integrators and a second switched current bilinear integrator; n is an integer greater than 1;

The current mirror circuit is used to perform equivalent copy and reverse on the external input signal respectively to generate a forward output signal and a negative output signal; the input end is connected to the external input signal, and the serial number of the forward output signal is 1 The positive input terminal of the first switched current bilinear integrator is connected, and the negative output signal is connected with the negative input terminal of the first switched current bilinear integrator whose serial number is 1;

The first switched current bilinear integrator is used to integrate the current; the input terminal includes: a positive input terminal and a negative input terminal; the output terminal of the first switched current bilinear integrator includes a positive input terminal. output terminal, negative output terminal, positive feedback output terminal, negative feedback output terminal and external output terminal; wherein, the positive direction of the first switching current bilinear integrator whose serial number is 1 to n-2 The output ends are respectively output to the positive input ends of the next cascaded first switched current bilinear integrator, and the negative outputs of the first switched current bilinear integrators whose serial numbers are 1 to n-2 terminals are respectively output to the negative input terminals of the next cascaded first switched current bilinear integrator; the positive output terminal of the first switched current bilinear integrator whose sequence number is n-1 is output to The positive input terminal of the second switched current bilinear integrator, the negative output terminal of the first switched current bilinear integrator with the serial number n-1 outputs to the cascaded second switched current bilinear integrator The negative input terminal of the linear integrator; the positive feedback output terminal of the first switch current bilinear integrator whose serial number is 2 to n-1 respectively outputs to the last first switch current bilinear integrator in the cascade The negative input terminal of the linear integrator, and the negative feedback output terminals of the first switch current bilinear integrator whose serial number is 2 to n-1 respectively output to the cascaded last first switch current bilinear The positive input terminal of the linear integrator, the positive feedback output terminal of the first switched current bilinear integrator whose sequence number is 1 outputs to the negative direction of the first switched current bilinear integrator whose sequence number is 1 The input terminal, the negative feedback output terminal of the first switched current bilinear integrator with serial number 1 is output to the positive input terminal of the first switched current bilinear integrator with serial number 1;

The second switch current bilinear integrator is used to integrate the current. The input terminals include: a positive input terminal and a negative input terminal; the positive input terminal and the first switch current with the serial number n-1 The positive output terminal of the bilinear integrator is connected, and the negative input terminal is connected to the negative output terminal of the first switching current bilinear integrator whose serial number is n-1; the output terminal includes: a positive feedback output terminal , the negative feedback output terminal and the external output terminal; wherein, the positive feedback output terminal outputs to the negative input terminal of the first switching current bilinear integrator whose serial number is n-1, and the negative feedback output terminal outputs to the serial number of the positive input terminal of the first switched current bilinear integrator of n-1;

The n-1 external output terminals of the first switched current bilinear integrator are connected to the external output terminals of the second switched current bilinear integrator, and they are used as the output of the switched current filter together.

As shown in Figure 2-1 and Figure 2-2, the current mirror circuit includes:

The first MOS transistor M ₁ , the second MOS transistor M ₂ , the third MOS transistor M ₃ , the fourth MOS transistor M ₄ , the fifth MOS transistor M ₅ , the first input terminal I _in , the first negative output terminal i _a0 ^- and the first positive output terminal i _a0 ⁺ ;

The gate of the second MOS transistor _M2 is respectively connected to the gate and drain of the _first MOS transistor M1, and connected to the first input terminal _Iin ; the drain of the _second MOS transistor M2 is connected to the first negative output terminal i _a0 ⁻ ; the gate of the second MOS transistor _M2 is connected to the gate of the _third MOS transistor M3;

The drain of the _third MOS transistor M3 is connected to the gate and drain of the _fourth MOS transistor M4; the gate of the _fourth MOS transistor M4 is connected to the gate of the _fifth MOS transistor M5 ;

The drain of the _fifth MOS transistor M5 is connected to the first positive output terminal i _a0 ⁺ ;

The drains of the first MOS transistor M ₁ , the second MOS transistor M ₂ , the third MOS transistor M ₃ , the fourth MOS transistor M ₄ , and the fifth MOS transistor M ₅ are all connected to the power supply; the first MOS transistor M ₁ , the second MOS transistor M 5 The sources of the MOS transistor M ₂ , the third MOS transistor M ₃ , the fourth MOS transistor M ₄ , and the fifth MOS transistor M ₅ are all grounded.

The ratio of the channel width-to-length ratio of the second MOS transistor _M2 to the _first MOS transistor M1 is a0 _;

The channel width-to-length ratios of the first MOS transistor M ₁ , the third MOS transistor M ₃ and the fourth MOS transistor M ₄ are equal;

The channel width-to-length ratios of the second MOS transistor _M2 and the _fifth MOS transistor M5 are equal.

As shown in Figure 3-1 and Figure 3-2, the first switched current bilinear integrator includes:

Sixth MOS transistor M ₆ , seventh MOS transistor M ₇ , eighth MOS transistor M ₈ , ninth MOS transistor M ₉ , tenth MOS transistor M ₁₀ , eleventh MOS transistor M ₁₁ , twelfth MOS transistor M ₁₂ , the thirteenth MOS transistor M ₁₃ , the fourteenth MOS transistor M ₁₄ , the second positive input terminal i _k ⁺ , the second negative input terminal i _k ^- , the second positive output terminal i _ak ⁺ , the second negative to the output terminal i _ak ^- , the first positive feedback output terminal _ifk ⁺ , the first negative feedback output terminal _ifk ^- and the first external output terminal _ick ⁺ ; k is the first switching current bilinear integrator The sequence number is a natural number greater than 0 and less than or equal to n-1;

The drain of the _sixth MOS transistor M6 is connected to the drain of the _seventh MOS transistor M7; the gate and drain of the _sixth MOS transistor M6 are connected by the first switch controlled by the _second clock φ2 ; The drain of the sixth MOS transistor M ₆ is connected to the second positive input terminal _ik ⁺ controlled by the second switch controlled by the second clock φ ₂ ; the drain of the sixth MOS transistor M ₆ is connected to the second negative input terminal ik+ connected to the input terminal i _k ^- the third switch controlled by the first clock φ ₁ ; φ ₁ and φ ₂ are two-phase non-overlapping clocks, and the clock waveform is shown in Figure 5.

The gate and drain of the _seventh MOS transistor M7 are connected by the fourth switch controlled by the _first clock φ1; the gate of the _seventh MOS transistor M7 is connected to the gate of the _eighth MOS transistor M8 ;

The drain of the _eighth MOS transistor M8 is connected to the second positive output terminal _iak ⁺ , and the gate of the _eighth MOS transistor M8 is connected to the gate of the _ninth MOS transistor M9;

The drain of the _ninth MOS transistor M9 is connected to the first external output terminal _ick ⁺ ;

The gate of the _ninth MOS transistor M9 is connected to the gate of the _tenth MOS transistor M10; the drain of the _tenth MOS transistor M10 is connected to the first forward feedback output terminal _ifk ⁺ ;

The gate of the _tenth MOS transistor M10 is connected to the gate of the _eleventh MOS transistor M11; the drain of the _eleventh MOS transistor M11 is connected to the drain of the _twelfth MOS transistor M12 and grid;

The gate of the _twelfth MOS transistor M12 is connected to the gate of the _thirteenth MOS transistor M13; the drain of the _thirteenth MOS transistor M13 is connected to the second negative output terminal i _ak ^- ;

The gate of the _thirteenth MOS transistor M13 is connected to the gate of the _fourteenth MOS transistor M14; the drain of the _fourteenth MOS transistor M14 is connected to the first negative feedback output terminal _ifk ^- ;

Sixth MOS transistor M ₆ , seventh MOS transistor M ₇ , eighth MOS transistor M ₈ , ninth MOS transistor M ₉ , tenth MOS transistor M ₁₀ , eleventh MOS transistor M ₁₁ , twelfth MOS transistor M ₁₂ , the drains of the thirteenth MOS tube M ₁₃ and the fourteenth MOS tube M ₁₄ are all connected to the power supply;

Sixth MOS transistor M ₆ , seventh MOS transistor M ₇ , eighth MOS transistor M ₈ , ninth MOS transistor M ₉ , tenth MOS transistor M ₁₀ , eleventh MOS transistor M ₁₁ , twelfth MOS transistor M ₁₂ The sources of the thirteenth MOS transistor M ₁₃ and the fourteenth MOS transistor M ₁₄ are all grounded.

Channel width-to-length ratios of the sixth MOS transistor M ₆ , the seventh MOS transistor M ₇ , the eleventh MOS transistor M ₁₁ , and the twelfth MOS transistor M ₁₂ are equal;

The channel width-to-length ratios of the _eighth MOS transistor M8 and the _thirteenth MOS transistor M13 are both a _k times the channel width-to-length ratio of the _sixth MOS transistor M6;

The channel width-to-length ratio of the _ninth MOS transistor M9 is c _k times the channel width-to-length ratio of the _sixth MOS transistor M6;

The channel width-to-length ratio of the _tenth MOS transistor M10 and the _fourteenth MOS transistor M14 is f _k times the channel width-to-length ratio of the _sixth MOS transistor M6.

The ratio between the current of the positive output terminal of the kth first switched current bilinear integrator and the current of the positive input terminal and the ratio of the negative output terminal of the kth first switched current bilinear integrator The ratio between the current and the current at the negative input is

The ratio between the current at the external output terminal of the kth first switch current bilinear integrator and the current at the positive input terminal is

The ratio of the current at the forward feedback output terminal of the kth first switch current bilinear integrator to the current at the forward input terminal is

The ratio of the current at the negative feedback output terminal of the kth first switch current bilinear integrator to the current at the positive input terminal is

As shown in Figure 4-1 and Figure 4-2, the second switch current bilinear integrator includes:

The fifteenth MOS transistor M ₁₅ , the sixteenth MOS transistor M ₁₆ , the seventeenth MOS transistor M ₁₇ , the eighteenth MOS transistor M ₁₈ , the nineteenth MOS transistor M ₁₉ , the twentieth MOS transistor M ₂₀ , the second Eleven MOS transistors M ₂₁ , the third positive input terminal _{i n} ⁺ , the third negative input terminal in ^- , the second positive feedback output terminal _ifn ⁺ , the second negative feedback output terminal _ifn ^- , the third Two external output terminals i _cn ⁺ ;

The drain of the _fifteenth MOS transistor M15 is connected to the drain of the _sixteenth MOS transistor M16, and the gate and drain of the _fifteenth MOS transistor M15 are switched by the _second clock φ2 The gate and drain of the sixteenth MOS transistor M ₁₆ are connected by a switch controlled by the first clock φ ₁ ; the drain of the fifteenth MOS transistor M ₁₅ is connected to the third ^positive input terminal in ₊ The switch controlled by the second clock φ ₂ is connected, and the drain of the fifteenth MOS transistor M ₁₅ is connected to the third negative input terminal ^in- _switch controlled by the first clock φ ₁ ;

The gate of the _sixteenth MOS transistor M16 is connected to the gate of the _seventeenth MOS transistor M17; the drain of the _seventeenth MOS transistor M17 is connected to the second external output terminal i _cn ⁺ ;

The gate of the _seventeenth MOS transistor M17 is connected to the gate of the _eighteenth MOS transistor M18; the drain of the _eighteenth MOS transistor M18 is connected to the second forward feedback output terminal _ifn ⁺ ;

The gate of the _eighteenth MOS transistor M18 is connected to the gate of the _nineteenth MOS transistor M19;

The drain of the _nineteenth MOS transistor M19 is connected to the drain and gate of the _twentieth MOS transistor M20;

The gate of the _twentieth MOS transistor M20 is connected to the gate of the _twenty -first MOS transistor M21;

The drain of the _twenty -first MOS transistor M21 is connected to the second negative feedback output terminal _ifn ⁻ ;

The fifteenth MOS transistor M ₁₅ , the sixteenth MOS transistor M ₁₆ , the seventeenth MOS transistor M ₁₇ , the eighteenth MOS transistor M ₁₈ , the nineteenth MOS transistor M ₁₉ , the twentieth MOS transistor M ₂₀ and the second The drains of the eleven MOS tubes M ₂₁ are all connected to the power supply;

The fifteenth MOS transistor M ₁₅ , the sixteenth MOS transistor M ₁₆ , the seventeenth MOS transistor M ₁₇ , the eighteenth MOS transistor M ₁₈ , the nineteenth MOS transistor M ₁₉ , the twentieth MOS transistor M ₂₀ and the second The sources of the eleven MOS transistors _M21 are all grounded.

The channel width-to-length ratios of the fifteenth MOS transistor M ₁₅ , the sixteenth MOS transistor M ₁₆ , the nineteenth MOS transistor M ₁₉ and the twentieth MOS transistor M ₂₀ are equal; the channel width of the seventeenth MOS transistor M ₁₇ is The length ratio is c _n times of the fifteenth MOS transistor M ₁₅ ; the channel width-to-length ratios of the eighteenth MOS transistor M ₁₈ and the twenty-first MOS transistor M ₂₁ are f _n times of the fifteenth MOS transistor M ₁₅ .

The ratio of the current at the external output terminal of the second switch current bilinear integrator to the current at the positive input terminal is

The ratio of the current at the forward feedback output terminal of the second switched current bilinear integrator to the current at the forward input terminal is

The ratio of the current at the negative feedback output terminal of the second switch current bilinear integrator to the current at the positive input terminal is

The external output terminals of the first switched current bilinear integrator and the external output terminals of the second switched current bilinear integrator are connected together as the output of the switched current filter, specifically:

When the external output terminal of the first switched current bilinear integrator outputs a negative current, the external output terminal of the first switched current bilinear integrator is connected to a first reverse circuit, and the first reverse circuit The output terminal of the circuit is connected with the external output terminals of other first switched current bilinear integrators and the second switched current bilinear integrator together as the output of the switched current filter; the first reverse circuit is used to convert The current output by the external output terminal of the first switched current bilinear integrator is reversed;

When the external output terminal of the second switched current bilinear integrator outputs a negative current, the external output terminal of the second switched current bilinear integrator is connected to a second reverse circuit, and the second reverse circuit The output terminal of the circuit and the external output terminal of the first switched current bilinear integrator are all connected together as the output of the switched current filter; the second reverse circuit is used to convert the second switched current bilinear integrator The current output of the external output terminal is reversed.

As shown in Figure 6, a leapfrog multi-loop feedback switching current filter includes:

A current mirror circuit cascaded in sequence, n-1 first switched current bilinear integrators and a second switched current bilinear integrator; n is an integer greater than 1;

The current mirror circuit is used to respectively copy and reverse the external input signal to generate n positive output signals and n negative output signals; the input terminal is connected to the external input signal; the first n-1 positive output signals The negative output signals are respectively connected to the positive input terminals of the n-1 first switching current bilinear integrators corresponding to the sequence number, and the first n-1 negative output signals are respectively connected to the n-1 first switch current bilinear integrators corresponding to the sequence number. The negative input terminal of the switch current bilinear integrator is connected; the positive output signal of the nth one is connected with the positive input terminal of the second switch current bilinear integrator, and the negative output signal of the nth one is The signal is connected to the negative input terminal of the second switched current bilinear integrator;

The first switched current bilinear integrator is used to integrate the current; the input terminal includes: a positive input terminal and a negative input terminal; the output terminal of the first switched current bilinear integrator includes a positive input terminal. output terminal, negative output terminal, positive feedback output terminal, and negative feedback output terminal; wherein, the positive output terminals of the first switching current bilinear integrator whose sequence numbers are 1 to n-2 respectively output To the positive input terminal of the next first switched current bilinear integrator in the cascade, the negative output terminals of the first switched current bilinear integrator whose sequence numbers are 1 to n-2 are respectively output to The negative input terminal of the next first switch current bilinear integrator in the cascade; the positive output terminal of the first switch current bilinear integrator whose sequence number is n-1 is output to the second switch current The positive input terminal of the bilinear integrator, the negative output terminal of the first switched current bilinear integrator whose serial number is n-1 is output to the cascaded second switched current bilinear integrator Negative input terminals; the positive feedback output terminals of the first switched current bilinear integrators whose serial numbers are 2 to n-1 are respectively output to the cascaded last first switched current bilinear integrators. Negative input terminals, the negative feedback output terminals of the first switched current bilinear integrators whose serial numbers are 2 to n-1 respectively output to the cascaded last first switched current bilinear integrators The positive input terminal, the positive feedback output terminal of the first switched current bilinear integrator with the serial number 1 is output to the negative input terminal of the first switched current bilinear integrator with the serial number 1, the serial number The negative feedback output terminal of the first switched current bilinear integrator whose serial number is 1 is output to the positive input terminal of the first switched current bilinear integrator whose serial number is 1;

The second switch current bilinear integrator is used to integrate the current. The input terminals include: a positive input terminal and a negative input terminal; the positive input terminal and the first switch current with the serial number n-1 The positive output terminal of the bilinear integrator is connected, and the negative input terminal is connected to the negative output terminal of the first switching current bilinear integrator whose serial number is n-1; the output terminal includes: a positive feedback output terminal , the negative feedback output terminal and the external output terminal; wherein, the positive feedback output terminal outputs to the negative input terminal of the first switching current bilinear integrator whose serial number is n-1, and the negative feedback output terminal outputs to the serial number of The positive input terminal of the n-1 first switched current bilinear integrator, and the external output terminal is the output of the switched current filter.

As shown in Figure 7-1 and Figure 7-2, the current mirror circuit includes:

The first MOS transistor M ₁ , the second MOS transistor M ₂ , the third MOS transistor M ₃ , n positive feedback output MOS transistors M _dj , n negative feedback output MOS transistors M _cj , the first input terminal I _in , n first positive output signals i _cj ⁺ , n first negative output signals i _cj ^- ; j is a natural number greater than or equal to 0 and less than or equal to n-1;

The drain of the _first MOS transistor M1 is connected to the first input terminal I _in , and the gate and drain of the _first MOS transistor M1 are connected;

The gates of the _first MOS transistor M1 are respectively connected to the gates of the n negative feedback output MOS transistors _Mcj ; the drains of the n negative feedback output MOS transistors _Mcj are respectively connected to the corresponding serial numbers The first negative output signal i _cj ^- ;

The gate of the _first MOS transistor M1 is connected to the gate of the _second MOS transistor M2;

The drain of the second MOS transistor _M2 is connected to the drain and gate of the _third MOS transistor M3;

The gate of the _third MOS transistor M3 is respectively connected to the gates of n said forward feedback output MOS transistors _Mdj ; the drains of the n said forward feedback output MOS transistors _Mdj are respectively connected to the corresponding serial number Describe the first forward output signal i _cj ⁺ ;

The drains of the first MOS transistor M ₁ , the second MOS transistor M ₂ , the third MOS transistor M ₃ , the n positive feedback output MOS transistors M _dj , and the n negative feedback output MOS transistors M _cj are all connected to the power supply;

The sources of the first MOS transistor M ₁ , the second MOS transistor M ₂ , the third MOS transistor M ₃ , the n positive feedback output MOS transistors M _dj , and the n negative feedback output MOS transistors M _cj are all grounded.

The channel width-to-length ratios of the first MOS transistor M ₁ , the second MOS transistor M ₂ and the third MOS transistor M ₃ are equal;

The positive feedback output MOS transistor M _dj and the negative feedback output MOS transistor M _cj with the same serial number have the same channel width-to-length ratio, and both are c _j times of the _first MOS transistor M1.

As shown in Figure 8-1 and Figure 8-2, the first switched current bilinear integrator includes:

The fourth MOS transistor M ₄ , the fifth MOS transistor M ₅ , the sixth MOS transistor M ₆ , the seventh MOS transistor M ₇ , the eighth MOS transistor M ₈ , the ninth MOS transistor M ₉ , the tenth MOS transistor M ₁₀ , the sixth MOS transistor M 10 Eleven MOS transistors M ₁₁ , the second positive input terminal i _k ⁺ , the second negative input terminal i _k ^- , the second positive output terminal i _ak ⁺ , the second negative output terminal i _ak ^- , the first positive To the feedback output terminal i _fk ⁺ and the first negative feedback output terminal i _fk ^- ; k is the serial number of the first switch current bilinear integrator, which is a natural number greater than 0 and less than or equal to n-1;

The drain of the _fourth MOS transistor M4 is connected to the drain of the _fifth MOS transistor M5; the gate and drain of the _fourth MOS transistor M4 are connected by the first switch controlled by the _second clock φ2 ; The drain of the fourth MOS transistor M ₄ is connected to the second positive input terminal _ik ⁺ controlled by the second switch controlled by the second clock φ ₂ ; the drain of the fourth MOS transistor M ₄ is connected to the second negative input terminal ik+ connected to the input terminal _ik ^- the third switch controlled by the first clock φ ₁ ; φ ₁ and φ ₂ are two-phase non-overlapping clocks, and the clock waveform is shown in FIG. 10 .

The gate and drain of the _fifth MOS transistor M5 are connected by the fourth switch controlled by the _first clock φ1; the gate of the _fifth MOS transistor M5 is connected to the gate of the _sixth MOS transistor M6 ;

The drain of the _sixth MOS transistor M6 is connected to the second positive output terminal _iak ⁺ , and the gate of the _sixth MOS transistor M6 is connected to the gate of the _seventh MOS transistor M7;

The drain of the _seventh MOS transistor M7 is connected to the first forward feedback output terminal _ifk ⁺ ;

The gate of the _seventh MOS transistor M7 is connected to the gate of the _eighth MOS transistor M8; the drain of the _eighth MOS transistor M8 is connected to the drain and gate of the _ninth MOS transistor M9 ;

The gate of the _ninth MOS transistor M9 is connected to the gate of the _tenth MOS transistor M10; the drain of the _tenth MOS transistor M10 is connected to the second negative output terminal i _ak ⁻ ;

The gate of the _tenth MOS transistor M10 is connected to the gate of the _eleventh MOS transistor M11 ^; the drain of the _eleventh MOS transistor M11 is connected to the first negative feedback output terminal _ifk- ;

The fourth MOS transistor M ₄ , the fifth MOS transistor M ₅ , the sixth MOS transistor M ₆ , the seventh MOS transistor M ₇ , the eighth MOS transistor M ₈ , the ninth MOS transistor M ₉ , the tenth MOS transistor M ₁₀ , the sixth MOS transistor M 10 The drains of the eleven MOS tubes M ₁₁ are all connected to the power supply;

The fourth MOS transistor M ₄ , the fifth MOS transistor M ₅ , the sixth MOS transistor M ₆ , the seventh MOS transistor M ₇ , the eighth MOS transistor M ₈ , the ninth MOS transistor M ₉ , the tenth MOS transistor M ₁₀ , the sixth MOS transistor M 10 The sources of the _eleven MOS transistors M11 are all grounded.

Channel width-to-length ratios of the fourth MOS transistor M ₄ , the fifth MOS transistor M ₅ , the eighth MOS transistor M ₈ , and the ninth MOS transistor M ₉ are equal;

The channel width-to-length ratios of the sixth MOS transistor _M6 and the _tenth MOS transistor M10 are both a _k times the channel width-to-length ratio of the _fourth MOS transistor M4;

The channel width-to-length ratio of the _seventh MOS transistor M7 and the _eleventh MOS transistor M11 is f _k times the channel width-to-length ratio of the _fourth MOS transistor M4.

The ratio between the current of the positive output terminal of the kth first switched current bilinear integrator and the current of the positive input terminal and the ratio of the negative output terminal of the kth first switched current bilinear integrator The ratio between the current and the current at the negative input is

The ratio of the current at the forward feedback output terminal of the kth first switch current bilinear integrator to the current at the forward input terminal is

The ratio of the current at the negative feedback output terminal of the kth first switch current bilinear integrator to the current at the positive input terminal is

As shown in Figure 9-1 and Figure 9-2, the second switch current bilinear integrator includes:

The twelfth MOS transistor M ₁₂ , the thirteenth MOS transistor M ₁₃ , the fourteenth MOS transistor M ₁₄ , the fifteenth MOS transistor M ₁₅ , the sixteenth MOS transistor M ₁₆ , the seventeenth MOS transistor M ₁₇ , the tenth Eight MOS transistors M ₁₈ , the third positive input terminal _{i n} ⁺ , the third negative input terminal in ^- , the second positive feedback output terminal _ifn ⁺ , the second negative feedback output terminal _ifn ^- , external output Terminal i _an ⁺ ;

The drain of the _twelfth MOS transistor M12 is connected to the drain of the _thirteenth MOS transistor M13, and the gate and drain of the _twelfth MOS transistor M12 are switched by the _second clock φ2 The gate and drain of the thirteenth MOS transistor M ₁₃ are connected by a switch controlled by the first clock φ ₁ ; the drain of the twelfth MOS transistor M ₁₂ is connected to the third ^positive input terminal in ₊ The switch controlled by the second clock φ ₂ is connected, and the drain of the twelfth MOS transistor M ₁₂ is connected to the third negative input terminal ^in- _switch controlled by the first clock φ ₁ ;

The gate of the _thirteenth MOS transistor M13 is connected to the gate of the _fourteenth MOS transistor M14; the drain of the _fourteenth MOS transistor M14 is connected to the external output terminal i _an ⁺ ;

The gate of the _fourteenth MOS transistor M14 is connected to the gate of the _fifteenth MOS transistor M15, and the drain of the _fifteenth MOS transistor M15 is connected to the second forward feedback output terminal _ifn ⁺ ;

The gate of the _fifteenth MOS transistor M15 is connected to the gate of the _sixteenth MOS transistor M16;

The drain of the _sixteenth MOS transistor M16 is connected to the drain and gate of the _seventeenth MOS transistor M17;

The gate of the _seventeenth MOS transistor M17 is connected to the gate of the _eighteenth MOS transistor M18;

The drain of the _eighteenth MOS transistor M18 is connected to the second negative feedback output terminal _ifn ⁻ ;

The twelfth MOS transistor M ₁₂ , the thirteenth MOS transistor M ₁₃ , the fourteenth MOS transistor M ₁₄ , the fifteenth MOS transistor M ₁₅ , the sixteenth MOS transistor M ₁₆ , the seventeenth MOS transistor M ₁₇ and the tenth _The drains of the eight MOS transistors M18 are all connected to the power supply;

The twelfth MOS transistor M ₁₂ , the thirteenth MOS transistor M ₁₃ , the fourteenth MOS transistor M ₁₄ , the fifteenth MOS transistor M ₁₅ , the sixteenth MOS transistor M ₁₆ , the seventeenth MOS transistor M ₁₇ and the tenth _The sources of the eight MOS transistors M18 are all grounded.

The channel width-to-length ratios of the twelfth MOS transistor M ₁₂ , the thirteenth MOS transistor M ₁₃ , the sixteenth MOS transistor M ₁₆ and the seventeenth MOS transistor M ₁₇ are equal; the channel width of the fourteenth MOS transistor M ₁₄ is The length ratio is a _n times that of the twelfth MOS transistor M ₁₂ ; the channel width-to-length ratio of the fifteenth MOS transistor M ₁₅ and the eighteenth MOS transistor M ₁₈ is f _n times that of the twelfth MOS transistor M ₁₂ .

The ratio of the current at the external output terminal of the second switch current bilinear integrator to the current at the positive input terminal is

The ratio of the current at the forward feedback output terminal of the second switched current bilinear integrator to the current at the forward input terminal is

The ratio of the current at the negative feedback output terminal of the second switch current bilinear integrator to the current at the positive input terminal is

The two switched current filter structures shown in Figure 1 and Figure 6 have the same leap-frog negative feedback connection, namely:

The positive feedback output terminals of the first switched current bilinear integrators whose serial numbers are 2 to n-1 are respectively output to the negative input terminals of the last cascaded first switched current bilinear integrator, The negative feedback output terminals of the first switched current bilinear integrators whose serial numbers are 2 to n-1 are respectively output to the positive input terminals of the last cascaded first switched current bilinear integrator, The positive feedback output terminal of the first switched current bilinear integrator whose serial number is 1 is output to the negative input terminal of the first switched current bilinear integrator whose serial number is 1, and the negative input terminal of the first switched current bilinear integrator whose serial number is 1 The negative feedback output terminal of the first switched current bilinear integrator is output to the positive input terminal of the first switched current bilinear integrator whose sequence number is 1;

The positive feedback output terminal of the second switched current bilinear integrator is output to the negative input terminal of the first switched current bilinear integrator whose sequence number is n-1, and the negative input terminal of the second switched current bilinear integrator The feedback output terminal is output to the positive input terminal of the first switched current bilinear integrator with the sequence number n-1.

The beneficial effects of the present invention are:

Realized by standard digital CMOS technology, it has the advantages of large dynamic range, simple design process, no need for analog-to-digital converter, suitable for large-scale integration of low voltage and low power consumption, etc.; it can accurately integrate the time constant of analog filter, so as to accurately realize analog filtering The frequency response characteristics of the filter; the cascaded structure of the switched current integrator with a leapfrog negative feedback branch to construct the filter can effectively shorten the length of the feedback path of the switched current filter and reduce the circuit sensitivity of the switched current filter.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present invention can easily think of changes or Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (10)

1. A jump-frog type multi-loop feedback switch current filter, is characterized in that, comprising: A current mirror circuit cascaded in sequence, n-1 first switched current bilinear integrators and a second switched current bilinear integrator; n is an integer greater than 1; The current mirror circuit is used to perform equivalent copy and reverse on the external input signal respectively to generate a forward output signal and a negative output signal; the input end is connected to the external input signal, and the serial number of the forward output signal is 1 The positive input terminal of the first switched current bilinear integrator is connected, and the negative output signal is connected with the negative input terminal of the first switched current bilinear integrator whose serial number is 1; The first switched current bilinear integrator is used to integrate the current; the input terminal includes: a positive input terminal and a negative input terminal; the output terminal of the first switched current bilinear integrator includes a positive input terminal. output terminal, negative output terminal, positive feedback output terminal, negative feedback output terminal and external output terminal; wherein, the positive direction of the first switching current bilinear integrator whose serial number is 1 to n-2 The output ends are respectively output to the positive input ends of the next cascaded first switched current bilinear integrator, and the negative outputs of the first switched current bilinear integrators whose serial numbers are 1 to n-2 terminals are respectively output to the negative input terminals of the next cascaded first switched current bilinear integrator; the positive output terminal of the first switched current bilinear integrator whose sequence number is n-1 is output to The positive input terminal of the second switched current bilinear integrator, the negative output terminal of the first switched current bilinear integrator with the serial number n-1 outputs to the cascaded second switched current bilinear integrator The negative input terminal of the linear integrator; the positive feedback output terminal of the first switch current bilinear integrator whose serial number is 2 to n-1 respectively outputs to the last first switch current bilinear integrator in the cascade The negative input terminal of the linear integrator, and the negative feedback output terminals of the first switch current bilinear integrator whose serial number is 2 to n-1 respectively output to the cascaded last first switch current bilinear The positive input terminal of the linear integrator, the positive feedback output terminal of the first switched current bilinear integrator whose sequence number is 1 outputs to the negative direction of the first switched current bilinear integrator whose sequence number is 1 The input terminal, the negative feedback output terminal of the first switched current bilinear integrator with serial number 1 is output to the positive input terminal of the first switched current bilinear integrator with serial number 1; The second switch current bilinear integrator is used to integrate the current. The input terminals include: a positive input terminal and a negative input terminal; the positive input terminal and the first switch current with the serial number n-1 The positive output terminal of the bilinear integrator is connected, and the negative input terminal is connected to the negative output terminal of the first switching current bilinear integrator whose serial number is n-1; the output terminal includes: a positive feedback output terminal , the negative feedback output terminal and the external output terminal; wherein, the positive feedback output terminal outputs to the negative input terminal of the first switching current bilinear integrator whose serial number is n-1, and the negative feedback output terminal outputs to the serial number of the positive input terminal of the first switched current bilinear integrator of n-1; The n-1 external output terminals of the first switched current bilinear integrator are connected to the external output terminals of the second switched current bilinear integrator, and they are used as the output of the switched current filter together. 2. leapfrog type multi-loop feedback switch current filter according to claim 1, is characterized in that, described current mirror circuit comprises: The first MOS transistor M ₁ , the second MOS transistor M ₂ , the third MOS transistor M ₃ , the fourth MOS transistor M ₄ , the fifth MOS transistor M ₅ , the first input terminal I _in , the first negative output terminal i _a0 ^- and the first positive output terminal i _a0 ⁺ ; The gate of the second MOS transistor _M2 is respectively connected to the gate and drain of the _first MOS transistor M1, and connected to the first input terminal _Iin ; the drain of the _second MOS transistor M2 is connected to the first negative output terminal i _a0 ⁻ ; the gate of the second MOS transistor _M2 is connected to the gate of the _third MOS transistor M3; The drain of the _third MOS transistor M3 is connected to the gate and drain of the _fourth MOS transistor M4; the gate of the _fourth MOS transistor M4 is connected to the gate of the _fifth MOS transistor M5 ; The drain of the _fifth MOS transistor M5 is connected to the first positive output terminal i _a0 ⁺ ; The drains of the first MOS transistor M ₁ , the second MOS transistor M ₂ , the third MOS transistor M ₃ , the fourth MOS transistor M ₄ , and the fifth MOS transistor M ₅ are all connected to the power supply; the first MOS transistor M ₁ , the second MOS transistor M 5 The sources of the MOS transistor M ₂ , the third MOS transistor M ₃ , the fourth MOS transistor M ₄ , and the fifth MOS transistor M ₅ are all grounded. 3. The leap-frog multi-loop feedback switch current filter according to claim 1, wherein the first switch current bilinear integrator comprises: Sixth MOS transistor M ₆ , seventh MOS transistor M ₇ , eighth MOS transistor M ₈ , ninth MOS transistor M ₉ , tenth MOS transistor M ₁₀ , eleventh MOS transistor M ₁₁ , twelfth MOS transistor M ₁₂ , the thirteenth MOS transistor M ₁₃ , the fourteenth MOS transistor M ₁₄ , the second positive input terminal i _k ⁺ , the second negative input terminal i _k ^- , the second positive output terminal i _ak ⁺ , the second negative to the output terminal i _ak ^- , the first positive feedback output terminal _ifk ⁺ , the first negative feedback output terminal _ifk ^- and the first external output terminal _ick ⁺ ; k is the first switching current bilinear integrator The sequence number is a natural number greater than 0 and less than or equal to n-1; The drain of the _sixth MOS transistor M6 is connected to the drain of the _seventh MOS transistor M7; the gate and drain of the _sixth MOS transistor M6 are connected by the first switch controlled by the second clock; The drain of the _sixth MOS transistor M6 is connected to the second positive input terminal i _k ⁺ by the second switch controlled by the second clock; the drain of the _sixth MOS transistor M6 is connected to the second negative input terminal i _k ^- connected by the third switch controlled by the first clock; The gate and drain of the _seventh MOS transistor M7 are connected by a fourth switch controlled by the first clock; the gate of the _seventh MOS transistor M7 is connected to the gate of the _eighth MOS transistor M8; The drain of the _eighth MOS transistor M8 is connected to the second positive output terminal _iak ⁺ , and the gate of the _eighth MOS transistor M8 is connected to the gate of the _ninth MOS transistor M9; The drain of the _ninth MOS transistor M9 is connected to the first external output terminal _ick ⁺ ; The gate of the _ninth MOS transistor M9 is connected to the gate of the _tenth MOS transistor M10; the drain of the _tenth MOS transistor M10 is connected to the first forward feedback output terminal _ifk ⁺ ; The gate of the _tenth MOS transistor M10 is connected to the gate of the _eleventh MOS transistor M11; the drain of the _eleventh MOS transistor M11 is connected to the drain of the _twelfth MOS transistor M12 and grid; The gate of the _twelfth MOS transistor M12 is connected to the gate of the _thirteenth MOS transistor M13; the drain of the _thirteenth MOS transistor M13 is connected to the second negative output terminal i _ak ^- ; The gate of the _thirteenth MOS transistor M13 is connected to the gate of the _fourteenth MOS transistor M14; the drain of the _fourteenth MOS transistor M14 is connected to the first negative feedback output terminal _ifk ^- ; Sixth MOS transistor M ₆ , seventh MOS transistor M ₇ , eighth MOS transistor M ₈ , ninth MOS transistor M ₉ , tenth MOS transistor M ₁₀ , eleventh MOS transistor M ₁₁ , twelfth MOS transistor M ₁₂ , the drains of the thirteenth MOS tube M ₁₃ and the fourteenth MOS tube M ₁₄ are all connected to the power supply; Sixth MOS transistor M ₆ , seventh MOS transistor M ₇ , eighth MOS transistor M ₈ , ninth MOS transistor M ₉ , tenth MOS transistor M ₁₀ , eleventh MOS transistor M ₁₁ , twelfth MOS transistor M ₁₂ The sources of the thirteenth MOS transistor M ₁₃ and the fourteenth MOS transistor M ₁₄ are all grounded. 4. leapfrog type multi-loop feedback switch current filter according to claim 1, is characterized in that, described second switch current bilinear integrator comprises: The fifteenth MOS transistor M ₁₅ , the sixteenth MOS transistor M ₁₆ , the seventeenth MOS transistor M ₁₇ , the eighteenth MOS transistor M ₁₈ , the nineteenth MOS transistor M ₁₉ , the twentieth MOS transistor M ₂₀ , the second Eleven MOS transistors M ₂₁ , the third positive input terminal _{i n} ⁺ , the third negative input terminal in ^- , the second positive feedback output terminal _ifn ⁺ , the second negative feedback output terminal _ifn ^- , the third Two external output terminals i _cn ⁺ ; The drain of the _fifteenth MOS transistor M15 is connected to the drain of the _sixteenth MOS transistor M16, and the gate and drain of the _fifteenth MOS transistor M15 are connected by a switch controlled by the second clock, The gate and drain of the _sixteenth MOS transistor M16 are connected by a switch controlled by the first clock; the drain of the _fifteenth MOS transistor M15 ^{and the third positive input terminal in+} _are connected by the second clock The controlled switch is connected, and the drain of the fifteenth MOS transistor M ₁₅ is connected to the third negative input terminal ^in- _connected by the switch controlled by the first clock; The gate of the _sixteenth MOS transistor M16 is connected to the gate of the _seventeenth MOS transistor M17; the drain of the _seventeenth MOS transistor M17 is connected to the second external output terminal i _cn ⁺ ; The gate of the _seventeenth MOS transistor M17 is connected to the gate of the _eighteenth MOS transistor M18; the drain of the _eighteenth MOS transistor M18 is connected to the second forward feedback output terminal _ifn ⁺ ; The gate of the _eighteenth MOS transistor M18 is connected to the gate of the _nineteenth MOS transistor M19; The drain of the _nineteenth MOS transistor M19 is connected to the drain and gate of the _twentieth MOS transistor M20; The gate of the _twentieth MOS transistor M20 is connected to the gate of the _twenty -first MOS transistor M21; The drain of the _twenty -first MOS transistor M21 is connected to the second negative feedback output terminal _ifn ⁻ ; The fifteenth MOS transistor M ₁₅ , the sixteenth MOS transistor M ₁₆ , the seventeenth MOS transistor M ₁₇ , the eighteenth MOS transistor M ₁₈ , the nineteenth MOS transistor M ₁₉ , the twentieth MOS transistor M ₂₀ and the second The drains of the eleven MOS tubes M ₂₁ are all connected to the power supply; The fifteenth MOS transistor M ₁₅ , the sixteenth MOS transistor M ₁₆ , the seventeenth MOS transistor M ₁₇ , the eighteenth MOS transistor M ₁₈ , the nineteenth MOS transistor M ₁₉ , the twentieth MOS transistor M ₂₀ and the second The sources of the eleven MOS transistors _M21 are all grounded. 5. leapfrog type multi-loop feedback switch current filter according to claim 4, is characterized in that, The channel width-to-length ratios of the fifteenth MOS transistor M ₁₅ , the sixteenth MOS transistor M ₁₆ , the nineteenth MOS transistor M ₁₉ and the twentieth MOS transistor M ₂₀ are equal; the channel width of the seventeenth MOS transistor M ₁₇ is The length ratio is c _n times of the fifteenth MOS transistor M ₁₅ ; the channel width-to-length ratios of the eighteenth MOS transistor M ₁₈ and the twenty-first MOS transistor M ₂₁ are f _n times of the fifteenth MOS transistor M ₁₅ . 6. leapfrog type multi-loop feedback switch current filter according to claim 1, is characterized in that, The external output terminals of the first switched current bilinear integrator and the external output terminals of the second switched current bilinear integrator are connected together as the output of the switched current filter, specifically: When the external output terminal of the first switched current bilinear integrator outputs a negative current, the external output terminal of the first switched current bilinear integrator is connected to a first reverse circuit, and the first reverse circuit The output terminal of the circuit is connected with the external output terminals of other first switched current bilinear integrators and the second switched current bilinear integrator together as the output of the switched current filter; the first reverse circuit is used to convert The current output by the external output terminal of the first switched current bilinear integrator is reversed; When the external output terminal of the second switched current bilinear integrator outputs a negative current, the external output terminal of the second switched current bilinear integrator is connected to a second reverse circuit, and the second reverse circuit The output terminal of the circuit and the external output terminal of the first switched current bilinear integrator are all connected together as the output of the switched current filter; the second reverse circuit is used to convert the second switched current bilinear integrator The current output of the external output terminal is reversed. 7. A leapfrog type multi-loop feedback switch current filter, characterized in that, comprising: A current mirror circuit cascaded in sequence, n-1 first switched current bilinear integrators and a second switched current bilinear integrator; n is an integer greater than 1; The current mirror circuit is used to respectively copy and reverse the external input signal to generate n positive output signals and n negative output signals; the input terminal is connected to the external input signal; the first n-1 positive output signals The negative output signals are respectively connected to the positive input terminals of the n-1 first switching current bilinear integrators corresponding to the sequence number, and the first n-1 negative output signals are respectively connected to the n-1 first switch current bilinear integrators corresponding to the sequence number. The negative input terminal of the switch current bilinear integrator is connected; the positive output signal of the nth one is connected with the positive input terminal of the second switch current bilinear integrator, and the negative output signal of the nth one is The signal is connected to the negative input terminal of the second switched current bilinear integrator; The first switched current bilinear integrator is used to integrate the current; the input terminal includes: a positive input terminal and a negative input terminal; the output terminal of the first switched current bilinear integrator includes a positive input terminal. output terminal, negative output terminal, positive feedback output terminal, and negative feedback output terminal; wherein, the positive output terminals of the first switching current bilinear integrator whose sequence numbers are 1 to n-2 respectively output To the positive input terminal of the next first switched current bilinear integrator in the cascade, the negative output terminals of the first switched current bilinear integrator whose sequence numbers are 1 to n-2 are respectively output to The negative input terminal of the next first switch current bilinear integrator in the cascade; the positive output terminal of the first switch current bilinear integrator whose sequence number is n-1 is output to the second switch current The positive input terminal of the bilinear integrator, the negative output terminal of the first switched current bilinear integrator whose serial number is n-1 is output to the cascaded second switched current bilinear integrator Negative input terminals; the positive feedback output terminals of the first switched current bilinear integrators whose serial numbers are 2 to n-1 are respectively output to the cascaded last first switched current bilinear integrators. Negative input terminals, the negative feedback output terminals of the first switched current bilinear integrators whose serial numbers are 2 to n-1 respectively output to the cascaded last first switched current bilinear integrators The positive input terminal, the positive feedback output terminal of the first switched current bilinear integrator with the serial number 1 is output to the negative input terminal of the first switched current bilinear integrator with the serial number 1, the serial number The negative feedback output terminal of the first switched current bilinear integrator whose serial number is 1 is output to the positive input terminal of the first switched current bilinear integrator whose serial number is 1; The second switch current bilinear integrator is used to integrate the current. The input terminals include: a positive input terminal and a negative input terminal; the positive input terminal and the first switch current with the serial number n-1 The positive output terminal of the bilinear integrator is connected, and the negative input terminal is connected to the negative output terminal of the first switching current bilinear integrator whose serial number is n-1; the output terminal includes: a positive feedback output terminal , the negative feedback output terminal and the external output terminal; wherein, the positive feedback output terminal outputs to the negative input terminal of the first switching current bilinear integrator whose serial number is n-1, and the negative feedback output terminal outputs to the serial number of The positive input terminal of the n-1 first switched current bilinear integrator, and the external output terminal is the output of the switched current filter. 8. leapfrog type multi-loop feedback switch current filter according to claim 7, is characterized in that, described current mirror circuit comprises: The first MOS transistor M ₁ , the second MOS transistor M ₂ , the third MOS transistor M ₃ , n positive feedback output MOS transistors M _dj , n negative feedback output MOS transistors M _cj , the first input terminal I _in , n first positive output signals i _cj ⁺ , n first negative output signals i _cj ^- ; j is a natural number greater than or equal to 0 and less than or equal to n-1; The drain of the _first MOS transistor M1 is connected to the first input terminal I _in , and the gate and drain of the _first MOS transistor M1 are connected; The gates of the _first MOS transistor M1 are respectively connected to the gates of the n negative feedback output MOS transistors _Mcj ; the drains of the n negative feedback output MOS transistors _Mcj are respectively connected to the corresponding serial numbers The first negative output signal i _cj ^- ; The gate of the _first MOS transistor M1 is connected to the gate of the _second MOS transistor M2; The drain of the second MOS transistor _M2 is connected to the drain and gate of the _third MOS transistor M3; The gate of the _third MOS transistor M3 is respectively connected to the gates of n said forward feedback output MOS transistors _Mdj ; the drains of the n said forward feedback output MOS transistors _Mdj are respectively connected to the corresponding serial number Describe the first forward output signal i _cj ⁺ ; The drains of the first MOS transistor M ₁ , the second MOS transistor M ₂ , the third MOS transistor M ₃ , the n positive feedback output MOS transistors M _dj , and the n negative feedback output MOS transistors M _cj are all connected to the power supply; The sources of the first MOS transistor M ₁ , the second MOS transistor M ₂ , the third MOS transistor M ₃ , the n positive feedback output MOS transistors M _dj , and the n negative feedback output MOS transistors M _cj are all grounded. 9. The leap-frog multi-loop feedback switch current filter according to claim 7, wherein the first switch current bilinear integrator comprises: The fourth MOS transistor M ₄ , the fifth MOS transistor M ₅ , the sixth MOS transistor M ₆ , the seventh MOS transistor M ₇ , the eighth MOS transistor M ₈ , the ninth MOS transistor M ₉ , the tenth MOS transistor M ₁₀ , the sixth MOS transistor M 10 Eleven MOS transistors M ₁₁ , the second positive input terminal i _k ⁺ , the second negative input terminal i _k ^- , the second positive output terminal i _ak ⁺ , the second negative output terminal i _ak ^- , the first positive To the feedback output terminal i _fk ⁺ and the first negative feedback output terminal i _fk ^- ; k is the serial number of the first switch current bilinear integrator, which is a natural number greater than 0 and less than or equal to n-1; The drain of the _fourth MOS transistor M4 is connected to the drain of the _fifth MOS transistor M5; the gate and drain of the _fourth MOS transistor M4 are connected by the first switch controlled by the second clock; The drain of the _fourth MOS transistor M4 is connected to the second positive input terminal i _k ⁺ by the second switch controlled by the second clock; the drain of the _fourth MOS transistor M4 is connected to the second negative input terminal i _k ^- connected by the third switch controlled by the first clock; The gate and drain of the _fifth MOS transistor M5 are connected by a fourth switch controlled by the first clock; the gate of the _fifth MOS transistor M5 is connected to the gate of the _sixth MOS transistor M6; The drain of the _sixth MOS transistor M6 is connected to the second positive output terminal _iak ⁺ , and the gate of the _sixth MOS transistor M6 is connected to the gate of the _seventh MOS transistor M7; The drain of the _seventh MOS transistor M7 is connected to the first forward feedback output terminal _ifk ⁺ ; The gate of the _seventh MOS transistor M7 is connected to the gate of the _eighth MOS transistor M8; the drain of the _eighth MOS transistor M8 is connected to the drain and gate of the _ninth MOS transistor M9 ; The gate of the _ninth MOS transistor M9 is connected to the gate of the _tenth MOS transistor M10; the drain of the _tenth MOS transistor M10 is connected to the second negative output terminal i _ak ⁻ ; The gate of the _tenth MOS transistor M10 is connected to the gate of the _eleventh MOS transistor M11 ^; the drain of the _eleventh MOS transistor M11 is connected to the first negative feedback output terminal _ifk- ; The fourth MOS transistor M ₄ , the fifth MOS transistor M ₅ , the sixth MOS transistor M ₆ , the seventh MOS transistor M ₇ , the eighth MOS transistor M ₈ , the ninth MOS transistor M ₉ , the tenth MOS transistor M ₁₀ , the sixth MOS transistor M 10 The drains of the eleven MOS tubes M ₁₁ are all connected to the power supply; The fourth MOS transistor M ₄ , the fifth MOS transistor M ₅ , the sixth MOS transistor M ₆ , the seventh MOS transistor M ₇ , the eighth MOS transistor M ₈ , the ninth MOS transistor M ₉ , the tenth MOS transistor M ₁₀ , the sixth MOS transistor M 10 The sources of the _eleven MOS transistors M11 are all grounded. 10. The leapfrog type multi-loop feedback switch current filter according to claim 7, wherein the second switch current bilinear integrator comprises: The twelfth MOS transistor M ₁₂ , the thirteenth MOS transistor M ₁₃ , the fourteenth MOS transistor M ₁₄ , the fifteenth MOS transistor M ₁₅ , the sixteenth MOS transistor M ₁₆ , the seventeenth MOS transistor M ₁₇ , the tenth Eight MOS transistors M ₁₈ , the third positive input terminal _{i n} ⁺ , the third negative input terminal in ^- , the second positive feedback output terminal _ifn ⁺ , the second negative feedback output terminal _ifn ^- , external output Terminal i _an ⁺ ; The drain of the _twelfth MOS transistor M12 is connected to the drain of the _thirteenth MOS transistor M13, and the gate and drain of the _twelfth MOS transistor M12 are connected by a switch controlled by the second clock, The gate and drain of the _thirteenth MOS transistor M13 are connected by a switch controlled by the first clock; the drain of the _twelfth MOS transistor M12 ^{and the third positive input terminal in+} _are connected by the second clock The controlled switch is connected, and the drain of the twelfth MOS transistor M ₁₂ is connected to the third negative input terminal ^in- _connected by the switch controlled by the first clock; The gate of the _thirteenth MOS transistor M13 is connected to the gate of the _fourteenth MOS transistor M14; the drain of the _fourteenth MOS transistor M14 is connected to the external output terminal i _an ⁺ ; The gate of the _fourteenth MOS transistor M14 is connected to the gate of the _fifteenth MOS transistor M15, and the drain of the _fifteenth MOS transistor M15 is connected to the second forward feedback output terminal _ifn ⁺ ; The gate of the _fifteenth MOS transistor M15 is connected to the gate of the _sixteenth MOS transistor M16; The drain of the _sixteenth MOS transistor M16 is connected to the drain and gate of the _seventeenth MOS transistor M17; The gate of the _seventeenth MOS transistor M17 is connected to the gate of the _eighteenth MOS transistor M18; The drain of the _eighteenth MOS transistor M18 is connected to the second negative feedback output terminal _ifn ⁻ ; The twelfth MOS transistor M ₁₂ , the thirteenth MOS transistor M ₁₃ , the fourteenth MOS transistor M ₁₄ , the fifteenth MOS transistor M ₁₅ , the sixteenth MOS transistor M ₁₆ , the seventeenth MOS transistor M ₁₇ and the tenth _The drains of the eight MOS transistors M18 are all connected to the power supply; The twelfth MOS transistor M ₁₂ , the thirteenth MOS transistor M ₁₃ , the fourteenth MOS transistor M ₁₄ , the fifteenth MOS transistor M ₁₅ , the sixteenth MOS transistor M ₁₆ , the seventeenth MOS transistor M ₁₇ and the tenth _The sources of the eight MOS transistors M18 are all grounded.