CN203151447U - Current mode five step Marr wavelet filter circuit - Google Patents
Current mode five step Marr wavelet filter circuit Download PDFInfo
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- CN203151447U CN203151447U CN 201320142673 CN201320142673U CN203151447U CN 203151447 U CN203151447 U CN 203151447U CN 201320142673 CN201320142673 CN 201320142673 CN 201320142673 U CN201320142673 U CN 201320142673U CN 203151447 U CN203151447 U CN 203151447U
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Abstract
The utility model discloses a current mode five step Marr wavelet filter circuit which employs switched current technology. According to the technology solution provided by the utility model, the current mode five-step Marr wavelet filter circuit comprises an input current copy unit, a switch current first order circuit and two switch current second order power-saving circuits. The switch current first order power-saving circuit is connected with the two switch current second order circuits in parallel; the input terminals of the switch current first order circuit and the two switch second order current circuits are respectively connected with three current signal output terminals of the current copy unit; the output terminals of the switch current first order circuit and the switch current second order circuits are connected together to achieve summing and output of the outputted current signals ; and the impulse responsive waveform outputted by the circuit is similar with ideal Marr wavelet. The current mode five-step Marr wavelet filter circuit has advantages of good circuit performance and a good effect of being close to the Marr wavelet. The first order circuit and the two second circuits have ideal and less parameters, wherein the first order circuit only has two parameters and the second order power saving circuit only has four parameters. The circuit parameter sizes are relatively uniform, which is beneficial for circuit board design.
Description
Technical field
The utility model belongs to the Electronics and Information Engineering field, relates to a kind of current-mode five rank Marr wavelet filter circuit.
Background technology
Wavelet transformation is with its good time-frequency local characteristics, is widely used in non-stationary and transient signal and handles, one of efficient mathematical instrument that has become now that each engineering field signal handles.
Wavelet transformation can be realized also can realizing with hardware with software.Realize wavelet transformation with hardware, particularly realize with analog circuit, owing to have low in energy consumption, fireballing advantage, be subjected to more and more the attention.Analog circuit realization wavelet transformation can be regarded the linear combination of the yardstick wavelet filter different with displacement as, so the design of wavelet filter is the basis of realizing wavelet transformation.
Switched current technique is a kind of advanced person's current-mode circuit designing technique, and its handles the analog signal of continuous time with the sampled data system of discrete time, and has the following advantages: high frequency characteristics is good, be suitable for low voltage operating, dynamic range is big.Compare with the switching capacity filter based on voltage mode, Switched-Current Filter is not used amplifier, thus restriction and error that circuit simply, does not exist amplifier to bring, and compatible fully with the CMOS technology of standard, be convenient to the integrated on a large scale of circuit.
Therefore, be of great immediate significance and using value based on switched current technique design and realization current-mode wavelet filter.
The utility model content
The utility model provides a kind of current-mode five rank Marr wavelet filter circuit, and circuit adopts the mode that is connected in parallel.
Described current-mode five rank Marr wavelet filter circuit, its s territory transfer function is
In the formula, the s territory transfer function of H (s) expression five rank Marr wavelet filters, s represents complex frequency.
System function H (s) to five rank Marr wavelet filters carries out the z conversion, and it is transformed into the z territory, obtains the z territory transfer function of five rank Marr wavelet filters:
In the formula, the z territory transfer function of H (z) expression five rank Marr wavelet filters, z represents discrete complex variable.
Adopt second generation switched current technique, according to the digital filter design method, design the realization circuit of the z territory transfer function H (z) of above-mentioned five rank Marr wavelet filters, circuit comprises: an input current copy cell; A switching current single order economize on electricity road and two switching current second order economize on electricity roads.
Described switching current single order economize on electricity road adopts mode in parallel to be connected with two switching current second order economize on electricity roads, switching current single order economize on electricity road and the input on switching current second order economize on electricity road are connected three current signal output ends of input current copy cell respectively, and the output on switching current single order economize on electricity road and switching current second order economize on electricity road links together and realizes output current signal addition and output.
Described input current copy cell adopts 6 N-type metal-oxide-semiconductors (NMOS) and bias current sources thereof to form, and comprises a current signal input and three current signal output ends.Described input current copy cell is given a switching current single order economize on electricity road and two switching current second order economize on electricity roads respectively with three parts in input current signal copy; The input current copy cell plays the effect of isolating input current signal and switching current single order economize on electricity road and switching current second order economize on electricity road feedback signal simultaneously.
Described switching current single order economize on electricity road adopts 4 switches, 4 N-type metal-oxide-semiconductors (NMOS) and bias current sources thereof to form, input connects the output of input current copy cell, and the output on output and switching current second order economize on electricity road links together and realizes output current signal addition and output.4 switches that adopt on described switching current single order economize on electricity road are by two-phase non-overlapping clock signal controlling, switch opens when clock signal is high level, and switch cut out when clock signal was low level.Described switching current single order economize on electricity road uses the grid-source parasitic capacitance of 2 N-type metal-oxide-semiconductors (NMOS).4 N-type metal-oxide-semiconductors (NMOS) in the described switching current single order economize on electricity road, wherein 2 breadth length ratios (W/L) are 1, other 2 breadth length ratios (W/L) are respectively 1.3550 and 0.9540.
Described switching current second order economize on electricity road adopts 8 switches, 17 N-type metal-oxide-semiconductors (NMOS) and bias current sources thereof to form, input connects the output of input current copy cell, and the output on output and switching current single order economize on electricity road links together and realizes output current signal addition and output.8 switches that adopt on described switching current second order economize on electricity road are by two-phase non-overlapping clock signal controlling, switch opens when clock signal is high level, and switch cut out when clock signal was low level.Described switching current single order economize on electricity road uses the grid-source parasitic capacitance of 4 N-type metal-oxide-semiconductors (NMOS).17 N-type metal-oxide-semiconductors (NMOS) in first switching current second order economize on electricity road, wherein 13 breadth length ratio (W/L) is 1, other 4 breadth length ratio (W/L) is respectively 0.9084,0.9686,1.9580 and 0.9686; 17 N-type metal-oxide-semiconductors (NMOS) in second switching current second order economize on electricity road, wherein 13 breadth length ratio (W/L) is 1, other 4 breadth length ratio (W/L) is respectively 0.2659,0.1446,1.9613 and 0.9651.
The beneficial effects of the utility model are: 1, a kind of current-mode five rank Marr wavelet filter circuit are provided, and the circuit overall performance is outstanding, approaches the effective of desirable Marr small echo.The single order economize on electricity road of 2, adopting and biquadratic economize on electricity road have desirable parameter, and the one, circuit parameter is few, and single order economize on electricity road has only two parameters, and second order economize on electricity road has only four parameters; The 2nd, the circuit parameter size is homogeneous comparatively, is beneficial to the circuit layout design.
Description of drawings
Fig. 1 is current-mode five rank Marr wavelet filter circuit diagrams.
Fig. 2 is the clock signal sequential chart of control circuit switch.
Fig. 3 is Marr small echo ideal waveform figure.
Fig. 4 is circuit impulse response simulation waveform figure of the present utility model.
Fig. 5 is circuit pole-zero plot of the present utility model.
Embodiment
The utility model provides a kind of current-mode five rank Marr wavelet filter circuit, the circuit sampling mode that is connected in parallel.According to the technical scheme that the utility model provides, a kind of current-mode five rank Marr wavelet filter circuit comprise: an input current copy cell; A switching current single order economize on electricity road and two switching current second order economize on electricity roads.
Described input current copy cell embodiment explanation:
As shown in Figure 1, described input current copy cell adopts 6 N-type metal-oxide-semiconductors (NMOS) and bias current sources thereof to form, 6 N-type metal-oxide-semiconductors (NMOS) are respectively M1-M6, its breadth length ratio (W/L) is 1, and the connected mode of each metal-oxide-semiconductor is described below: the connection of (1) metal-oxide-semiconductor M1: drain electrode and input current signal input (
i In) link to each other, and link to each other with power vd D by the bias current sources that a size is J, grid links to each other with drain electrode, links to each other with the grid of M2 simultaneously, and source electrode links to each other with ground; (2) connection of metal-oxide-semiconductor M2: drain electrode links to each other with the drain electrode of M3, and links to each other with power vd D by the bias current sources that a size is 2J, and grid links to each other with the grid of M1, and source electrode links to each other with ground; (3) connection of metal-oxide-semiconductor M3: drain electrode links to each other with the drain electrode of M2, and grid links to each other with the grid of M4, M5 and M6, and source electrode links to each other with ground; (4) connection of metal-oxide-semiconductor M4: from its drain electrode draw a current signal output end and switching current single order economize on electricity road input (
i In1) connect, the bias current sources that drain electrode is J by a size also links to each other with power vd D, and grid links to each other with the grid of M3, M5 and M6, and source electrode links to each other with ground; (5) connection of metal-oxide-semiconductor M5: from its drain electrode draw a current signal output end and first switching current second order economize on electricity road input (
i In2) connect, the bias current sources that drain electrode is J by a size also links to each other with power vd D, and grid links to each other with the grid of M3, M4 and M6, and source electrode links to each other with ground; (6) connection of metal-oxide-semiconductor M6: from its drain electrode draw a current signal output end and second switching current second order economize on electricity road input (
i In3) connect, the bias current sources that drain electrode is J by a size also links to each other with power vd D, and grid links to each other with the grid of M3, M4 and M5, and source electrode links to each other with ground.
Described switching current single order economize on electricity road embodiment explanation:
As shown in Figure 1, described switching current single order economize on electricity road adopts 4 switches and 4 N-type metal-oxide-semiconductors (NMOS) and bias current sources thereof to form, and 4 switches are respectively s
1-s
4, 4 N-type metal-oxide-semiconductors (NMOS) are respectively M7-M10, the breadth length ratio (W/L) that the breadth length ratio of M7 and M8 (W/L) is 1, M9 is b
11The breadth length ratio of=0.9540, M10 (W/L) is a
10=1.3550.The connected mode of each metal-oxide-semiconductor is described below: the connection of (1) metal-oxide-semiconductor M7: the drain electrode by open in
φ 1The switch s of phase
1With the input on switching current single order economize on electricity road (
i In1) and the drain electrode of M9 connect, the bias current sources that drain electrode is J by a size also links to each other with power vd D, grid by open in
φ 1The switch s of phase
2Link to each other with drain electrode, source electrode links to each other with ground, and circuit utilizes the parasitic capacitance c between grid and the source electrode
1Carry out the storage of electric charge; (2) connection of metal-oxide-semiconductor M8: the drain electrode by open in
φ 2The switch s of phase
3Be connected with the drain electrode of M7, drain electrode is J by a size also bias current sources links to each other with power vd D, grid by open in
φ 2The switch s of phase
4Link to each other with drain electrode, source electrode links to each other with ground, and circuit utilizes the parasitic capacitance c between grid and the source electrode
2Carry out the storage of electric charge; (3) connection of metal-oxide-semiconductor M9: the drain electrode by open in
φ 1The switch s of phase
1Be connected with the drain electrode of M7, drain electrode is b by a size also
11The bias current sources of J links to each other with power vd D, and grid links to each other with the grid of M8 and M10, and source electrode links to each other with ground; (4) connection of metal-oxide-semiconductor M10: from its drain electrode draw switching current single order economize on electricity road output (
i Out1), drain electrode is a by a size also
10The bias current sources of J links to each other with power vd D, and grid links to each other with the grid of M8 and M9, and source electrode links to each other with ground.
Described switching current second order economize on electricity road embodiment explanation:
As shown in Figure 1, described first switching current second order economize on electricity road adopts 8 switches, 17 N-type metal-oxide-semiconductors (NMOS) and bias current sources thereof to form, and 8 switches are respectively s
5-s
12, 17 N-type metal-oxide-semiconductors (NMOS) are respectively M11-M27, wherein the breadth length ratio of M14, M20, M21, M25 (W/L) is respectively a
20=0.9084, a
21=0.9686, b
21=1.9580 and b
22=0.9686, and the source electrode of these 4 NMOS pipes (M14, M20, M21 and M25) ground connection all, drain electrode is a by size respectively
20J, a
21J, b
21J and b
22The current source of J links to each other with power vd D; The breadth length ratio (W/L) of other 13 NMOS pipes (M11, M12, M13, M15, M16, M17, M18, M19, M22, M23, M24, M26, M27) is 1, source electrode is ground connection all, drain electrode is that the current source of J links to each other with power vd D by size, because the drain electrode of M12 and M13 links to each other, the size of M12 and M13 is that the current source of J is merged into the current source of a big or small 2J and linked to each other with power vd D.Described 17 NMOS pipes are except above-mentioned connection, and other connected mode of each NMOS pipe is described below: (1) NMOS manages M11: from its drain electrode draw first switching current second order economize on electricity road input (
i In2), input (
i In2) link to each other with the drain electrode of NMOS pipe M5, its drain electrode also is connected with the drain electrode of NMOS pipe M21 and M27, and its drain electrode also is connected with its grid, and grid is connected with the grid of M12; (2) NMOS pipe M12: drain electrode is connected with the drain electrode of M13, and grid is connected with drain electrode with the grid of M11; (3) NMOS pipe M13: drain electrode is connected with the drain electrode of M12, and grid is connected with the grid of M14 and M17; (4) NMOS pipe M14: drain electrode is connected with the drain electrode of M15, and grid is connected with the grid of M13 and M17; (5) NMOS pipe M15: drain electrode is connected with the drain electrode of M14, and grid links to each other with drain electrode, and grid also is connected with the grid of M16; (6) NMOS pipe M16: drain electrode is connected with the drain electrode of M20, and grid is connected with the grid of M15; (7) NMOS pipe M17: drain electrode by open in
φ 1The switch s of phase
5Be connected with the drain electrode of M18, grid is connected with the grid of M13 and M14; (8) NMOS pipe M18: drain electrode by open in
φ 1The switch s of phase
5Be connected with the drain electrode of M17, the drain electrode also by open in
φ 1The switch s of phase
6Be connected with its grid, the drain electrode also by open in
φ 2The switch s of phase
7Be connected with the drain electrode of M19, utilize the parasitic capacitance c between its grid and the source electrode
3Carry out charge storage; (9) NMOS pipe M19: drain electrode by open in
φ 2The switch s of phase
7Be connected with the drain electrode of M18, the drain electrode also by open in
φ 2The switch s of phase
8Be connected with its grid, grid is connected with the grid of M20, M21 and M22 simultaneously, utilizes the parasitic capacitance c between its grid and the source electrode
4Carry out charge storage; (10) NMOS pipe M20: drain electrode is connected with the drain electrode of M16, from drain electrode draw first switching current second order economize on electricity the road output (
i Out2), grid is connected with the grid of M19, M21 and M22; (11) NMOS pipe M21: drain electrode is connected with the drain electrode of M11 and M27, and grid is connected with the grid of M19, M20 and M22; (12) NMOS pipe M22: drain electrode by open in
φ 1The switch s of phase
9Be connected with the drain electrode of M23, grid is connected with the grid of M19, M20 and M21; (13) NMOS pipe M23: drain electrode by open in
φ 1The switch s of phase
9Be connected with the drain electrode of M22, the drain electrode also by open in
φ 1The switch s of phase
10Be connected with its grid, the drain electrode also by open in
φ 2The switch s of phase
11Be connected with the drain electrode of M24, utilize the parasitic capacitance c between its grid and the source electrode
5Carry out charge storage; (14) NMOS pipe M24: drain electrode by open in
φ 2The switch s of phase
11Be connected with the drain electrode of M23, the drain electrode also by open in
φ 2The switch s of phase
12Be connected with its grid, grid is connected with the grid of M25, utilizes the parasitic capacitance c between its grid and the source electrode
6Carry out charge storage; (15) NMOS pipe M25: drain electrode is connected with the drain electrode of M26, and grid is connected with the grid of M24; (16) NMOS pipe M26: drain electrode is connected with grid, and drain electrode also is connected with the drain electrode of M25, and grid is connected with the grid of M27; (17) NMOS pipe M27: drain electrode is connected with the drain electrode of M11 and M21 simultaneously, and grid is connected with drain electrode with the grid of M26.
As shown in Figure 1, described second switching current second order economize on electricity road adopts 8 switches, 17 N-type metal-oxide-semiconductors (NMOS) and bias current sources thereof to form, and 8 switches are respectively s
13-s
20, 17 N-type metal-oxide-semiconductors (NMOS) are respectively M28-M44, wherein the breadth length ratio of M31, M37, M38, M42 (W/L) is respectively a
30=0.2659, a
31=0.1446, b
31=1.9613 and b
32=0.9651, and the source electrode of these 4 NMOS pipes (M31, M37, M38, M42) ground connection all, drain electrode is a by size respectively
30J, a
31J, b
31J and b
32The current source of J links to each other with power vd D; The breadth length ratio (W/L) of other 13 NMOS pipes (M28, M29, M30, M32, M33, M34, M35, M36, M39, M40, M41, M43, M44) is 1, source electrode is ground connection all, drain electrode is that the current source of J links to each other with power vd D by size, because the drain electrode of M29 and M30 links to each other, the size of M29 and M30 is that the current source of J is merged into the current source of a big or small 2J and linked to each other with power vd D.Described 17 NMOS pipes are except above-mentioned connection, and other connected mode of each NMOS pipe is described below: (1) NMOS manages M28: from its drain electrode draw second switching current second order economize on electricity road input (
i In3), input (
i In3) link to each other with the drain electrode of NMOS pipe M6, its drain electrode also is connected with the drain electrode of NMOS pipe M38 and M42, and its drain electrode also is connected with its grid, and grid is connected with the grid of M29; (2) NMOS pipe M29: drain electrode is connected with the drain electrode of M30, and grid is connected with drain electrode with the grid of M28; (3) NMOS pipe M30: drain electrode is connected with the drain electrode of M29, and grid is connected with the grid of M31 and M34; (4) NMOS pipe M31: drain electrode is connected with the drain electrode of M32, and grid is connected with the grid of M30 and M34; (5) NMOS pipe M32: drain electrode is connected with grid, and grid is connected with the grid of M33; (6) NMOS pipe M33: drain electrode is connected with the drain electrode of M37, and grid is connected with the grid of M32; (7) NMOS pipe M34: drain electrode by open in
φ 1The switch s of phase
13Be connected with the drain electrode of M35, grid is connected with the grid of M30 and M31; (8) NMOS pipe M35: drain electrode by open in
φ 1The switch s of phase
13Be connected with the drain electrode of M34, the drain electrode also by open in
φ 1The switch s of phase
14Be connected with its grid, utilize the parasitic capacitance c between its grid and the source electrode
7Carry out charge storage; (9) NMOS pipe M36: drain electrode by open in
φ 2The switch s of phase
15Be connected with the drain electrode of M35, the drain electrode also by open in
φ 2The switch s of phase
16Be connected with its grid, grid is connected with the grid of M37, M38 and M39 simultaneously, utilizes the parasitic capacitance c between its grid and the source electrode
8Carry out charge storage; (10) NMOS pipe M37: drain electrode is connected with the drain electrode of M33, from drain electrode draw second switching current second order economize on electricity the road output (
i Out3), grid is connected with the grid of M36, M38 and M39; (11) NMOS pipe M38: drain electrode is connected with the drain electrode of M28 and M44, and grid is connected with the grid of M36, M37 and M39; (12) NMOS pipe M39: drain electrode by open in
φ 1The switch s of phase
17Be connected with the drain electrode of M40, grid is connected with the grid of M36, M37 and M38; (13) NMOS pipe M40: drain electrode by open in
φ 1The switch s of phase
17Be connected with the drain electrode of M39, the drain electrode also by open in
φ 1The switch s of phase
18Be connected with its grid, the drain electrode also by open in
φ 2The switch s of phase
19Be connected with the drain electrode of M41, utilize the parasitic capacitance c between its grid and the source electrode
9Carry out charge storage; (14) NMOS pipe M41: drain electrode by open in
φ 2The switch s of phase
19Be connected with the drain electrode of M40, the drain electrode also by open in
φ 2The switch s of phase
20Be connected with its grid, grid is connected with the grid of M42, utilizes the parasitic capacitance c between its grid and the source electrode
10Carry out charge storage; (15) NMOS pipe M42: drain electrode is connected with the drain electrode of M43, and grid is connected with the grid of M41; (16) NMOS pipe M43: drain electrode is connected with grid, and drain electrode also is connected with the drain electrode of M42, and grid is connected with the grid of M44; (17) NMOS pipe M44: drain electrode is connected with the drain electrode of M28 and M38 simultaneously, and grid is connected with drain electrode with the grid of M43.
As shown in Figure 1, described switching current single order economize on electricity road adopts mode in parallel to be connected with two switching current single order economize on electricity roads, the input on switching current single order economize on electricity road (
i In1) and the input on two switching current second orders economize on electricity roads (
i In2With
i In3) connect three current signal output ends (i.e. the drain electrode of NMOS among figure pipe M4, M5 and M6) of input current copy cell respectively, the output on described switching current single order economize on electricity road (
i Out1) and the output on two switching current second orders economize on electricity roads (
i Out2With
i Out3) directly link together realize output current signal phase adduction as the output of whole filter circuit (
i Out).
As shown in Figure 1, the switch in the circuit on described switching current single order economize on electricity road and second order economize on electricity road is controlled the sequential of clock signal as shown in Figure 2, among the figure by the non-overlapped clock signal control of two-phase
φ 1Mutually and
φ 2Be the non-overlapped signal of two-phase mutually, when certain is high level mutually, the switch opens of controlling, when certain was low level mutually, the switch of controlling then cut out, and T represents the cycle of clock signal among the figure, and n represents the numbering of clock cycle.
As shown in Figure 1, the parameter on described switching current single order economize on electricity road and second order economize on electricity road realizes that by the breadth length ratio (W/L) that the NMOS pipe is set NMOS pipe title, corresponding parameters and parameter value thereof are listed table 1 respectively in.
Table 1: current-mode five rank Marr wavelet filter circuit parameters
[0026]In order to verify the performance of designed current-mode five rank Marr wavelet filter circuit, adopt ASIZ switching current simulation software to carry out emulation here.Emulation arranges: the input stimulus electric current of circuit is 1uA, and output resistance is 1 Ω, and the switch clock frequency is 20Hz.The circuit impulse response simulation waveform that obtains as shown in Figure 3.Contrast Marr small echo ideal waveform as shown in Figure 2, designed as can be known current-mode five rank Marr wavelet filter circuit workings are normal, and overall performance is outstanding, approaches the effective of desirable Marr small echo.
The pole-zero plot of the current-mode five rank Marr wavelet filter circuit of design as shown in Figure 4, visible all limits are positioned at unit circle, therefore, designed current-mode five rank Marr wavelet filter circuit are stable.
Comprehensive above-mentioned simulation result and the analysis showed that the beneficial effects of the utility model are: 1, a kind of current-mode five rank Marr wavelet filter circuit are provided, and the circuit overall performance is outstanding, approaches the effective of desirable Marr small echo.The single order economize on electricity road of 2, adopting and biquadratic economize on electricity road have desirable parameter, and the one, circuit parameter is few, and single order economize on electricity road has only two parameters, and second order economize on electricity road has only four parameters; The 2nd, the circuit parameter size is homogeneous comparatively, is beneficial to the circuit layout design.
Claims (3)
1. current-mode five rank Marr wavelet filter circuit, it comprises: an input current copy cell, a switching current single order economize on electricity road and two switching current second order economize on electricity roads, described switching current single order economize on electricity road adopts mode in parallel to be connected with two switching current second order economize on electricity roads, switching current single order economize on electricity road and the input on switching current second order economize on electricity road are connected three current signal output ends of input current copy cell respectively, the output on switching current single order economize on electricity road and switching current second order economize on electricity road links together and realizes output current signal addition and output, and the impulse response waveform of circuit output is similar to desirable Marr small echo.
2. according to the described current-mode five rank Marr wavelet filter circuit of claim 1, it is characterized in that: described switching current single order economize on electricity road adopts 4 switches, 4 N-type metal-oxide-semiconductors (NMOS) and bias current sources thereof to form, input connects the output of input current copy cell, and the output on output and switching current second order economize on electricity road links together and realizes output current signal addition and output; 4 switches that adopt on described switching current single order economize on electricity road are by two-phase non-overlapping clock signal controlling, switch opens when clock signal is high level, and switch cut out when clock signal was low level; Described switching current single order economize on electricity road uses the grid-source parasitic capacitance of 2 N-type metal-oxide-semiconductors (NMOS); 4 N-type metal-oxide-semiconductors (NMOS) in the described switching current single order economize on electricity road, wherein 2 breadth length ratios (W/L) are 1, other 2 breadth length ratios (W/L) are respectively 1.3550 and 0.9540.
3. according to the described current-mode five rank Marr wavelet filter circuit of claim 1, it is characterized in that: described switching current second order economize on electricity road adopts 8 switches, 17 N-type metal-oxide-semiconductors (NMOS) and bias current sources thereof to form, input connects the output of input current copy cell, and the output on output and switching current single order economize on electricity road links together and realizes output current signal addition and output; 8 switches that adopt on described switching current second order economize on electricity road are by two-phase non-overlapping clock signal controlling, switch opens when clock signal is high level, and switch cut out when clock signal was low level; Described switching current second order economize on electricity road uses the grid-source parasitic capacitance of 4 N-type metal-oxide-semiconductors (NMOS); 17 N-type metal-oxide-semiconductors (NMOS) in first switching current second order economize on electricity road, wherein 13 breadth length ratio (W/L) is 1, other 4 breadth length ratio (W/L) is respectively 0.9084,0.9686,1.9580 and 0.9686; 17 N-type metal-oxide-semiconductors (NMOS) in second switching current second order economize on electricity road, wherein 13 breadth length ratio (W/L) is 1, other 4 breadth length ratio (W/L) is respectively 0.2659,0.1446,1.9613 and 0.9651.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104333347A (en) * | 2014-10-14 | 2015-02-04 | 北京交通大学 | Switching current Gauss low-pass filter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104333347A (en) * | 2014-10-14 | 2015-02-04 | 北京交通大学 | Switching current Gauss low-pass filter |
| CN104333347B (en) * | 2014-10-14 | 2017-07-04 | 北京交通大学 | A kind of switching current gauss low frequency filter |
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