CN203301433U - Direct current gain-increasing direct current offset-decreasing low-pass filter with clock scanning capability - Google Patents
Direct current gain-increasing direct current offset-decreasing low-pass filter with clock scanning capability Download PDFInfo
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- CN203301433U CN203301433U CN2013200668610U CN201320066861U CN203301433U CN 203301433 U CN203301433 U CN 203301433U CN 2013200668610 U CN2013200668610 U CN 2013200668610U CN 201320066861 U CN201320066861 U CN 201320066861U CN 203301433 U CN203301433 U CN 203301433U
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Abstract
A direct current gain-increasing direct current offset-decreasing low-pass filter with a clock scanning capability is provided. The direct current gain-increasing direct current offset-decreasing low-pass filter with the clock scanning capability includes an operational amplifier with a resistor (or switched capacitor). According to the filter, an input end of the operational amplifier is connected with a signal input port; a first capacitor provides a first feedback loop between the output and the input of the operational amplifier; and an active network is in serial connection with another resistor (or switched capacitor) so as to form as a filtering feedback loop.
Description
Technical field
Present invention generally relates to the filter circuit of low pass electricity consumption, and more particularly the present invention relates to switch electricity low pass filter and utilize an active network to improve to obtain and roll-off and the accuracy of DC current gain.The resistance that passive low ventilating filter forms and the element of electric capacity present a kind of acquisition and have important function of roll-offing, and the function that the composition that namely filters out high-frequency signal is used as a frequency occurs usually.Active filter, or filter includes derived components, improves the flatness of passive circuit passband and DC current gain is provided, but can be introduced in the direct current offset mistake that output signal occurs.As shown in Figure 1, in fact this filter comprises the shunting capacitance element series connection of a switched capacitor network and a passive low ventilating filter.In order to obtain the planar network of a maximum, the cut-off frequency of this low pass filter should be closely related with outside RC element, or
Background technology
Of the present invention one to as if active low-pass filter, this dc offset only depends on the side-play amount of being introduced by input operational amplifier.Of the present invention another to as if an active low pass filter, can realize the equivalent electric circuit of a switched capacitor, this circuit is swept out and can keeps the DC current gain precision in a single clock frequency.Also have one of the present invention to as if an active low-pass filter, the time constant of the input circuit of this filter can be combined with the low pass filter that the co-factor of source network has calculated a full limit of needs.Briefly, according to the present invention, an active network is placed on the feedback loop of an operational amplifier, and namely the direct current output offset only depends on the input offset of this operational amplifier.The resistance of external passive and capacity cell can be revised as the equivalent electric circuit of switching capacity at an easy rate to active network,, keeping DC current gain accurately in situation, thereby can scan whole circuit with a single clock frequency accordingly, change the cut-off frequency of filter.In addition, non-essential resistance and capacity cell can be combined with the coefficient of source network and complete Bezier, Butterworth, chebyshev function or other full pole lowpass function.The drawing that the present invention and object and characteristics thereof are taked according to following detailed description with when the accessory claim will be more obvious.
Summary of the invention
the invention provides a kind of clock with increase DC current gain and minimizing direct current offset has the low pass filter of scan capability, operational amplifier has the first order and second level input and output, first resistance device couples together a single input signal end and above-mentioned first input, earthing device is above-mentioned second input, capacitive means allows above-mentioned output and above-mentioned first input connect each other, the network of an active low-pass filter has an input and an output, above-mentioned low-pass filter network comprises that has an all-pole filter that has translation function on the part basis of above-mentioned first resistance device, the device of above-mentioned electric capacity, device with second electric capacity, these devices are connected with the above-mentioned input of the above-mentioned active filter network that has above-mentioned operational amplifier output terminal, above-mentioned second resistor device is connected first input of the output of above-mentioned active filter and above-mentioned operational amplifier.
The invention provides a kind of clock with increase DC current gain and minimizing direct current offset has the low pass filter of scan capability, and wherein above-mentioned first resistance device and second resistor device comprise switched capacitor and the active power filtering network that has switched capacitor.
the invention provides a kind of clock with increase DC current gain and minimizing direct current offset has the low pass filter of scan capability, a filter circuit comprises that an operational amplifier has the first order and second level input and output, the device of first electric capacity is connected between above-mentioned first input and output, an active switched capacitor filter network has an input and an output, these devices are connected to above-mentioned active switched capacitor filter network to above-mentioned input and are connected to the output of above-mentioned that operational amplifier, second capacitive means has first and second port, first switching device is for above-mentioned second capacitive means of the change that replaces above-mentioned first port between a switching capacity filter network, second switching device for above-mentioned second capacitive means of the change that replaces at first input of above-mentioned operational amplifier and above-mentioned second port between earth terminal, wherein above-mentioned second capacitive means comprises first and second capacitor that has separately first and second port, the port above-mentioned first and second capacitor that above-mentioned first switching device replaces is connected to the output of a signal input part and above-mentioned active switched capacitor filter network, and above-mentioned second switching device replaces is connected to above-mentioned first and second electric capacity port first input and the earth terminal of above-mentioned operational amplifier.
Documents, utility model patent: low pass filter, application number: 200920277860.4
Description of drawings
Fig. 1 is the bypass network that the FBD (function block diagram) of a low pass filter comprises a switching capacity.
Fig. 2 be one according to functions of low-pass filter piece figure of the present invention
Fig. 3 is the schematic diagram that a Fig. 2 utilizes the low pass filter of switching capacity element
Fig. 4 is the another kind of schematic diagram that embodies of low pass filter that a Fig. 2 uses the switching capacity element
Fig. 5 is the schematic diagram that a Fig. 2 uses another embodiment of low pass filter of switching capacity element
Embodiment
Fig. 1 is the schematic diagram of a low pass filter, and as shown in the figure, switched capacitor network 5 is that one of a conduct with the capacitor C series connection shunts to ground and provides communication channel to the high-frequency signal element that filters.DC path is from being input to output by resistance R.The collaborative clock of switched capacitor network is controlled by outside or internal clocking.
Fig. 2 is a schematic diagram according to low pass filter of the present invention, and this is desired to make money or profit with an active network 10 in the feedback loop of operational amplifier 12.Input voltage V
inBe to provide by the input of resistance R 1 to operational amplifier 12, and DC voltage offset is applied to other input of operational amplifier by the explanation of figure tabular form.The feedback loop of this operational amplifier comprises that a capacitor C and a resistance R 2 minutes were separately the terminals of linking active network.
For a direct current signal, the impedance of capacitor C is unlimited, and if the DC current gain of supposition operational amplifier is also unlimited, the output of gain is so
(filter DC current gain).The direct current offset of output only depends on the skew of operational amplifier, offset voltage, and this does not depend on the direct current offset of active network inner ring road.The total drift amount is
Exchange row considering, if for the transfer function of active network be
Then the entire gain of circuit is
Here s=jw, T=R
2C, it can
The middle embodiment.Consider a present full limit (Butterworth, Chebyshev, Bezier) low pass filter.If the transfer function of active network is
The normalized transfer function of a full pole lowpass filter is
The transfer function of Fig. 2 circuit is at R
2=R
1The time be formula
Between (1) and (2)
ω
realb
o＝Co ω
real＝Co/C1
b
n-2＝C
n-1 b
n-2＝C
n-1
b
n-3＝C
n-2 b
n-3＝C
n-2
· ·
· ·
b
0＝C1 b
0＝C1
Be considered as being equal to.
As can be seen from the above, method is flat-footed, and what all need to be done is to design an active low-pass network, and its function is:
The circuit of above-mentioned Fig. 2, active network according to the present invention is placed between direct current and ac circuit.For direct current, the open-loop gain that operational amplifier is very high forces the direct current offset of output only to depend on the internal blas of operational amplifier.In addition, the DC current gain of circuit is forced to the DC current gain that is independent of active network.When the function of circuit required be a traditional higher order pole low pass filter, the design of inner active network is conventional program.Because the input link of Fig. 2 amplifier is an inverting amplifier, integrator, resistance and capacitor can be made with switched capacitor technique, as shown in Figure 3.In addition, internal network can comprise switched-capacitor circuit.A clock is driving integrated and the internal switch capacitance network, and namely a single clock can scan whole circuit.In the circuit of Fig. 3, the port of a capacitor C 1 replaces between input and earth terminal switching, other port of two capacitor C 1 switches between an input of earth terminal and operational amplifier 12.The resistive element R2 of Fig. 2 circuit the substitute is a switching capacity C2, this element is replaced between feedback loop and earth terminal switching.For unified DC current gain, C1=C2 and DC current gain are expressed as C1/C2 ± capacitance tolerance.Input switched capacitor C1 is that the inverted integrated straight flow enhancement that makes is noninverting.
The switching capacity C1 of Fig. 3 is the function of resistance R 1 and resistance R 2 in execution graph 2 how, and as shown in Figure 4, one is significantly improved, and the circuit that utilizes Fig. 4 is the unification of the DC current gain of whole filter.
Fig. 5 is the another kind embodiment of Fig. 2 circuit and is the more perfect embodiment of Fig. 4 circuit.This is embodied in a large amount of time, and whole loop is open, and it is minimized utilizing a dual handover scheme, utilizes two capacitors (C/2) to replace the single capacitor of Fig. 4 (C1).Here by several embodiment of an active low-pass filter, described, direct current offset only depends on the skew that an operational amplifier is introduced.This filter can realize as a switching capacity or its equivalent electric circuit, and this circuit can be scanned and keep the DC current gain precision in single clock frequency.Time constant can evolve in conjunction with the coefficient of high-order multiple filter.
Claims (3)
1. one kind has the clock that increases DC current gain and reduce direct current offset the low pass filter of scan capability is arranged, it is characterized in that: operational amplifier has the first order and second level input and output, first resistance device couples together a single input signal end and above-mentioned first input, earthing device is above-mentioned second input, capacitive means allows above-mentioned output and above-mentioned first input connect each other, the network of an active low-pass filter has an input and an output, above-mentioned low-pass filter network comprises that has an all-pole filter that has translation function on the part basis of above-mentioned first resistance device, the device of above-mentioned electric capacity, device with second electric capacity, these devices are connected with the above-mentioned input of the above-mentioned active filter network that has above-mentioned operational amplifier output terminal, above-mentioned second resistor device is connected first input of the output of above-mentioned active filter and above-mentioned operational amplifier.
2. the clock with increase DC current gain and minimizing direct current offset according to claim 1 has the low pass filter of scan capability, and it is characterized in that: wherein above-mentioned first resistance device and second resistor device comprise switched capacitor and the active power filtering network that has switched capacitor.
3. the clock with increase DC current gain and minimizing direct current offset according to claim 1 has the low pass filter of scan capability, it is characterized in that:
a filter circuit comprises that an operational amplifier has the first order and second level input and output, the device of first electric capacity is connected between above-mentioned first input and output, an active switched capacitor filter network has an input and an output, these devices are connected to above-mentioned active switched capacitor filter network to above-mentioned input and are connected to the output of above-mentioned that operational amplifier, second capacitive means has first and second port, first switching device is for above-mentioned second capacitive means of the change that replaces above-mentioned first port between a switching capacity filter network, second switching device for above-mentioned second capacitive means of the change that replaces at first input of above-mentioned operational amplifier and above-mentioned second port between earth terminal, wherein above-mentioned second capacitive means comprises first and second capacitor that has separately first and second port, the port above-mentioned first and second capacitor that above-mentioned first switching device replaces is connected to the output of a signal input part and above-mentioned active switched capacitor filter network, and above-mentioned second switching device replaces is connected to above-mentioned first and second electric capacity port first input and the earth terminal of above-mentioned operational amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013200668610U CN203301433U (en) | 2013-02-06 | 2013-02-06 | Direct current gain-increasing direct current offset-decreasing low-pass filter with clock scanning capability |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013200668610U CN203301433U (en) | 2013-02-06 | 2013-02-06 | Direct current gain-increasing direct current offset-decreasing low-pass filter with clock scanning capability |
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| Publication Number | Publication Date |
|---|---|
| CN203301433U true CN203301433U (en) | 2013-11-20 |
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|---|---|---|---|
| CN2013200668610U Expired - Fee Related CN203301433U (en) | 2013-02-06 | 2013-02-06 | Direct current gain-increasing direct current offset-decreasing low-pass filter with clock scanning capability |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103354446A (en) * | 2013-02-06 | 2013-10-16 | 苏州硅智源微电子有限公司 | Low-pass filter provided with clock capable of increasing DC gain and decreasing DC offset and ability of scanning |
| CN113884659A (en) * | 2021-09-08 | 2022-01-04 | 中国航空工业集团公司西安航空计算技术研究所 | Lubricating oil metal chip parameter detection method |
-
2013
- 2013-02-06 CN CN2013200668610U patent/CN203301433U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103354446A (en) * | 2013-02-06 | 2013-10-16 | 苏州硅智源微电子有限公司 | Low-pass filter provided with clock capable of increasing DC gain and decreasing DC offset and ability of scanning |
| CN113884659A (en) * | 2021-09-08 | 2022-01-04 | 中国航空工业集团公司西安航空计算技术研究所 | Lubricating oil metal chip parameter detection method |
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Granted publication date: 20131120 Termination date: 20140206 |