CN103957004A - Phase-locked loop filter circuit applied to direct transmitter - Google Patents
Phase-locked loop filter circuit applied to direct transmitter Download PDFInfo
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- CN103957004A CN103957004A CN201410150770.4A CN201410150770A CN103957004A CN 103957004 A CN103957004 A CN 103957004A CN 201410150770 A CN201410150770 A CN 201410150770A CN 103957004 A CN103957004 A CN 103957004A
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Abstract
The invention discloses a phase-locked loop filter circuit applied to a direct transmitter. The phase-locked loop filter circuit comprises CMOS transmission gates S1, S2 and S3, a unity gain amplifier A1, a VFD node voltage generation circuit P1 and a main filter circuit P2, wherein the right end of the S1 is respectively connected with the right end of the S2 and the right end of the S3, the left end of the S1 is connected with output currents ICP of a module charge pump in a phase-locked loop, the right end of the S2 is connected with a node A, the left end of the S3 is connected with a node VFD, the input end of the A1 is connected with the node A, the output end of the A1 is connected with the node VFD of the P1, the left end of the P2 is connected with the node A, and the right end of the P2 is connected with output VOUT. The phase-locked loop filter circuit has the advantages that instead of a traditional structure that a large loop capacitor is needed, the discharge path of a loop filter is ingeniously cut off because of the design structure so that the purpose of stabilizing loop voltage can be achieved, and therefore the integration level of chips is improved and cost is reduced.
Description
Technical field
The present invention relates to a kind of cycle of phase-locked loop filter circuit, particularly a kind of cycle of phase-locked loop filter circuit that is applied to direct transmitter.
Background technology
Along with the fast development of the fast development of wireless communication field, particularly handheld device, radio frequency integrated circuit is to low volume, high integration, and the requirement of low-power consumption is more and more higher.For transmitter, adopt the structure of direct modulation voltage controlled oscillator to be undoubtedly the first-selection of handheld device, because it has functional module, quantity is few, advantage low in energy consumption, but directly transmitter need to be the in the situation that of phase-locked loop open loop transmitting data, this just requires cycle of phase-locked loop filter loop voltage to be maintained to a period of time in phase-locked loop open loop to meet the requirement of data transmission.
As shown in Figure 1, it is to reach by large electric capacity the object that maintains loop voltage to traditional cycle of phase-locked loop filter circuit for direct transmitter, closes at phase-locked loop locked stage switch; When phase-locked loop locks onto after the frequency needing, switch opens, reaches by the large electric capacity after switch the object that maintains transmitting data required voltage.But this electric capacity needs tens nF conventionally, and so large electric capacity cannot be integrated on sheet, can only use the outer electric capacity of sheet, and this will reduce the integrated level of chip greatly, and can increase cost simultaneously.
Summary of the invention
The object of this invention is to provide a kind of cycle of phase-locked loop filter circuit that can be applicable to direct transmitter, to overcome the deficiency of mentioning in above-mentioned background technology.
For achieving the above object, the present invention is achieved through the following technical solutions:
A cycle of phase-locked loop filter circuit that is applied to direct transmitter, comprises cmos transmission gate S1, S2, S3, unity gain amplifier A1, and VFD node voltage produces circuit P1, and main filter circuit P2; Wherein the right-hand member of transmission gate S1 is connected with the left end of transmission gate S2, the right-hand member of transmission gate S3 respectively, and the left end of transmission gate S1 is connected with the output current ICP of the Modular charge pump in phase-locked loop; The right-hand member of transmission gate S2 is connected with node A; The left end of transmission gate S3 is connected with node VFD; The input of unity gain amplifier A1 is connected with node A, and the output of unity gain amplifier A1 is connected with the node VFD that VFD node voltage produces circuit P1; The left end of main filter circuit P2 is connected with node A, and right-hand member is connected with output VOUT.
Described transmission gate S1 leaks by source the mode interconnecting by a nmos pass transistor M4 and a PMOS transistor M3 and forms, the substrate of nmos pass transistor M4 is connected with ground GND, the grid of nmos pass transistor M4 are connected with SP, the substrate of PMOS transistor M3 is connected with power vd D, and the grid of PMOS transistor M3 are connected with SN.
Described transmission gate S2 leaks by source the mode interconnecting by a nmos pass transistor M6 and a PMOS transistor M5 and forms, the substrate of nmos pass transistor M6 is connected with node VL, the grid of nmos pass transistor M6 are connected with SP, the substrate of PMOS transistor M5 is connected with node VH, and the grid of PMOS transistor M5 are connected with SN.
Described transmission gate S3 leaks by source the mode interconnecting by a nmos pass transistor M8 and a PMOS transistor M7 and forms, the substrate of nmos pass transistor M8 is connected with ground GND, the grid of nmos pass transistor M8 are connected with SP, the substrate of PMOS transistor M7 is connected with power vd D, and the grid of PMOS transistor M7 are connected with SN.
Described VFD node voltage produces circuit P1 and comprises PMOS transistor M1, nmos pass transistor M2, resistance R 4, R5; Wherein the substrate of PMOS transistor M1 is connected with source and power vd D, and the grid of PMOS transistor M1 are connected with VBIAS, and the leakage of PMOS transistor M1 is connected with node VH, further, between node VH and node VFD, is connected with resistance R 4; The substrate of nmos pass transistor M2 is connected with source and ground GND, and the grid of nmos pass transistor M2 are connected with VBIAS, and the leakage of nmos pass transistor M2 is connected with node VL, further, between node VL and node VFD, is connected with resistance R 5.
Described main filter circuit P2 comprises resistance R 1, R3, capacitor C 1, C2, C3, and unity gain amplifier A2; Wherein the upper end of resistance R 1 is connected with node A, and the lower end of resistance R 1 is connected with the upper end of capacitor C 1, and the lower end of capacitor C 1 is connected with ground GND; Between node A and ground GND, be connected with capacitor C 2; The input of unity gain amplifier A2 is connected with node A, between the output of unity gain amplifier A2 and output VOUT, is connected with resistance R 3; Between output VOUT and ground GND, be connected with capacitor C 3.
The present invention utilizes switch to carry out the mode of operation of switching filter, and in the time being operated in cycle of phase-locked loop locking mode, loop filter of the present invention is equivalent to passive three rank filters; In the time being operated in loop voltage and maintaining pattern, reach by cutting off the discharge path that in circuit of the present invention, A is ordered the object that voltage maintains.Different from traditional implementation, the present invention utilizes cut-out discharge path to maintain loop voltage, instead of extends discharge time by excessive electric capacity, thus do not need large electric capacity, therefore can Embedded.
The beneficial effect of the cycle of phase-locked loop filter circuit that is applied to direct transmitter of the present invention is: the design's structure has been cut off the discharge path of loop filter cleverly, reach with this object of stablizing loop voltage, and unlike traditional structure, need large loop capacitance, therefore the integrated level that has improved chip, has reduced cost.
Brief description of the drawings
Fig. 1 is traditional cycle of phase-locked loop filter circuit configuration schematic diagram for direct transmitter;
Fig. 2 is the cycle of phase-locked loop filter circuit configuration schematic diagram that the present invention is applied to direct transmitter;
Fig. 3 be circuit of the present invention in phase-locked loop operation the equivalent circuit diagram under normal lock state.
Embodiment
As shown in Figure 2, be the cycle of phase-locked loop filter circuit configuration schematic diagram that the present invention is applied to direct transmitter.The course of work of the present invention is as follows:
First, when cycle of phase-locked loop is operated in normal lock state, configuration SP=" 1 ", SN=" 0 ", makes loop filter of the present invention be operated in normal filter state.At this moment transmission gate S1, transmission gate S2 conducting, transmission gate S3 closes, from the output current ICP of the charge pump module in phase-locked loop, by transmission gate S1, transmission gate S2, arrive A point, with capacitor C 1, capacitor C 2, resistance R 1 forms voltage together, this voltage is by after unity gain amplifier A2, arrive resistance R 3, after the low pass filter filtering that resistance R 3 and capacitor C 3 form, form output VOUT, because the unity gain amplifier A2 in this path does not affect the gain of transmission, also can ignore the phase effect of transmission by rational circuit design unity gain amplifier A2, therefore when phase-locked loop operation is during in normal lock state, circuit of the present invention can be equivalent to the passive three rank filters shown in Fig. 3.
Then, in the time of transmitter transmitting data, require phase-locked loop operation in loop off-state, and require the voltage on loop filter to be maintained, at this moment, configuration SP=" 0 ", SN=" 1 ", makes loop filter of the present invention be operated in voltage and maintains state.Now, transmission gate S1, transmission gate S2 closes, and transmission gate S3 conducting, now exports VOUT, node VFD, the voltage of these three points of node A equates.The present invention utilizes the mode of cutting off the A discharge path of order to reach the object of the stable VOUT of output voltage.Have with node A is direct-connected: the right-hand member of transmission gate S2, the input of unity gain amplifier A1, the input of unity gain amplifier A2, resistance R 1 and capacitor C 2.Due to unity gain amplifier A1 and unity gain amplifier A2 be input as the transistorized grid of CMOS, therefore it does not have effective discharge path; In capacitor C 2, there is no effective discharge path yet; What connect below due to resistance R 1 is capacitor C 1, and therefore resistance R 1 can not form effective discharge path.So the discharge path of voltage only has the right-hand member of transmission gate S2, and the electric discharge of transmission gate S2 right-hand member is to complete by the discharging current of its parasitic diode, comprises the parasitic diode between horizontal source leakage, and the diode between substrate is leaked in longitudinal source.The present invention by design cleverly, the source of transmission gate S2 is leaked and the voltage of substrate equates to reach the object of cutting off discharging current.The voltage of ordering as A in Fig. 2 equates with the voltage of VFD, and the voltage approximately equal of the voltage of VH and VL and VFD, (when design, flow through the very little 10uA of the electric current left and right of PMOS transistor M1 and nmos pass transistor M2, and resistance R 4, R5 also only have 100 ohm of left and right, so the voltage difference of VH and VL and VFD only has 1mV left and right), so all discharge paths are all cut off, electric leakage can be ignored, the voltage of node A will effectively be maintained, and the voltage that output VOUT is ordered also effectively maintained.
Claims (6)
1. a cycle of phase-locked loop filter circuit that is applied to direct transmitter, is characterized in that: comprise cmos transmission gate S1, S2, S3, and unity gain amplifier A1, VFD node voltage produces circuit P1, and main filter circuit P2; Wherein the right-hand member of transmission gate S1 is connected with the left end of transmission gate S2, the right-hand member of transmission gate S3 respectively, and the left end of transmission gate S1 is connected with the output current ICP of the Modular charge pump in phase-locked loop; The right-hand member of transmission gate S2 is connected with node A; The left end of transmission gate S3 is connected with node VFD; The input of unity gain amplifier A1 is connected with node A, and the output of unity gain amplifier A1 is connected with the node VFD that VFD node voltage produces circuit P1; The left end of main filter circuit P2 is connected with node A, and right-hand member is connected with output VOUT.
2. the cycle of phase-locked loop filter circuit that is applied to direct transmitter as claimed in claim 1, it is characterized in that: described transmission gate S1 leaks by source the mode interconnecting by a nmos pass transistor M4 and a PMOS transistor M3 and forms, the substrate of nmos pass transistor M4 is connected with ground GND, the grid of nmos pass transistor M4 are connected with SP, the substrate of PMOS transistor M3 is connected with power vd D, and the grid of PMOS transistor M3 are connected with SN.
3. the cycle of phase-locked loop filter circuit that is applied to direct transmitter as claimed in claim 1, it is characterized in that: described transmission gate S2 leaks by source the mode interconnecting by a nmos pass transistor M6 and a PMOS transistor M5 and forms, the substrate of nmos pass transistor M6 is connected with node VL, the grid of nmos pass transistor M6 are connected with SP, the substrate of PMOS transistor M5 is connected with node VH, and the grid of PMOS transistor M5 are connected with SN.
4. the cycle of phase-locked loop filter circuit that is applied to direct transmitter as claimed in claim 1, it is characterized in that: described transmission gate S3 leaks by source the mode interconnecting by a nmos pass transistor M8 and a PMOS transistor M7 and forms, the substrate of nmos pass transistor M8 is connected with ground GND, the grid of nmos pass transistor M8 are connected with SP, the substrate of PMOS transistor M7 is connected with power vd D, and the grid of PMOS transistor M7 are connected with SN.
5. the cycle of phase-locked loop filter circuit that is applied to direct transmitter as claimed in claim 1, is characterized in that: described VFD node voltage produces circuit P1 and comprises PMOS transistor M1, nmos pass transistor M2, resistance R 4, R5; Wherein the substrate of PMOS transistor M1 is connected with source and power vd D, and the grid of PMOS transistor M1 are connected with VBIAS, and the leakage of PMOS transistor M1 is connected with node VH, further, between node VH and node VFD, is connected with resistance R 4; The substrate of nmos pass transistor M2 is connected with source and ground GND, and the grid of nmos pass transistor M2 are connected with VBIAS, and the leakage of nmos pass transistor M2 is connected with node VL, further, between node VL and node VFD, is connected with resistance R 5.
6. the cycle of phase-locked loop filter circuit of direct transmitter as claimed in claim 1, is characterized in that: described main filter circuit P2 comprises resistance R 1, R3, capacitor C 1, C2, C3 and unity gain amplifier A2; Wherein the upper end of resistance R 1 is connected with node A, and the lower end of resistance R 1 is connected with the upper end of capacitor C 1, and the lower end of capacitor C 1 is connected with ground GND; Between node A and ground GND, be connected with capacitor C 2; The input of unity gain amplifier A2 is connected with node A, between the output of unity gain amplifier A2 and output VOUT, is connected with resistance R 3; Between output VOUT and ground GND, be connected with capacitor C 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410150770.4A CN103957004A (en) | 2014-04-16 | 2014-04-16 | Phase-locked loop filter circuit applied to direct transmitter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410150770.4A CN103957004A (en) | 2014-04-16 | 2014-04-16 | Phase-locked loop filter circuit applied to direct transmitter |
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| CN103957004A true CN103957004A (en) | 2014-07-30 |
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| CN201410150770.4A Pending CN103957004A (en) | 2014-04-16 | 2014-04-16 | Phase-locked loop filter circuit applied to direct transmitter |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105207669A (en) * | 2015-08-19 | 2015-12-30 | 深圳市海能达通信有限公司 | Method and circuit for reducing frequency source locking time |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1236225A (en) * | 1998-03-26 | 1999-11-24 | 日本电气株式会社 | Charge pump circuit for PLL |
| CN1578152A (en) * | 2003-06-27 | 2005-02-09 | 松下电器产业株式会社 | Low-pass filter and feedback system |
| CN101409554A (en) * | 2007-10-11 | 2009-04-15 | 北京朗波芯微技术有限公司 | Loop filter circuit for charge pump phase-locked loop |
| CN102739173A (en) * | 2012-06-21 | 2012-10-17 | 中国科学院微电子研究所 | Transconductance amplifier, resistor, inductor and filter |
| CN203761369U (en) * | 2014-04-16 | 2014-08-06 | 中科芯集成电路股份有限公司 | Phase-lock loop filter circuit applied to direct transmitter |
-
2014
- 2014-04-16 CN CN201410150770.4A patent/CN103957004A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1236225A (en) * | 1998-03-26 | 1999-11-24 | 日本电气株式会社 | Charge pump circuit for PLL |
| CN1578152A (en) * | 2003-06-27 | 2005-02-09 | 松下电器产业株式会社 | Low-pass filter and feedback system |
| CN101409554A (en) * | 2007-10-11 | 2009-04-15 | 北京朗波芯微技术有限公司 | Loop filter circuit for charge pump phase-locked loop |
| CN102739173A (en) * | 2012-06-21 | 2012-10-17 | 中国科学院微电子研究所 | Transconductance amplifier, resistor, inductor and filter |
| CN203761369U (en) * | 2014-04-16 | 2014-08-06 | 中科芯集成电路股份有限公司 | Phase-lock loop filter circuit applied to direct transmitter |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105207669A (en) * | 2015-08-19 | 2015-12-30 | 深圳市海能达通信有限公司 | Method and circuit for reducing frequency source locking time |
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Application publication date: 20140730 |