CN101692607A - High stability clock circuit for passive high-frequency radio frequency identification chip - Google Patents
High stability clock circuit for passive high-frequency radio frequency identification chip Download PDFInfo
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- CN101692607A CN101692607A CN200910023889A CN200910023889A CN101692607A CN 101692607 A CN101692607 A CN 101692607A CN 200910023889 A CN200910023889 A CN 200910023889A CN 200910023889 A CN200910023889 A CN 200910023889A CN 101692607 A CN101692607 A CN 101692607A
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Abstract
The invention discloses a high stability clock circuit for a passive high-frequency radio frequency identification chip, aiming to solve the problems of large jitter and high temperature-drift of the existing clock circuit. The high stability clock circuit of the invention comprises a group of current mirror clock calibration circuit (301), two inverters (302,303), two comparators (304,305), two RS triggers (306,307) and two phase inverters (308,309); the two inverters, two comparators and two RS triggers compose two oscillator circuits, a resistor R' for generating comparative level and a delay capacitor C3 are connected with the inverting output ends of the two comparators and the ground, a positive temperature coefficient N-well resistor R1 is in series with a negative temperature coefficient high resistance polysilicon resistor R2 for compensating the resistance of the resistor so as to inhibit the clock temperature-drift; the capacitance of the capacitor is half of the charge-discharge capacitance to realize 1/4 delay period of the comparative level and inhibit the clock jitter caused by the fluctuation of current. The clock generated by the clock circuit of the invention has the advantage of highly stable frequency for the out clock and can be used in the integrated circuit.
Description
Technical field
The invention belongs to microelectronics technology, relate to integrated circuit (IC) design, particularly a kind of clock generation circuit is used for passive ultra-high frequency radio-frequency (RF) identification (UHF RFID) chip etc. and has the integrated circuit (IC) system of independent clock generation module.
Background technology
In recent years, the radio frequency discrimination RFID technology is because its wide application prospect develops very rapid.Rfid system generally includes electronic tag, read write line and three major parts of data management system and constitutes.Electronic tag is made up of antenna and RFID chip, and each chip-stored the relevant information of its object that identifies; Read write line reads or writes the information in the RFID chip, and by networking and other computers or system communication, finish to the information of RFID chip obtain, explanation and data management.Passive UHF RFID uses the carrier frequency of 860～960MHz, Fig. 1 is read write line and electronic tag communication figure, the RFID chip obtains energy by antenna from read write line, electrifying startup work, receive the data that read write line sends over, and, finish the communication between electronic tag and the read write line to read write line backscattering data.
Passive UHF RFID chip is made of AFE (analog front end), digital baseband and memory, and Fig. 2 is AFE (analog front end) and digital baseband structured flowchart.The standard of ISO does not support that label chip recovers to extract clock from eat dishes without rice or wine at present, can only provide specific clock frequency for digital baseband work by the clock module circuit of AFE (analog front end).Antenna component is exported to the certain voltage of power management module from the read write line received energy by charge pump, and the power management module circuit provides operating voltage VDD for the clock module circuit and with reference to input current I.When not having transfer of data between RFID chip and the read write line, the energy of acquisition is horizontal fixed, and power management module output voltage V DD and electric current I be fluctuation not; When read write line when chip sends data or chip modulation reflectance data, the energy that chip obtains has very big fluctuation, power management module output voltage V DD and electric current I produce very great fluctuation process; And, cause the very big deviation of VDD and I owing to the influence of chip with the far and near different and technology of the operating distance of reader.
For passive UHF rfid system, clock circuit the output clock frequency and operating voltage VDD or relevant generally used both at home and abroad at present with reference to input current I, it is all very big therefore to export clock frequency shake and deviation, makes digital baseband reliablely and stablely not work.People such as F.Cilek propose ring oscillator in Ultra Low Power Oscillatorfor UHF RFID Transponder article, sort circuit structure output clock frequency is directly proportional with electric current I, is inversely proportional to VDD.When electric current I or voltage VDD existence fluctuation or deviation, very big shake and deviation appear in the output clock frequency, and clock frequency temperature coefficient at normal temperatures is very big.
Ray Barnett and Jin Liu propose relaxation osillator at A 0.8V 1.52MHz MSVC Relaxation Oscillator withInverted Mirror Feedback Reference for UHF RFID, the output clock frequency is the minorant of electric current I, shake reduces to some extent, but fundamentally do not solving the problem that clock frequency is shaken with the operating current fluctuation, and clock frequency with variation of temperature deviation appears.
The defective of clock generation circuit that is applicable to passive UHF RFID chip at present is as follows:
1. the clock circuit structure can not suppress electric current I and operating voltage VDD fluctuation, and the clock output frequency shake is very big;
2. the prime power management module need use filter circuit to reduce the ripple of I and VDD, has increased chip area and cost, and design difficulty is big;
3. the clock circuit structure can not suppress electric current I and operating voltage VDD deviation, has limited the operating distance of RFID chip;
4.RFID during chip operation, must frequently use clock alignment, reduced operating efficiency, increased the design difficulty of digital baseband simultaneously.
5. the temperature coefficient under the output clock frequency normal temperature is big, and the temperature range of RFID chip operation is narrow.
Summary of the invention
The objective of the invention is to overcome the deficiency of above-mentioned prior art, a kind of clock generation circuit that is used for passive UHF RFID chip is provided, to suppress fluctuation and the deviation of electric current I and voltage VDD, reduce clock jitter and deviation and temperature drift, make the RFID chip operation in farther distance and wideer temperature range.
For achieving the above object, clock circuit of the present invention comprises: one group of current mirror clock alignment circuit, first inverter, second inverter, first comparator, second comparator, first rest-set flip-flop, second rest-set flip-flop, the 3rd inverter and the 4th inverter, current mirror clock alignment circuit output current I
2Resistance R ' generation comparative level the V of the inverting input by being connected first comparator and second comparator, the output of first inverter and the first charge and discharge capacitance C
1Be connected with the in-phase input end of first comparator, the output of first comparator input that is connected to first inverter of input S and the output Q by first rest-set flip-flop and second rest-set flip-flop successively constitutes first oscillation circuit; The output of second inverter and the second charge and discharge capacitance C
2Be connected with the in-phase input end of second comparator, the output of second comparator input that is connected to second inverter of input R and the output～Q by first rest-set flip-flop and second rest-set flip-flop successively constitutes second oscillation circuit, output～the Q of second rest-set flip-flop is successively through the 3rd inverter and the 4th inverter output clock, wherein: the N trap resistance R of resistance R ' employing positive temperature coefficient
1High resistance polysilicon resistance R with negative temperature coefficient
2Be in series, regulate the ratio of these two kinds of resistance, obtain the clock frequency of zero-temperature coefficient under the normal temperature, avoid the temperature of clock to float problem; The resistance R that is being connected in series
1And R
2Two ends are connected in parallel to the delay capacitor C
3, postpone T backward to realize comparative level V
0/ 4 times, avoid clock frequency to shake, T with current fluctuation
0Be the output clock cycle.
Described current mirror/clock alignment circuit adopts one group of PMOS current mirror to form, and this group PMOS current mirror is made up of six current mirror branch roads, but is not limited to six the tunnel, can be according to the needs of the scope and the precision of clock alignment, increase current mirror branch road.The first current mirror branch road is that comparator produces bias current I
3, the electric current I that the second current mirror branch road produces
2By resistance R ' generation comparative level V, Third Road current mirror branch road, the four road current mirror branch road, the five road current mirror branch road and the six road current mirror branch road compile the formation electric current I through a PMOS switching tube respectively
1, the clock alignment data are input to the grid of each PMOS switching tube, and the through and off of control switch pipe are to regulate electric current I
1Size.This structure makes electric current I
1With I
2Size and fluctuating range proportional: k=I
1/ I
2, during clock alignment port input default value, k=1.
The described first charge and discharge capacitance C
1With the second charge and discharge capacitance C
2Equate, make that the output clock duty cycle is 1: 1.
Described delay capacitor C
3Size be first to discharge and recharge C
1Or the second charge and discharge capacitance C
2Half, make comparative level V postpone T
0During/4 times, the output clock frequency is
C=C
1=C
2
Described first comparator and second comparator use the two stage comparator structure of typical PMOS input to pipe, and when hanging down to be implemented in comparative level V, each transistor of comparator can both work in the saturation region.
Described first rest-set flip-flop and second rest-set flip-flop use the NOR gate structure.
The present invention has following advantage:
The present invention since resistance R ' on the capacitor C that postpones in parallel
3After, make comparative level V postpone
Time, thereby output clock frequency
C=C
1=C
2Output clock frequency and electric current and independent from voltage, the fluctuation and the deviation that have suppressed electric current and voltage, solved the problem that clock is shaken with the fluctuation of current/voltage, and then reduced the design difficulty of prime power management module, and the prime power management module need not to design big filter circuit, saved chip area, and chip cost is reduced; When causing electric current and voltage deviation to occur apart from read write line greatly apart from change owing to the RFID chip, output clock frequency zero deflection, thus make chip can work in farther distance.And prior art is not owing to there is the capacitor C that postpones in parallel
3, the output clock frequency
Wherein, I
1=kI
2=k (I
0+ I
mCos ω t), T
0Be output clock cycle, I
0Be flip-flop, I
mBe the amplitude of current fluctuation, ω is a vibration frequency, and clock frequency is shaken with the fluctuation of electric current as can be seen.
2. resistance R of the present invention ' owing to adopt the N trap resistance of positive temperature coefficient and the high resistance polysilicon resistance of negative temperature coefficient to be in series, by regulating the ratio of two kinds of resistance, the temperature coefficient of last trading day and electric capacity, obtain the clock frequency of almost nil temperature coefficient under the normal temperature, thereby the temperature that has solved clock is floated problem, makes chip operation in bigger temperature range.
3. current mirror of the present invention/clock alignment circuit structure is simple, by Control current I
1Size, regulatory factor k, last trading day R ' and capacitor C
1And C
2Process deviation, thereby overcome technology to output clock frequency influence, the clock alignment port is k=1 when the input default value;
4. owing to be not subjected to distance and Temperature Influence in the certain limit of clock in follow-up work after the calibration, clock frequency is stable, need not frequent calibration, has improved chip operation efficient; And can use outside artificial fixed calibration pattern, digital baseband need not the clock alignment module of design control return data separately, has reduced the chip digital baseband design complexities, has reduced area of chip.
Description of drawings
Fig. 1 is the traffic diagram of existing read write line and label chip;
Fig. 2 is existing label chip AFE (analog front end) and digital baseband structure chart;
Fig. 3 is a clock integrated circuit schematic diagram of the present invention;
Fig. 4 is the current mirror/clock alignment module circuit diagram in the whole schematic diagram of clock of the present invention;
Fig. 5 is the comparator circuit figure in the whole schematic diagram of clock of the present invention;
Fig. 6 is the rest-set flip-flop circuit diagram in the whole schematic diagram of clock of the present invention;
Fig. 7 be resistance R of the present invention ' theory of constitution figure;
Fig. 8 is clock of the present invention and existing clock simulation result comparison diagram;
Fig. 9 is a clock delay capacitor C of the present invention
3Value with output clock frequency concern analogous diagram;
Figure 10 is a clock temperature characterisitic analogous diagram of the present invention.
Embodiment
With reference to Fig. 3, clock integrated circuit of the present invention comprises: one group of current mirror clock alignment circuit 301, first inverter 302, second inverter 303, the first charge and discharge capacitance C
1, the second charge and discharge capacitance C
2, first comparator 304, second comparator 305, first rest-set flip-flop 306, second rest-set flip-flop 307, the 3rd inverter 308 and the 4th inverter 309.Wherein first inverter 302 and second inverter 303 adopt PMOS pipe and NMOS pipe cascaded structure.Current mirror clock alignment circuit 301 output two-way electric current I
1And I
2, the first output current I
1Be input to the source electrode of the PMOS pipe of first inverter 302 and second inverter 303; The output of first inverter 302 and second inverter 303 is connected respectively to the in-phase input end of first comparator 304 and second comparator 305; The inverting input of first comparator 304 is connected with the inverting input of second comparator 305, and is parallel with the delay capacitor C
3And resistance R ', the output of first comparator 303 is the input that is connected to first inverter 302 of input S and the output Q by first rest-set flip-flop 306 and second rest-set flip-flop 307 successively, constitutes first oscillation circuit; The output of second comparator 305 is the input that is connected to second inverter 303 of input R and the output～Q by first rest-set flip-flop 306 and second rest-set flip-flop 307 successively, constitutes second oscillation circuit.The second output current I
2Flow through resistance R ', produce comparative level V; Be serially connected with the first charge and discharge capacitance C between the output of first inverter 302 and the ground
1, be serially connected with the second charge and discharge capacitance C between the output of second inverter 303 and the ground
2Output～the Q of second rest-set flip-flop is successively through the 3rd inverter 308 and the 4th inverter 309 output clocks.Postpone capacitor C
3Size be first to discharge and recharge C
1Or the second charge and discharge capacitance C
2Half, make comparative level V postpone T
0During/4 times, the output clock frequency is
C=C
1=C
2, the N trap resistance of resistance R ' employing positive temperature coefficient and the high resistance polysilicon resistance of negative temperature coefficient are in series, and as shown in Figure 7, regulate the ratio of these two kinds of resistance, make that the temperature coefficient of output clock is zero.
With reference to Fig. 4, current mirror/clock alignment circuit 301 adopts one group of PMOS current mirror to form, and this group PMOS current mirror is made up of six current mirror branch roads, but is not limited to six the tunnel, can be according to the needs of the scope and the precision of clock alignment, increase current mirror branch road.The first current mirror branch road 401 produces bias current I for comparator
3, the electric current I that the second current mirror branch road 402 produces
2By resistance R ' generation comparative level V, Third Road current mirror branch road 403, the four road current mirror branch road 404, the five road current mirror branch road 405 and the six road current mirror branch road 406 compile the formation electric current I through a PMOS switching tube respectively
1, the clock alignment data are input to the grid of each PMOS switching tube, and the through and off of control switch pipe are to regulate electric current I
1Size.This structure makes electric current I
1With I
2Size and fluctuating range proportional: k=I
1/ I
2, during clock alignment port input default value, k=1.
With reference to Fig. 5, first comparator 304 and second comparator 305 use the two stage comparator structure of typical PMOS input to pipe, and when hanging down to be implemented in comparative level V, each transistor of comparator can both work in the saturation region.
With reference to Fig. 6, first rest-set flip-flop 306 and second rest-set flip-flop 307 use the NOR gate structure.
The course of work of the present invention is as follows:
If trigger is in behind the power supply electrifying～state of Q=1, Q=0, and the then P of inverter 302 pipe conducting, the N pipe ends, the N pipe conducting of inverter 303, the P pipe ends, so electric current I
1Through the P of inverter 302 pipe to capacitor C
1Charging is along with the C that carries out of charging process
1On voltage and raise gradually; C
2Through the discharge over the ground of the N of inverter 303 pipe, arrive low level rapidly.
Work as C
1On voltage when rising to V, comparator 304 output S are high by low upset, trigger 307 states also upset immediately are～the state of Q=0, Q=1, so the conducting of the P of inverter 303 pipe, the N pipe ends, the N pipe conducting of inverter 302, the P pipe ends, I
1To C
2Charging, the voltage on it rises gradually, C
1Through the discharge over the ground of the N of inverter 303 pipe, drop to low level rapidly.
Work as C
2On voltage when rising to V, comparator 305 output R are high by the low level upset, so Q=0, simultaneously～Q=1, trigger 307 has been got back to above-mentioned first state again, again to C
1Charging, C
2Discharge.So go round and begin again, just obtained the output clock waveform at～Q or Q end.
For making output clock frequency and electric current irrelevant, resistance R ' on delay capacitor C in parallel
3,
Make comparative level V postpone T
0/ 4 times, thus the output clock frequency is
Effect of the present invention can further specify by following emulation:
Emulation 1: existing clock circuit and clock circuit contrast simulation of the present invention
Input reference electric current I ripple amplitude accounts for the specified direct current different proportion of input, to ring oscillator, no capacitor C
3Clock and add electric capacity C
3Clock carry out emulation respectively, add electric capacity C
3Clock be clock of the present invention.Emulated data such as table 1, analogous diagram are as shown in Figure 8.
Table 1 clock circuit of the present invention and the contrast of existing clock emulated data
As can be seen from Table 1, clock of the present invention increases the delay capacitor C
3, the output clock jitter is very little, is about no capacitor C
3Timing topology 1/16, be about 1/180 of ring oscillator.
Because the shake of ring oscillator is too big, only having contrasted among Fig. 8 increases the delay capacitor C
3Timing topology and no capacitor C
3Timing topology, as can be seen from Figure 8, do not have shunt capacitance C
3Clock increase rapidly with the amplitude of current fluctuation, and clock jitter of the present invention is very little, when the current fluctuation amplitude increased, clock jitter did not almost increase.
By table 1 and Fig. 8 as can be seen, clock of the present invention has very strong inhibition ability to the reference current ripple, and clock jitter is very little, and existing clock circuit is not owing to be with the delay capacitor C
3, the ability that suppresses ripple reduces greatly.
Emulation 2: the parallel connection of clock of the present invention postpones capacitor C
3Value to output clock influence
Account under the different ratio of the specified flip-flop of input in reference current ripple amplitude, get the delay capacitor C
3During for different value, diplomatic copy invention clock circuit, simulation result is as shown in Figure 9.
As shown in Figure 9, when postponing capacitor C
3For
The time, output clock jitter minimum, and current ripples is more little, and clock jitter is more little.
Emulation 3: clock temperature characterisitic of the present invention emulation
Clock of the present invention uses the N trap resistance R of positive temperature coefficient
1High resistance polysilicon resistance R with negative temperature coefficient
2Series compensation reduces the temperature coefficient of exporting clock frequency, and simulation result as shown in figure 10.
As seen from Figure 10, when temperature was 25 ℃, clock temperature coefficient of the present invention was 26ppm/ ℃ only, illustrated that clock circuit of the present invention has very strong inhibition temperature to float ability.
Claims (6)
1. clock generation circuit that is used for passive high-frequency radio frequency identification chip, comprise: one group of current mirror clock alignment circuit (301), first inverter (302), second inverter (303), first comparator (304), second comparator (305), first rest-set flip-flop (306), second rest-set flip-flop (307), the 3rd inverter (308) and the 4th inverter (309), current mirror clock alignment circuit (301) output current I
2Resistance R ' generation comparative level the V of the inverting input by being connected first comparator (304) and second comparator (305), the output of first inverter and the first charge and discharge capacitance C
1Be connected with the in-phase input end of first comparator, the output of first comparator input that is connected to first inverter of input S and the output Q by first rest-set flip-flop and second rest-set flip-flop successively constitutes first oscillation circuit; The output of second inverter and the second charge and discharge capacitance C
2Be connected with the in-phase input end of second comparator, the output of second comparator input that is connected to second inverter of input R and the output～Q by first rest-set flip-flop and second rest-set flip-flop successively constitutes second oscillation circuit, output～the Q of second rest-set flip-flop through the 3rd inverter (308) and the 4th inverter (309) output clock, is characterized in that successively:
The N trap resistance R of resistance R ' employing positive temperature coefficient
1High resistance polysilicon resistance R with negative temperature coefficient
2Be in series, regulate the ratio of these two kinds of resistance, obtain the clock frequency of zero-temperature coefficient under the normal temperature, avoid the temperature of clock to float problem;
The resistance R that is being connected in series
1And R
2Two ends are connected in parallel to the delay capacitor C
3, postpone T backward to realize comparative level V
0/ 4 times, avoid clock frequency to shake, T with current fluctuation
0Be the output clock cycle.
2. according to the described clock generation circuit of claim 1, it is characterized in that: current mirror/clock alignment circuit (301) adopts one group of PMOS current mirror to form, this group PMOS current mirror is made up of six current mirror branch roads, but be not limited to six the tunnel, can increase the current mirror branch road according to the needs of the scope and the precision of clock alignment.The first current mirror branch road (401) produces bias current I for comparator
3, the electric current I that the second current mirror branch road (402) produces
2By resistance R ' generation comparative level V, Third Road current mirror branch road (403), the four road current mirror branch road (404), the five road current mirror branch road (405) and the six road current mirror branch road (406) compile the formation electric current I through a PMOS switching tube respectively
1, the clock alignment data are input to the grid of each PMOS switching tube, and the through and off of control switch pipe are to regulate electric current I
1Size.This structure makes electric current I
1With I
2Size and fluctuating range proportional: k=I
1/ I
2, during clock alignment port input default value, k=1.
3. according to the described clock generation circuit of claim 1, it is characterized in that: the first charge and discharge capacitance C
1With the second charge and discharge capacitance C
2Equate, make that the output clock duty cycle is 1: 1.
4. according to the described clock generation circuit of claim 1, it is characterized in that: postpone capacitor C
3Size be first to discharge and recharge C
1Or the second charge and discharge capacitance C
2Half, make comparative level V postpone T
0During/4 times, the output clock frequency is
5. according to the described clock generation circuit of claim 1, it is characterized in that: first comparator (304) and second comparator (305) use the two stage comparator structure of typical PMOS input to pipe, when hanging down to be implemented in comparative level V, each transistor of comparator can both work in the saturation region.
6. according to the described clock generation circuit of claim 1, it is characterized in that: first rest-set flip-flop (306) and second rest-set flip-flop (307) use the NOR gate structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910023889A CN101692607A (en) | 2009-09-11 | 2009-09-11 | High stability clock circuit for passive high-frequency radio frequency identification chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910023889A CN101692607A (en) | 2009-09-11 | 2009-09-11 | High stability clock circuit for passive high-frequency radio frequency identification chip |
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| Publication Number | Publication Date |
|---|---|
| CN101692607A true CN101692607A (en) | 2010-04-07 |
Family
ID=42081270
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910023889A Pending CN101692607A (en) | 2009-09-11 | 2009-09-11 | High stability clock circuit for passive high-frequency radio frequency identification chip |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102880220A (en) * | 2011-07-12 | 2013-01-16 | 联咏科技股份有限公司 | Temperature coefficient current triggering generator and temperature coefficient current triggering generating module |
| CN103677082A (en) * | 2013-12-20 | 2014-03-26 | 深圳国微技术有限公司 | Clock frequency monitoring circuit and method |
| WO2016090729A1 (en) * | 2014-12-08 | 2016-06-16 | 佛山市顺德区阿波罗环保器材有限公司 | Water purification apparatus based on filter cartridge identification security |
| CN107231149A (en) * | 2017-06-08 | 2017-10-03 | 深圳驰芯微电子有限公司 | Chip and method for manufacturing the same |
| CN107507642A (en) * | 2017-10-13 | 2017-12-22 | 睿力集成电路有限公司 | Resistance value calibration circuit and method and apply its semiconductor memory |
| CN112910458A (en) * | 2019-12-03 | 2021-06-04 | 华润微集成电路(无锡)有限公司 | Counting circuit and hysteresis voltage generation method thereof |
| CN114900036A (en) * | 2022-05-24 | 2022-08-12 | 哈尔滨工业大学 | Switched capacitor voltage-stabilizing chip circuit with double control modes |
| CN117200756A (en) * | 2023-11-08 | 2023-12-08 | 成都爱旗科技有限公司 | Relaxation oscillator with adjustable temperature coefficient and temperature coefficient adjusting method thereof |
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2009
- 2009-09-11 CN CN200910023889A patent/CN101692607A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102880220A (en) * | 2011-07-12 | 2013-01-16 | 联咏科技股份有限公司 | Temperature coefficient current triggering generator and temperature coefficient current triggering generating module |
| CN102880220B (en) * | 2011-07-12 | 2016-01-06 | 联咏科技股份有限公司 | Temperature coefficient current shot generator and temperature coefficient current trigger generation module |
| CN103677082A (en) * | 2013-12-20 | 2014-03-26 | 深圳国微技术有限公司 | Clock frequency monitoring circuit and method |
| CN103677082B (en) * | 2013-12-20 | 2016-06-29 | 深圳国微技术有限公司 | Clock frequency observation circuit and method |
| WO2016090729A1 (en) * | 2014-12-08 | 2016-06-16 | 佛山市顺德区阿波罗环保器材有限公司 | Water purification apparatus based on filter cartridge identification security |
| CN107231149A (en) * | 2017-06-08 | 2017-10-03 | 深圳驰芯微电子有限公司 | Chip and method for manufacturing the same |
| CN107507642A (en) * | 2017-10-13 | 2017-12-22 | 睿力集成电路有限公司 | Resistance value calibration circuit and method and apply its semiconductor memory |
| CN112910458A (en) * | 2019-12-03 | 2021-06-04 | 华润微集成电路(无锡)有限公司 | Counting circuit and hysteresis voltage generation method thereof |
| CN112910458B (en) * | 2019-12-03 | 2024-05-17 | 华润微集成电路(无锡)有限公司 | Counting circuit and hysteresis voltage generation method thereof |
| CN114900036A (en) * | 2022-05-24 | 2022-08-12 | 哈尔滨工业大学 | Switched capacitor voltage-stabilizing chip circuit with double control modes |
| CN117200756A (en) * | 2023-11-08 | 2023-12-08 | 成都爱旗科技有限公司 | Relaxation oscillator with adjustable temperature coefficient and temperature coefficient adjusting method thereof |
| CN117200756B (en) * | 2023-11-08 | 2024-02-02 | 成都爱旗科技有限公司 | Relaxation oscillator with adjustable temperature coefficient and temperature coefficient adjusting method thereof |
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