CN105956647B - A kind of demodulator circuit applied to passive ultra-high frequency radio frequency identification label chip - Google Patents
A kind of demodulator circuit applied to passive ultra-high frequency radio frequency identification label chip Download PDFInfo
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- CN105956647B CN105956647B CN201610267759.5A CN201610267759A CN105956647B CN 105956647 B CN105956647 B CN 105956647B CN 201610267759 A CN201610267759 A CN 201610267759A CN 105956647 B CN105956647 B CN 105956647B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/0723—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
Abstract
The invention discloses a kind of demodulator circuits applied to passive ultra-high frequency radio frequency identification label chip, including the envelope detection circuit, pressure limiting circuit, low-pass filter circuit, the datum that are sequentially connected in series generate the output circuit compared with.The method that the envelope detection circuit of the present invention uses active envelope detection, the baseband signal being modulated on high frequency carrier is restored, the envelope signal of reduction is limited in through pressure limiting circuit in the common-mode input range of late-class circuit, then low-pass filtered circuit filters out the noise signal in high frequency carrier and environment, be input to again datum generate compared in output circuit compared with datum output digit signals, to digital base band processor, have the advantages that high sensitivity, low-power consumption, area are smaller.
Description
Technical field
The present invention relates to field of analog integrated circuit, more particularly to a kind of to be applied to passive ultra-high frequency RFID tag core
The demodulator circuit of piece.
Background technology
Radio frequency identification (RFID) is used as a kind of automatic identification technology, fast with reading speed compared with traditional bar code,
The advantages that long lifespan, reusable, small, data storage capacity are big and smaller by external environment influence, especially passive UHF
RFID has the characteristics that identification apart from remote, which is widely used in logistic storage management, the manufacturing, retail business and postal
The services such as political affairs express delivery and production field.
Usually basic RFID system is mainly made of RFID tag, reader, antenna, middleware and application software.
RFID tag is made of as the real carrier of data label chip and antenna.And label chip is mainly by rf analog front-end
Circuit, digital baseband, memory composition.Demodulator circuit belongs to rf analog front-end circuit, is mainly responsible for reader sending base
Band signal is demodulated, and is given digital baseband and handled.As passive RFID tag chip, need to emit by reader
Electromagnetic wave make its normal work to provide energy.Based on the considerations of chip cost and technical aspect, usual reader will be sent
Baseband signal by amplitude modulate (ASK) in a manner of, realize from reader to the communication of label chip forward link.It is remote to adapt to
Distance work needs label chip to have the characteristics that highly sensitive and low-power consumption, i.e., when reader sends small-signal, mark
Label chip can also be normally carried out demodulation.Demodulator circuit is generally divided into voltage-type and current mode；Current mode demodulator circuit usually will be electric
Pressure signal is converted to current signal and is handled, and structure is often more complicated.And voltage-type demodulator circuit, it is simple in structure to be easy to
It realizes, but traditional voltage-type demodulator circuit uses Schottky diode as envelope detection circuit, in the CMOS technology of standard
It is middle to bring relatively high cost.And the method for using inside and outside valve value compensation can increase additional chip area and power consumption.In addition,
The method that datum generation circuit uses electric resistance partial pressure in demodulator, can bring bigger area.Therefore, there is an urgent need to one
The small ASK demodulator circuits of kind low-power consumption, high sensitivity, area.
Invention content
In order to solve the above technical problem, the present invention provides a kind of low in energy consumption, high sensitivity, area it is small be applied to it is passive
The ASK demodulator circuits of UHF RFID label chips.
Technical proposal that the invention solves the above-mentioned problems is：It is a kind of applied to passive ultra-high frequency radio frequency identification label chip
Demodulator circuit, including the envelope detection circuit, pressure limiting circuit, low-pass filter circuit, the datum that are sequentially connected in series generate compared with
Output circuit, the envelope detection circuit include the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube, third
NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, the first capacitance, the second capacitance, third capacitance, the 4th capacitance,
5th capacitance, the first PMOS tube, the second PMOS tube source electrode connect high level, the grid of the grid of the first PMOS tube and the second PMOS tube
Extremely it is connected, and is connected with external bias voltage；The drain electrode of first PMOS tube is connected with the drain electrode of the first NMOS tube and is connected to
The grid of one NMOS tube；The source electrode of first NMOS tube is connected with the drain electrode of the second NMOS tube；The grid of first NMOS tube, second
The grid of NMOS tube, the 6th NMOS tube grid be connected and be connected to the 5th capacitance one end；The 5th capacitance other end is penetrated with first
Frequency input terminal is connected；The source electrode of second NMOS tube is connected with the source electrode of the 6th NMOS tube and is connected to ground；The leakage of second PMOS tube
Pole is connected and is connected to the grid of third NMOS tube with the drain electrode of third NMOS tube；The source electrode of third NMOS tube and the 4th NMOS tube
Drain electrode be connected；The grid of third NMOS tube, the grid of the 4th NMOS tube, the 5th NMOS tube grid be connected and be connected to second
Capacitance one end；The second capacitance other end is connect with the second rf inputs；The source electrode of 4th NMOS tube, the source of the 5th NMOS tube
The drain electrode of pole, the 6th NMOS tube is connected and is connected to the 4th capacitance one end；The 4th capacitance other end and third rf inputs phase
Even；Third capacitance one end is connected with the source electrode of the 5th NMOS tube, and the third capacitance other end is connected with the grid of the 5th NMOS tube；The
The drain electrode of five NMOS tubes is connected with pressure limiting circuit；One end of first capacitance is connected with the drain electrode of the 5th NMOS tube, the first capacitance
The other end is connected with the 4th rf inputs, wherein the first rf inputs and the second rf inputs differential input signal each other
End, third rf inputs and the 4th rf inputs differential input signal end each other.
For above application in the demodulator circuit of passive ultra-high frequency radio frequency identification label chip, the pressure limiting circuit includes the 7th
NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the tenth NMOS tube, the 6th capacitance, the grid of the 7th NMOS tube, the 8th NMOS tube
Drain electrode, the 9th NMOS tube grid be connected with the drain electrode of the 5th NMOS tube, the grid and the 7th NMOS tube of the 7th NMOS tube
Drain electrode be connected；The source electrode of 7th NMOS tube is grounded；The grid of 9th NMOS tube is connected with the drain electrode of the 9th NMOS tube；8th
The grid of NMOS tube, the source electrode of the 9th NMOS tube, the grid of the tenth NMOS tube, the tenth NMOS tube drain electrode be connected and with the 6th electricity
One end of appearance connects；Source electrode, the source electrode of the tenth NMOS tube, the other end of the 6th capacitance of 8th NMOS tube are connected and are grounded.
In the demodulator circuit of passive ultra-high frequency radio frequency identification label chip, the low-pass filter circuit includes above application
Resistance and the 7th capacitance, resistance one end are connected with the drain electrode of the 5th NMOS tube, the resistance other end, the 7th capacitance one end respectively with
The input terminal that datum generates the output circuit compared with is connected, the other end ground connection of the 7th capacitance.
Above application in the demodulator circuit of passive ultra-high frequency radio frequency identification label chip, the datum generate with than
Include third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the 8th PMOS compared with output circuit
Pipe, the 9th PMOS tube, the tenth PMOS tube, the 11st PMOS tube, the 12nd PMOS tube, the 11st NMOS tube, the 12nd NMOS tube,
13rd NMOS tube, the 14th NMOS tube, the 15th NMOS tube, the 16th NMOS tube, the 17th NMOS tube, the 18th NMOS tube
With the 8th capacitance, the drain electrode of third PMOS tube, the grid of the grid of third PMOS tube, the grid of the 4th PMOS tube, the 9th PMOS tube
Pole, the 11st PMOS tube grid be connected with each other and be connected with external bias voltage, the source electrode of third PMOS tube, the 4th PMOS tube
Source electrode, the source electrode of the 9th PMOS tube, the source electrode of the 11st PMOS tube be connected with each other and connect high level；The leakage of 4th PMOS tube
The source electrode interconnection of pole, the source electrode of the 5th PMOS tube, the source electrode of the 6th PMOS tube, the 8th PMOS tube；11st NMOS tube
It drains with the connection of the grid of the 5th PMOS tube and is connected to the 7th as the input terminal of output circuit compared with is generated with reference to level
One end of capacitance；The drain electrode of 5th PMOS tube, grid, the drain electrode of the 12nd NMOS tube, the 12nd NMOS of the 11st NMOS tube
The grid interconnection of the grid of pipe, the grid of the 13rd NMOS tube, the grid of the 14th NMOS tube, the 16th NMOS tube；The
The grid of six PMOS tube, the drain electrode of the 14th NMOS tube, the source electrode of the 7th PMOS tube, the 7th PMOS tube grid, the 8th PMOS
The grid of pipe is connected with each other and is connected with the 8th capacitance one end；The drain electrode of 6th PMOS tube, the drain electrode of the 13rd NMOS tube, the tenth
The grid interconnection of the grid of PMOS tube, the 17th NMOS tube；The drain electrode of 8th PMOS tube, the drain electrode of the 7th PMOS tube,
The drain electrode of the grid of 15 NMOS tubes, the 16th NMOS tube is connected with each other；The source electrode and the 15th NMOS tube of 14th NMOS tube
Drain electrode be connected；The drain electrode of 9th PMOS tube is connected with the source electrode of the tenth PMOS tube；The drain electrode of tenth PMOS tube, the 17th
The drain electrode of NMOS tube, the grid interconnection of the grid of the 12nd PMOS tube, the 18th NMOS tube；The drain electrode of 11st PMOS tube
It is connected with the source electrode of the 12nd PMOS tube；The drain electrode of 12nd PMOS tube is connected with each other and connect with the drain electrode of the 18th NMOS tube
To output voltage terminal；The source electrode of 11st NMOS tube, the source electrode of the 12nd NMOS tube, the source electrode of the 13rd NMOS tube, the 15th
The source electrode of NMOS tube, the source electrode of the 16th NMOS tube, the source electrode of the 17th NMOS tube, the source electrode of the 18th NMOS tube, the 8th electricity
The other end of appearance is connected with each other and is grounded.
Above application is in the demodulator circuit of passive ultra-high frequency radio frequency identification label chip, all NMOS tube and PMOS tube
It is operated in sub-threshold region.
The beneficial effects of the present invention are：
1, the present invention includes the envelope detection circuit being sequentially connected in series, pressure limiting circuit, low-pass filter circuit, datum generation
The output circuit compared with can improve demodulator sensitivity using active envelope detection circuit, increase the working distance of label chip
From；Pressure limiting circuit can play the role of a good pressure limiting when label near field works, and improve the dynamic range of demodulator；
2, datum of the invention generates the method that output circuit uses peak detection compared with, instead of traditional big electricity
Bulky capacitor is hindered, chip area is reduced, saves chip cost；
3, metal-oxide-semiconductor all in circuit of the present invention is all operated in sub-threshold region, has the characteristics that low current low-power consumption, adapts to
The requirement of passive label chip.
Description of the drawings
Fig. 1 is the circuit diagram of the present invention.
It in input radio frequency frequency of carrier signal is 920MHz that Fig. 2, which is the present invention, amplitude 0.1V, modulation depth 30%,
Modulation rate is 80kb/s, and supply voltage VDD is under 1.4V, and input signal is imitative with envelope signal, datum and output signal
True figure.
Fig. 3 be the present invention input radio frequency frequency of carrier signal be 920MHz, amplitude 1V, modulation depth 30%, adjust
Rate processed is 80kb/s, and supply voltage VDD is under 1.4V, and input signal is emulated with envelope signal, datum and output signal
Figure.
Transient power consumption analogous diagram when Fig. 4 is present invention normal work.
Specific implementation mode
The present invention is further illustrated with reference to the accompanying drawings and examples.
As shown in Figure 1, the present invention include the envelope detection circuit 1 being sequentially connected in series, pressure limiting circuit 2, low-pass filter circuit 3,
Datum generate with compared with output circuit 4, the envelope detection circuit 1 including the first PMOS tube 101, the second PMOS tube 102,
First NMOS tube 103, the second NMOS tube 104, third NMOS tube 105, the 4th NMOS tube 106, the 5th NMOS tube the 107, the 6th
NMOS tube 108, the first capacitance 131, the second capacitance 132, third capacitance 133, the 4th capacitance 134, the 5th capacitance 135, first
PMOS tube 101, the second PMOS tube 102 source electrode connect high level, the grid of the grid of the first PMOS tube 101 and the second PMOS tube 102
Extremely it is connected, and generates grid and drain electrode, the 4th of the third PMOS tube 114 compared in output circuit 4 with datum
The grid of PMOS tube 115, the grid of the 9th PMOS tube 125, the grid of the 11st PMOS tube 128 are connected, constitute current-mirror structure,
By being supplied to 114 bias current of third PMOS tube by outside, generates a bias voltage VIBIAS and provided partially to different branch
Set electric current；The drain electrode of first PMOS tube 101 is connected with the drain electrode of the first NMOS tube 103, the drain electrode of the first NMOS tube 103 and grid
It is connected and is connected with the grid of the grid of the second NMOS tube 104, the 6th NMOS tube 108 and constitute current-mirror structure, to eliminate charge
108 threshold voltage of the 6th NMOS tube of transfer tube influences.Equally, the drain electrode of third NMOS tube 105 is connected with grid and with the 4
The connected composition current-mirror structure of grid of the grid of NMOS tube 106, the 5th NMOS tube 107, eliminates the 5th NMOS of charge transfer tube
107 threshold voltage of pipe influences.The source electrode of first NMOS tube 103 is connected with the drain electrode of the second NMOS tube 104.
5th capacitance, 135 one end and the grid of the first NMOS tube 103, the grid of the second NMOS tube 104, the 6th NMOS tube
108 grid is connected, and is used as coupled capacitor, controls the grid voltage of the 6th NMOS tube 108, is at turn-on and turn-off shape
State.The source electrode of second NMOS tube 104 is connected with the source electrode of the 6th NMOS tube 108 and is connected to ground；The drain electrode of second PMOS tube 102
It is connected and is connected to the grid of third NMOS tube 105 with the drain electrode of third NMOS tube 105；The source electrode of third NMOS tube 105 and
The drain electrode of four NMOS tubes 106 is connected；4th capacitance, 134 one end and the source electrode of the 4th NMOS tube 106, the source of the 5th NMOS tube 107
The drain electrode of pole, the 6th NMOS tube 108 is connected, and is connect with 133 one end of third capacitance, is used as storage capacitance, is handed in radiofrequency signal
Charge and discharge are carried out when for variation；The grid of second capacitance, 132 one end and third NMOS tube 105, the grid of the 4th NMOS tube 106,
The grid of 5th NMOS tube 107 is connected, and is connect with 133 other end of third capacitance, is used as coupled capacitor, controls the 5th NMOS tube
107 grid voltage is at turn-on and turn-off state；When the second capacitance 132 is equal with the 4th capacitance 134, at this time
Three capacitances 133 stablize the gate source voltage of its 5th NMOS tube 107 for storing direct current signal.One end of first capacitance 131 and the
The grid of 7th NMOS tube and drain electrode, the drain electrode of the 8th NMOS tube, the 9th in the drain electrode of five NMOS tubes 107 and pressure limiting circuit 2
The grid of NMOS tube is respectively connected with drain electrode, 137 one end of resistance, is used as storage capacitance.
First capacitance 131 is connected with rf inputs RF+ respectively with 135 other end of the 5th capacitance；Second capacitance 132 and
Four capacitances, 134 other end is connected with radio frequency input RF- respectively.When RF+ is high voltage, and RF- is low-voltage, the 6th NMOS tube
108 conductings, the shutdown of the 5th NMOS tube 107.The charge of ground terminal is charged by the 6th NMOS tube 108 of transfer tube to the 4th capacitance 134,
Meanwhile first capacitance 131 discharge charge.When RF+ is low-voltage, and RF- is high voltage, the shutdown of the 6th NMOS tube 108, the 5th
NMOS tube 107 is connected, and the charge for being stored in the 4th capacitance 134 is filled by the 5th NMOS tube 107 of transfer tube to the first capacitance 131
Electricity, the charge discharge path on the first capacitance 131, is made of pressure limiting circuit 2 and low-pass filter circuit 3.
The effect of envelope detection circuit 1 is to restore the baseband signal being modulated on radio-frequency carrier, in order to eliminate MOS
Pipe threshold is influenced caused by sensitivity, the method for using active envelope detection, passes through the first PMOS tube 101, the first NMOS
Pipe 103, the second NMOS tube 104 are that the 6th NMOS tube 108 provides a stable bias voltage；Second PMOS tube 102, third
NMOS tube 105, the 4th NMOS tube 106 are that the 5th NMOS tube 107 provides a stable bias voltage；Radiofrequency signal RF+ and RF-
Differential input signal each other.
The pressure limiting circuit 2 includes the 7th NMOS tube 109, the 8th NMOS tube 110, the 9th NMOS tube 111, the tenth NMOS tube
112, the 6th capacitance 136, grid, the drain electrode of the 8th NMOS tube 110, the grid of the 9th NMOS tube 111 of the 7th NMOS tube 109 are equal
It is connected with the drain electrode of the 5th NMOS tube 107, the grid of the 7th NMOS tube 109 is connected with the drain electrode of the 7th NMOS tube 109；7th
The source electrode of NMOS tube 109 is grounded；The grid of 9th NMOS tube 111 is connected with the drain electrode of the 9th NMOS tube 111；8th NMOS tube
110 grid, the source electrode of the 9th NMOS tube 111, the grid of the tenth NMOS tube 112, the tenth NMOS tube 112 drain electrode be connected and with
One end of 6th capacitance 136 connects；The source electrode of 8th NMOS tube 110, the source electrode of the tenth NMOS tube 112, the 6th capacitance 136 it is another
One end is connected and is grounded.
The effect of pressure limiting circuit 2 is limitation envelope signal voltage amplitude, makes it without departing from datum generation circuit and ratio
Compared with the common-mode input range of device circuit.Using two-stage pressure limiting；The 7th NMOS tube 109 connected by diode constitutes first order limit
Pressure, the 8th NMOS tube 110, the 9th NMOS tube 111, the tenth NMOS tube 112, the 6th capacitance 136 constitute second level pressure limiting.7th
The grid of NMOS tube 109 is connected with drain electrode, constitutes the diode of a MOS connection.When envelope signal amplitude is more than Vgs109
First order pressure limiting circuit starts to act on, and Vgs109 is that the gate source voltage of the 7th NMOS tube 109 is poor；When envelope signal amplitude is more than
When Vgs111+Vgs112, the conducting of the 8th NMOS tube 110 proceeds by aerial drainage, wherein Vgs111 and Vgs112 are the 9th respectively
The gate source voltage of NMOS tube 111 and the tenth NMOS tube 112 is poor.6th capacitance 136 is used as pressure stabilization function, is the 8th NMOS tube 110
Grid provides a stable aerial drainage voltage value.
The effect of the low-pass filter circuit 3 is to filter out the noise letter in the high frequency carrier and environment on envelope signal
Number, low-pass filter circuit 3 includes resistance 137 and the 7th capacitance 138, the drain electrode phase of resistance 137 one end and the 5th NMOS tube 107
Even, 137 other end of resistance, the 7th capacitance 138 one end respectively with datum generate compared with output circuit 4 input terminal phase
Even, the other end ground connection of the 7th capacitance 138.Its resistance value meets the following formula with capacitance：
Wherein, Ω is modulated signal highest angular frequency, ω0It is carrier angular frequencies.Pass through regulation resistance 137 and the 7th capacitance
138 size can make it meet above formula.
Datum generates the effect of output circuit 4 with compared with and is that generating stable DC puts down, by will be straight
Galvanic electricity is flat compared with envelope signal, and output digit signals " 0 " and " 1 " are handled to digital baseband below.The reference electricity
The raw output circuit 4 compared with of showing no increases in output includes third PMOS tube 114, the 4th PMOS tube 115, the 5th PMOS tube 116, the 6th PMOS tube
117, the 7th PMOS tube 122, the 8th PMOS tube 123, the 9th PMOS tube 125, the tenth PMOS tube 126, the 11st PMOS tube 128,
12nd PMOS tube 129, the 11st NMOS tube 113, the 12nd NMOS tube 118, the 13rd NMOS tube 119, the 14th NMOS tube
120, the 15th NMOS tube 121, the 16th NMOS tube 124, the 17th NMOS tube 127, the 18th NMOS tube 130 and the 8th capacitance
139.The drain electrode of third PMOS tube 114, the grid of third PMOS tube 114, the grid of the 4th PMOS tube 115, the 9th PMOS tube 125
Grid, the 11st PMOS tube 128 grid be connected with each other and be connected with external bias voltage, the source electrode of third PMOS tube 114,
Source electrode, the source electrode of the 9th PMOS tube 125, the source electrode of the 11st PMOS tube 128 of 4th PMOS tube 115 are connected with each other and connect high electricity
It is flat；The drain electrode of 4th PMOS tube 115, the source electrode of the 5th PMOS tube 116, the source electrode of the 6th PMOS tube 117, the 8th PMOS tube 123
Source electrode be connected with each other；The drain electrode of 11st NMOS tube 113 connect with the grid of the 5th PMOS tube 116 and is produced as with reference to level
The raw input terminal of output circuit 4 compared with is connected to one end of the 7th capacitance 138；The drain electrode of 5th PMOS tube 116, the 11st
The grid of NMOS tube 113, the drain electrode of the 12nd NMOS tube 118, the grid of the 12nd NMOS tube 118, the 13rd NMOS tube 119
The grid interconnection of grid, the grid of the 14th NMOS tube 120, the 16th NMOS tube 124；The grid of 6th PMOS tube 117,
The drain electrode of 14th NMOS tube 120, the source electrode of the 7th PMOS tube 122, the grid of the 7th PMOS tube 122, the 8th PMOS tube 123
Grid is connected with each other and is connected with 139 one end of the 8th capacitance；The drain electrode of 6th PMOS tube 117, the leakage of the 13rd NMOS tube 119
The grid interconnection of pole, the grid of the tenth PMOS tube 126, the 17th NMOS tube 127；The drain electrode of 8th PMOS tube 123, the 7th
The drain electrode of PMOS tube 122, the drain electrode of the grid of the 15th NMOS tube 121, the 16th NMOS tube 124 are connected with each other；14th
The source electrode of NMOS tube 120 is connected with the drain electrode of the 15th NMOS tube 121；The drain electrode of 9th PMOS tube 125 and the tenth PMOS tube
126 source electrode is connected；The drain electrode of tenth PMOS tube 126, the drain electrode of the 17th NMOS tube 127, the 12nd PMOS tube 129 grid
The grid interconnection of pole, the 18th NMOS tube 130；The source electrode of the drain electrode and the 12nd PMOS tube 129 of 11st PMOS tube 128
It is connected；The drain electrode and the drain electrode of the 18th NMOS tube 130 of 12nd PMOS tube 129 are connected with each other and are connected to output voltage terminal；
Source electrode, the 15th NMOS of the source electrode of 11st NMOS tube 113, the source electrode of the 12nd NMOS tube 118, the 13rd NMOS tube 119
The source of the source electrode of pipe 121, the source electrode of the 16th NMOS tube 124, the source electrode of the 17th NMOS tube 127, the 18th NMOS tube 130
Pole, the 8th capacitance 139 the other end be connected with each other and be grounded.
The method that datum generation circuit uses peak detection, by the 5th PMOS tube 116, the 12nd NMOS tube 118,
8th PMOS tube 123, the 16th NMOS tube 124, the 7th PMOS tube 122, the 8th capacitance 139, the 14th NMOS tube the 120, the tenth
Five NMOS tubes 121 are constituted；Compare output circuit by the 5th PMOS tube 116, the 6th PMOS tube 117, the 12nd NMOS tube 118,
Single stage operational amplifier and the tenth PMOS tube 126 of 13 NMOS tubes 119 composition, the 17th NMOS tube 127 and the 12nd PMOS
The two-stage shaping circuit composition that pipe 129, the 18th NMOS tube 130 are constituted.
In datum generation circuit, the 5th PMOS tube 116, the 12nd NMOS tube 118, the 8th PMOS tube the 123, the 16th
NMOS tube 124 constitutes a single stage operational amplifier, and the 5th PMOS tube 116 and the 8th PMOS tube 123 are amplifier Differential Input pair
Pipe.The grid of 5th PMOS tube 116 is the in-phase input end of amplifier, and the grid of the 8th PMOS tube 123 is the anti-phase input of amplifier
End, the 12nd NMOS tube 118 and the 16th NMOS tube 124 constitute current-mirror structure, the load as amplifier.8th PMOS tube
123 drain electrode is connected with the drain electrode of the 16th NMOS tube 124, the output end as amplifier.The grid of 7th PMOS tube 122 and source
Extremely it is connected, constitutes a MOS diode, and be connected with the grid of the 8th PMOS tube 123, be attached to the reverse phase of operational amplifier
Input terminal.The drain electrode of 7th PMOS tube 122 is connected with the drain electrode of the drain electrode of the 8th PMOS tube 123, the 16th NMOS tube 124, i.e.,
It is connected to the output end of operational amplifier.
7th PMOS tube 122, the 8th capacitance 139, the 14th NMOS tube 120, the 15th NMOS tube 121 with it is above-mentioned
Operational amplifier constitutes a peak detection circuit.The grid of 7th PMOS tube 122 and drain electrode, 139 one end of the 8th capacitance, the
The drain electrode of the grid of eight PMOS tube 123, the grid of the 6th PMOS tube 117, the 14th NMOS tube 120 is connected with each other, and constitutes peak value
The output end of detection circuit.8th capacitance 139 and the 14th NMOS tube 120, the 15th NMOS tube 121 constitute peak detection electricity
The RC charge and discharge path on road.The grid of 14th NMOS tube 120 is connected with the grid of the 12nd NMOS tube 118, provides one surely
Fixed grid voltage.The grid of 15th NMOS tube 121 and the drain electrode of the 8th PMOS tube 123, the drain electrode of the 16th NMOS tube 124
It is connected, a dynamic grid voltage is provided, the velocity of discharge of peak detection circuit is controlled.When envelope signal amplitude increases,
The drain voltage increase of 8th PMOS tube 123, the 16th NMOS tube 124 so that the grid and drain voltage of the 7th PMOS tube 122
Increase.Meanwhile the 15th the grid voltage of NMOS tube 121 also increase, discharge current increases so that peak detection output end voltage
Maintain a stationary value.In order to enable peak detection voltage is less than envelope signal crest voltage, the breadth length ratio of the 5th PMOS tube 116
Following formula is must satisfy with the breadth length ratio of the 8th PMOS tube 123：
Wherein,It is the breadth length ratio of the 5th PMOS tube 116116,The breadth length ratio of 8th PMOS tube 123123.
It chooses suitably sized, makesForIntegral multiple.
Compare the 5th PMOS tube 116, the 6th PMOS tube 117, the 12nd NMOS tube 118, the 13rd NMOS in output circuit
Pipe 119 constitutes another operational amplifier.5th PMOS tube 116, the differential input end that the 6th PMOS tube 117 is amplifier, the 5th
The grid of PMOS tube 116 is in-phase input end, and the grid of the 6th PMOS tube 117 is inverting input, the 12nd NMOS tube 118,
13rd NMOS tube 119 is connected in the form of current mirror, is used as the load of amplifier.The grid and the 12nd of 11st NMOS tube 113
The grid of NMOS tube 118 is connected, for envelope signal aerial drainage.The drain electrode of 6th PMOS tube 117 and the 13rd NMOS tube 119
Drain electrode is connected, and is connected as the output end of amplifier, and with the grid of the grid of the tenth PMOS tube 126, the 17th NMOS tube 127.
The drain electrode of tenth PMOS tube 126 is connected with the drain electrode of the 17th NMOS tube 127, and with the grid of the 12nd PMOS tube 129, the tenth
The grid of eight NMOS tubes 130 is connected.The drain electrode of 9th PMOS tube 125 is connected with the source electrode of the tenth PMOS tube 126.9th PMOS tube
125 grid is connected with bias voltage VIBIAS, is carried for the phase inverter that the tenth PMOS tube 126 is constituted with the 17th NMOS tube 127
For a current limliting branch.The drain electrode of 11st PMOS tube 128 is connected with the source electrode of the 12nd PMOS tube 129.11st PMOS tube
128 grid is connected with bias voltage VIBIAS, is the phase inverter that the 12nd PMOS tube 129 and the 18th NMOS tube 130 are constituted
One current limliting branch is provided.
When the envelope signal of 116 grid of the 5th PMOS tube input is more than the datum of 117 grid of the 6th PMOS tube input
When, the electric current for flowing through the 5th PMOS tube 116 is less than the electric current of the 6th PMOS tube 117, flows through the electric current of the 5th PMOS tube 116 simultaneously
The 12nd NMOS tube 118 is flowed through, the electric current of the 6th PMOS tube 117 is flowed through while flowing through the 13rd NMOS tube 119.And the 12nd
The grid of NMOS tube 118 is connected with the grid of the 13rd NMOS tube 119.For NMOS tube, in the identical feelings of grid voltage
Under condition, its big drain voltage of electric current is big.Therefore, the drain voltage of the 13rd NMOS tube 119 is more than the 12nd NMOS tube 118
Drain voltage shows as high level.This high level by be made of the tenth PMOS tube 126 and the 17th NMOS tube 127 first
The second level phase inverter that grade phase inverter and the 12nd PMOS tube 129 and the 18th NMOS tube 130 are constituted, carrying out shaping output is
High level VOUT.When envelope signal is less than datum, the electric current for flowing through the 5th PMOS tube 116 is more than the 6th PMOS tube 117
Electric current, equally have 119 drain voltage of the 13rd NMOS tube be less than the 12nd NMOS tube 118 drain voltage, show as low electricity
It is flat, after two-stage phase inverter shaping, export as low level VOUT.
As shown in Fig. 2, radio-frequency input signals peak value is 0.1V, by envelope detection circuit 1, pressure limiting circuit 2, low-pass filtering
Envelope signal is obtained after circuit 3.Envelope signal obtains reference voltage by datum generation circuit all the way, and is input to and compares
For one section of device compared with envelope signal, demodulation output result, which is shown, normally demodulates data.
As shown in figure 3, radio-frequency input signals peak value is 1V, pressure limiting circuit 2 is opened at this time.Envelope signal peak value after pressure limiting
For 0.7V or so, within the common-mode input range in comparison circuit, output can be normally demodulated after comparison.
Fig. 4 show the transient power consumption analogous diagram within 0 to 250 μ s, and it is 293.6nW to be computed its average power consumption.
It the above is only the effect that embodiment is merely to illustrate the present invention, protection scope of the present invention is not limited merely to above-mentioned
Embodiment, it is noted that for those skilled in the art, if without departing from the principles of the present invention
Dry improvements and modifications, are regarded as protection scope of the present invention.
Claims (5)
1. a kind of demodulator circuit applied to passive ultra-high frequency radio frequency identification label chip, it is characterised in that：Including being sequentially connected in series
Envelope detection circuit, pressure limiting circuit, low-pass filter circuit, datum generate output circuit, the envelope detection compared with
Circuit includes the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube, third NMOS tube, the 4th NMOS tube, the
Five NMOS tubes, the 6th NMOS tube, the first capacitance, the second capacitance, third capacitance, the 4th capacitance, the 5th capacitance, the first PMOS tube,
The source electrode of second PMOS tube connects high level, and the grid of the first PMOS tube is connected with the grid of the second PMOS tube, and and external bias
Voltage is connected；The drain electrode of first PMOS tube is connected and is connected to the grid of the first NMOS tube with the drain electrode of the first NMOS tube；First
The source electrode of NMOS tube is connected with the drain electrode of the second NMOS tube；The grid of first NMOS tube, the grid of the second NMOS tube, the 6th NMOS
The grid of pipe is connected and is connected to the 5th capacitance one end；The 5th capacitance other end is connected with the first rf inputs；2nd NMOS
The source electrode of pipe is connected with the source electrode of the 6th NMOS tube and is connected to ground；The drain electrode phase of the drain electrode of second PMOS tube and third NMOS tube
Connect and be connected to the grid of third NMOS tube；The source electrode of third NMOS tube is connected with the drain electrode of the 4th NMOS tube；Third NMOS tube
Grid, the grid of the 4th NMOS tube, the grid of the 5th NMOS tube be connected and be connected to second capacitance one end；Second capacitance is another
End is connect with the second rf inputs；The drain electrode of the source electrode of 4th NMOS tube, the source electrode of the 5th NMOS tube, the 6th NMOS tube is connected
And it is connected to the 4th capacitance one end；The 4th capacitance other end is connected with third rf inputs；Third capacitance one end and the 5th
The source electrode of NMOS tube is connected, and the third capacitance other end is connected with the grid of the 5th NMOS tube；The drain electrode and pressure limiting of 5th NMOS tube
Circuit is connected；One end of first capacitance is connected with the drain electrode of the 5th NMOS tube, and the other end of the first capacitance and the 4th radio frequency input
End is connected, wherein the first rf inputs and the second rf inputs differential input signal end each other, third rf inputs and
4th rf inputs differential input signal end each other.
2. the demodulator circuit according to claim 1 applied to passive ultra-high frequency radio frequency identification label chip, feature exists
In：The pressure limiting circuit include the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the tenth NMOS tube, the 6th capacitance, the 7th
The grid of NMOS tube, the drain electrode of the 8th NMOS tube, the 9th NMOS tube grid be connected with the drain electrode of the 5th NMOS tube, the 7th
The grid of NMOS tube is connected with the drain electrode of the 7th NMOS tube；The source electrode of 7th NMOS tube is grounded；The grid of 9th NMOS tube and
The drain electrode of nine NMOS tubes is connected；The grid of 8th NMOS tube, the source electrode of the 9th NMOS tube, the grid of the tenth NMOS tube, the tenth
The drain electrode of NMOS tube is connected and is connect with one end of the 6th capacitance；The source electrode of 8th NMOS tube, the source electrode of the tenth NMOS tube, the 6th
The other end of capacitance is connected and is grounded.
3. the demodulator circuit according to claim 2 applied to passive ultra-high frequency radio frequency identification label chip, feature exists
In：The low-pass filter circuit includes resistance and the 7th capacitance, and resistance one end is connected with the drain electrode of the 5th NMOS tube, and resistance is another
End, the 7th capacitance one end generate that the input terminal of output circuit with compared with is connected with datum respectively, the 7th capacitance it is another
End ground connection.
4. the demodulator circuit according to claim 3 applied to passive ultra-high frequency radio frequency identification label chip, feature exists
In：It includes third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th that the datum, which generates the output circuit compared with,
PMOS tube, the 7th PMOS tube, the 8th PMOS tube, the 9th PMOS tube, the tenth PMOS tube, the 11st PMOS tube, the 12nd PMOS tube,
11st NMOS tube, the 12nd NMOS tube, the 13rd NMOS tube, the 14th NMOS tube, the 15th NMOS tube, the 16th NMOS
Pipe, the 17th NMOS tube, the 18th NMOS tube and the 8th capacitance, the drain electrode of third PMOS tube, the grid of third PMOS tube, the 4th
The grid of PMOS tube, the grid of the 9th PMOS tube, the 11st PMOS tube grid be connected with each other and be connected with external bias voltage,
The source electrode interconnection of the source electrode of third PMOS tube, the source electrode of the 4th PMOS tube, the source electrode of the 9th PMOS tube, the 11st PMOS tube
And connect high level；The drain electrode of 4th PMOS tube, the source of the source electrode of the 5th PMOS tube, the source electrode of the 6th PMOS tube, the 8th PMOS tube
Pole is connected with each other；The drain electrode of 11st NMOS tube connect with the grid of the 5th PMOS tube and as with reference to level generate with it is more defeated
The input terminal for going out circuit is connected to one end of the 7th capacitance；The drain electrode of 5th PMOS tube, the grid of the 11st NMOS tube, the 12nd
The drain electrode of NMOS tube, the grid of the 12nd NMOS tube, the grid of the 13rd NMOS tube, the grid of the 14th NMOS tube, the 16th
The grid of NMOS tube is connected with each other；The grid of 6th PMOS tube, the drain electrode of the 14th NMOS tube, the source electrode of the 7th PMOS tube,
The grid of seven PMOS tube, the 8th PMOS tube grid be connected with each other and be connected with the 8th capacitance one end；The leakage of 6th PMOS tube
Pole, the drain electrode of the 13rd NMOS tube, the grid interconnection of the grid of the tenth PMOS tube, the 17th NMOS tube；8th PMOS tube
Drain electrode, the drain electrode of the 7th PMOS tube, the grid of the 15th NMOS tube, the 16th NMOS tube drain electrode be connected with each other；14th
The source electrode of NMOS tube is connected with the drain electrode of the 15th NMOS tube；The source electrode phase of the drain electrode and the tenth PMOS tube of 9th PMOS tube
Even；The drain electrode of tenth PMOS tube, the drain electrode of the 17th NMOS tube, the grid of the 12nd PMOS tube, the 18th NMOS tube grid
It is connected with each other；The drain electrode of 11st PMOS tube is connected with the source electrode of the 12nd PMOS tube；The drain electrode and the tenth of 12nd PMOS tube
The drain electrode of eight NMOS tubes is connected with each other and is connected to output voltage terminal；The source electrode of 11st NMOS tube, the source of the 12nd NMOS tube
Pole, the source electrode of the 13rd NMOS tube, the source electrode of the 15th NMOS tube, the source electrode of the 16th NMOS tube, the 17th NMOS tube source
Pole, the source electrode of the 18th NMOS tube, the 8th capacitance the other end be connected with each other and be grounded.
5. the demodulator circuit according to claim 4 applied to passive ultra-high frequency radio frequency identification label chip, feature exists
In：All NMOS tubes and PMOS tube are operated in sub-threshold region.
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| CN106506419B (en) * | 2016-09-26 | 2019-11-05 | 深圳市中科先见医疗科技有限公司 | A kind of ASK demodulator |
| US10200163B1 (en) * | 2017-08-22 | 2019-02-05 | Texas Instruments Incorporated | Small and seamless carrier detector |
| CN110460313B (en) * | 2019-08-22 | 2020-08-18 | 湘潭大学 | Weak signal reading circuit for radiation detector |
| CN110912842B (en) * | 2019-11-13 | 2023-09-05 | 珠海一微半导体股份有限公司 | Envelope detection circuit |
| CN112994663A (en) * | 2021-02-07 | 2021-06-18 | 中国科学院微电子研究所 | Comparator and analog-to-digital converter |
| CN113259292B (en) * | 2021-05-28 | 2021-11-19 | 卓捷创芯科技（深圳）有限公司 | Differential input demodulation circuit for amplitude modulated wave envelope signals of radio frequency identification tags |
| CN114884467B (en) * | 2022-07-01 | 2022-09-27 | 浙江地芯引力科技有限公司 | Signal demodulation device and wireless charging equipment |
| CN115664470A (en) * | 2022-10-19 | 2023-01-31 | 安徽医科大学 | Low-power-consumption anti-noise UHF RFID demodulator circuit in medical Internet of things |
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| CN102810180A (en) * | 2012-07-04 | 2012-12-05 | 广州中大微电子有限公司 | ASK (Amplitude Shift Keying) demodulation circuit with wide demodulation range used for passive RFID (Radio Frequency Identification) label chips |
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| JP2010154501A (en) * | 2008-11-27 | 2010-07-08 | Sony Corp | Tuner module |
| US8115538B2 (en) * | 2009-07-10 | 2012-02-14 | Vasco Data Security, Inc. | Modulation and demodulation circuit |
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| CN101706879A (en) * | 2009-11-12 | 2010-05-12 | 武汉盛华微系统技术股份有限公司 | Uhf reader demodulation circuit |
| CN102810180A (en) * | 2012-07-04 | 2012-12-05 | 广州中大微电子有限公司 | ASK (Amplitude Shift Keying) demodulation circuit with wide demodulation range used for passive RFID (Radio Frequency Identification) label chips |
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