CN105577122A - High-linearity active double-balanced mixer - Google Patents
High-linearity active double-balanced mixer Download PDFInfo
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- CN105577122A CN105577122A CN201510953118.0A CN201510953118A CN105577122A CN 105577122 A CN105577122 A CN 105577122A CN 201510953118 A CN201510953118 A CN 201510953118A CN 105577122 A CN105577122 A CN 105577122A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
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- H03D7/1441—Balanced arrangements with transistors using field-effect transistors
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Abstract
The invention relates to a high-linearity active double-balanced mixer. The high-linearity active double-balanced mixer comprises a first level frequency mixing unit and a second level frequency mixing unit. The first level frequency mixing unit is arranged at one end of a passive capacitor C10 and a passive capacitor C11, and the second level frequency mixing unit is arranged at the other end of the passive capacitor C10 and the passive capacitor C11. The first level frequency mixing unit comprises a radio frequency positive signal branch, a tail current I1, a passive capacitor C1 and a radio frequency negative signal branch. The radio frequency positive signal branch and the radio frequency negative signal branch arranged at left and right sides are alternating-current symmetric with regard to the passive capacitor C1. The second level frequency mixing unit comprises NMOS transistors M5, M6, M7 and M8 forming a Kilbert frequency mixing structure. In this way, the high-linearity active double-balanced mixer provided by the invention is relatively high in linearity and has enough gain, and for the transistors, the transconductance is reduced, and the problem of voltage swing is avoided.
Description
Technical field
The present invention relates to the radio circuit field of semiconductor integrated circuit, more particularly, relate to a kind of high-linearity active double balanced mixer.
Background technology
The wireless communications market of quick growth makes wireless communication technology towards the future development of low cost, low-power consumption and high integration.In wireless application, portable set is in occupation of the very great share in market.The power consumption of particularity to integrated circuit of portable set proposes new requirement, and especially in medical science with automatically control application, battery becomes an important indicator of assessment properties of product.
After entering 90nm ~ 55nm technology node, power problems is particularly outstanding, and the power dissipation density in unit are sharply rises.Therefore, power consumption has become another key element after integrated circuit relaying tradition two key elements and speed and area.First must consider the power problems of product when designing, and carry out from system architecture to the series of optimum of bottom circuit design, to reduce circuit power consumption, increasing the service life.
Frequency mixer (Frequencymixer) is the one of non-linear radio communication circuit, frequency mixer is mixed into the output signal of one characteristic frequency the input signal of twice different frequency, it is the key modules of wireless communication system radio-frequency receiver front-end, is receiving and is playing critical effect in the process of down-conversion signal.Different receiver system frameworks, comprise heterodyne architecture, Direct-conversion structure and low intermediate frequency structure etc., all need an energy by the circuit module of radio frequency (RF) frequency down conversion to baseband intermediate frequency (IF) frequency, the function of this Key Circuit module is realized by frequency mixer, therefore, the gain, noise, the linearity etc. of frequency mixer all will directly affect the performance of whole receiver.
Those skilled in the art know that, a high performance frequency mixer not only needs to have enough good conversion gain, signal is effectively amplified in the process of down-conversion simultaneously, and needs to possess enough low noise and the linearity, make frequency mixer have superior performance contribution to whole system.So, in actual design, generally adopt compromise proposal, consider every factor, take into account the equilibrium of indices.
Refer to Fig. 1, the circuit shown in Fig. 1 is a kind of traditional active double balanced mixer (also known as Kilbert frequency mixer) structural representation.As shown in Figure 1, nmos pass transistor M1 and nmos pass transistor M2 is as the input pipe of radiofrequency signal, and its grid receives differential signal RF_n and RF_p from low noise amplifier (LowNoiseAmplifier is called for short LNA) respectively.Nmos pass transistor M3, nmos pass transistor M4, nmos pass transistor M5 and nmos pass transistor M6 are as the input pipe of intrinsic signals, the grid of nmos pass transistor M3, nmos pass transistor M6 receives from voltage-controlled oscillator (VoltageControlledOscillator, be called for short VCO) intrinsic signals LO_p, the grid of nmos pass transistor M4, nmos pass transistor M5 accepts the intrinsic signals LO_n from VCO.The drain electrode of nmos pass transistor M3 is connected with the drain electrode of nmos pass transistor M5, and export the low frequency signal IF_n after mixing, the drain electrode of nmos pass transistor M4 is connected with the drain electrode of nmos pass transistor M6, exports the low frequency signal IF_p after mixing.The source electrode of nmos pass transistor M1 is connected with inductance L 2, L3 respectively with the source electrode of nmos pass transistor M2, and by inductance L 1 ground connection.
But, for the frequency mixer shown in Fig. 1, in order to realize the higher linearity (usually weighing by IIP3 index) and enough gains, for input transistors (nmos pass transistor M1 and nmos pass transistor M2), need larger mutual conductance, it will be apparent to those skilled in the art that in metal-oxide-semiconductor, the size of mutual conductance reflects the control action of gate source voltage to drain current, on transfer characteristic curve, mutual conductance is slope of a curve, can cause the problem of voltage swing like this.
Therefore, be current industry urgent need to solve the problem.
Summary of the invention
The object of the present invention is to provide a kind of high-linearity active double balanced mixer being applicable to RF application.For achieving the above object, technical scheme of the present invention is as follows:
A kind of high-linearity active double balanced mixer, it comprises first order mixing unit and second level mixing unit; Described first order mixing unit is positioned at one end of passive capacitive C10 and passive capacitive C11, and second level mixing unit is positioned at the other end of passive capacitive C10 and passive capacitive C11 electric capacity; Described first order mixing unit comprises radio frequency forward signal branch road, tail current I1, passive capacitive C1 and radio frequency negative-going signal branch road; Described radio frequency forward signal branch road comprises the Input matching of nmos pass transistor M1, nmos pass transistor M3, the first load and radio frequency forward signal; The source electrode of described nmos pass transistor M1 is the input of radio frequency forward signal RF_n; Described radio frequency negative-going signal branch road comprises the Input matching of nmos pass transistor M2, nmos pass transistor M4, the second load and radio frequency negative-going signal; The source electrode of described nmos pass transistor M2 is the input of radio frequency negative-going signal RF_p; Wherein, described nmos pass transistor M1 and nmos pass transistor M2 common gate, described nmos pass transistor M3 and nmos pass transistor M4 common gate; The source electrode of described nmos pass transistor M1 and nmos pass transistor M2 is by described tail current I1 ground connection; Described nmos pass transistor M3 and nmos pass transistor M4 drains by electric capacity C1 ground connection; Described nmos pass transistor M1 is equivalent to a cathode-input amplifier after the Input matching of radio frequency forward signal, and radio frequency forward signal exports from the drain electrode of described nmos pass transistor M1 after being total to grid and amplifying; The signal that described nmos pass transistor M1 drain electrode exports is ac-coupled to the grid of described nmos pass transistor M3 by passive capacitive C6, simultaneously, the signal that nmos pass transistor M1 drain electrode exports enters nmos pass transistor M3 source electrode by passive inductance L5, final signal outputs to one end of electric capacity 10 from nmos pass transistor M3 drain electrode, and described nmos pass transistor M3 drains connected with power supply by described first load; Described nmos pass transistor M2 is equivalent to a cathode-input amplifier after the Input matching of radio frequency negative-going signal, and radio frequency negative-going signal exports from the drain electrode of described nmos pass transistor M2 after being total to grid and amplifying; The signal that described nmos pass transistor M2 drain electrode exports is ac-coupled to the grid of described nmos pass transistor M4 by passive capacitive C7, simultaneously, the signal that nmos pass transistor M2 drain electrode exports enters nmos pass transistor M4 source electrode by passive inductance L6, final signal outputs to one end of electric capacity 11 from nmos pass transistor M4 drain electrode, and described nmos pass transistor M4 drains connected with power supply by described second load; Described second level mixing unit comprises nmos pass transistor M5, nmos pass transistor M6, nmos pass transistor M7, nmos pass transistor M8, tail current I2, tail current I3, the 3rd load and the 4th load; Wherein, be transferred to the source of described nmos pass transistor M7 and M8 through the AC signal of ac coupling capacitor C10, the AC signal through ac coupling capacitor C11 is transferred to described nmos pass transistor M5 and M6 source, nmos pass transistor M5 and M6 source; Described nmos pass transistor M5 drain terminal is connected with M7 drain terminal, and described nmos pass transistor M6 drain terminal is connected with M8 drain terminal; Intrinsic forward signal LO_p inputs from described nmos pass transistor M5 and M8 grid end, intrinsic negative-going signal LO_n inputs from the grid end of described nmos pass transistor M6 and M7, described nmos pass transistor M5, M6, M7, M8 form Kilbert mixing structure, and the forward IF_p of final low intermediate frequency signal and negative sense IF_n transmits out from the drain terminal of described nmos pass transistor M8 and M5 respectively; Described nmos pass transistor M5 is connected with power supply by the 3rd load, and described nmos pass transistor M8 is connected with power supply by the 4th load, and the C10 other end of described electric capacity is by described tail current I2 ground connection, and the C11 other end of described electric capacity is by described tail current I3 ground connection.
Preferably, the Input matching of described radio frequency forward signal comprises passive capacitive C4 and passive inductance L3, described passive capacitive C4 is attempted by between described nmos pass transistor M1 grid and source class, and passive inductance L3 is serially connected between described nmos pass transistor M1 and M2 common gate point V1 and described nmos pass transistor M1 grid; The Input matching of described radio frequency negative-going signal comprises passive capacitive C5 and passive inductance L4, described passive capacitive C5 is attempted by between described nmos pass transistor M2 grid and source class, and passive inductance L4 is serially connected between the grid of described nmos pass transistor M1 and M2 common gate point V1 and described nmos pass transistor M2.
Preferably, the Input matching of described radio frequency forward signal also comprises passive capacitive C2 and passive resistance R1, described passive resistance R1 is serially connected between described passive inductance L3 and described nmos pass transistor M1 and M2 common gate point V1, described passive capacitive C2 one end is connected with described passive inductance L3 tie point with described passive resistance R1, other end ground connection; The Input matching of described radio frequency negative-going signal also comprises passive capacitive C3 and passive resistance R2, described passive resistance R2 is serially connected between described passive inductance L4 and described nmos pass transistor M1 and M2 common gate point V1, described passive capacitive C3 one end is connected with described passive inductance L4 tie point with described passive resistance R2, other end ground connection.
Preferably, described high-linearity active double balanced mixer also comprises passive inductance L1 and L2, described passive inductance L1 is serially connected between described nmos pass transistor M1 and described tail current I1, and described passive inductance L2 is serially connected between described nmos pass transistor M2 and described tail current I1.
Preferably, described high-linearity active double balanced mixer also comprises the first passive resistance and the second passive resistance, described first passive resistance is serially connected between described nmos pass transistor M1 and described tail current I1, and described second passive resistance is serially connected between described nmos pass transistor M2 and described tail current I1.
Preferably, described first load is passive inductance L7, and described second load is passive inductance L8, and described 3rd load is passive inductance L9, and described 4th load is passive inductance L10.
Preferably, described first load also comprises with described passive inductance L7 and the passive capacitive C8 connect, described second load also comprises with described passive inductance L8 and the passive capacitive C9 connect, described 3rd load also comprises with described passive inductance L9 and the passive capacitive C12 connect, and describedly also comprises with described passive inductance L10 and the passive capacitive C13 connect.
Preferably, described first load, the second load, the 3rd load and the 4th load are passive resistance.
Preferably, also comprise passive resistance R3 and passive resistance R4, described passive resistance R3 is serially connected between described nmos pass transistor M3 and described nmos pass transistor M3 and M4 common gate point V2, and described passive resistance R4 is serially connected between described nmos pass transistor M4 and described nmos pass transistor M3 and M4 common gate point V2.
Preferably, described tail current I1, I2, I3 are realized by nmos pass transistor, and realize by current mirror is folding.
As can be seen from technique scheme, high-linearity active double balanced mixer provided by the invention is divided into two-stage, both the higher linearity and enough gains had been realized, and for input transistors (nmos pass transistor M1 and nmos pass transistor M2), reduce mutual conductance, avoid the problem of voltage swing.
Accompanying drawing explanation
Circuit shown in Fig. 1 is a kind of traditional active double balanced mixer schematic diagram
Fig. 2 is the structure block diagram of high-linearity active double balanced mixer of the present invention
Fig. 3 is the schematic diagram of the linearity simulation curve of high-linearity active double balanced mixer of the present invention
Fig. 4 is the noise curve schematic diagram of high-linearity active double balanced mixer of the present invention
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
Refer to Fig. 2, Fig. 2 is the structure block diagram of high-linearity active double balanced mixer of the present invention.In an embodiment of the present invention, high-linearity active double balanced mixer can comprise first order mixing unit and second level mixing unit.As shown in the figure, first order mixing unit is positioned at one end of passive capacitive C10 and passive capacitive C11, and second level mixing unit is positioned at the other end of passive capacitive C10 and passive capacitive C11 electric capacity; Namely viewed from the position relationship arranged from figure, the left side of passive capacitive C10 and passive capacitive C11 is first order mixing unit, and the right of passive capacitive C10 and passive capacitive C11 electric capacity is second level mixing unit.
As shown in Figure 2, first order mixing unit can comprise radio frequency forward signal branch road, tail current I1, passive capacitive C1 and radio frequency negative-going signal branch road.The tail current I1 of first order mixing unit controls the power consumption of first order mixing unit.In an embodiment of the present invention, the source electrode of nmos pass transistor M1 is the input of radio frequency forward signal, and the source electrode of nmos pass transistor M2 is the input of radio frequency negative-going signal.
Radio frequency forward signal branch road can comprise the Input matching of nmos pass transistor M1, nmos pass transistor M3, the first load and radio frequency forward signal.The source electrode of nmos pass transistor M1 is the input of radio frequency forward signal RF_n.For radio frequency forward signal, nmos pass transistor M1 is equivalent to a cathode-input amplifier.Radio frequency negative-going signal branch road can comprise the Input matching of nmos pass transistor M2, nmos pass transistor M4, the second load and radio frequency negative-going signal; The source electrode of nmos pass transistor M2 is the input of radio frequency negative-going signal RF_p.For radio frequency negative-going signal, nmos pass transistor M2 is equivalent to a cathode-input amplifier.
In an embodiment of the present invention, first load can be passive electrical sense L7, and the second load can be passive electrical sense L8, preferably, first load can also comprise with passive inductance L7 and the passive capacitive C8 connect, and the second load can also comprise with passive inductance L8 and the passive capacitive C9 connect.
Wherein, nmos pass transistor M1 and nmos pass transistor M2 common gate, nmos pass transistor M3 and nmos pass transistor M4 common gate; The source electrode of nmos pass transistor M1 and nmos pass transistor M2 is by tail current I1 ground connection; Nmos pass transistor M3 and nmos pass transistor M4 drains by electric capacity C1 ground connection; Nmos pass transistor M1 is equivalent to a cathode-input amplifier after the Input matching of radio frequency forward signal, and radio frequency forward signal exports from the drain electrode of nmos pass transistor M1 after being total to grid and amplifying.The signal that this nmos pass transistor M1 drain electrode exports is ac-coupled to the grid of nmos pass transistor M3 by passive capacitive C6, simultaneously, the signal that nmos pass transistor M1 drain electrode exports enters nmos pass transistor M3 source electrode by passive inductance L5, and final signal outputs to one end of electric capacity C10 from nmos pass transistor M3 drain electrode; Nmos pass transistor M3 drains connected with power supply by the first load.
Nmos pass transistor M2 is equivalent to a cathode-input amplifier after the Input matching of radio frequency negative-going signal, and radio frequency negative-going signal exports from the drain electrode of nmos pass transistor M2 after being total to grid and amplifying; The signal that nmos pass transistor M2 drain electrode exports is ac-coupled to the grid of nmos pass transistor M4 by passive capacitive C7, simultaneously, the signal that nmos pass transistor M2 drain electrode exports enters nmos pass transistor M4 source electrode by passive inductance L6, final signal outputs to one end of electric capacity 11 from nmos pass transistor M4 drain electrode, and nmos pass transistor M4 drains connected with power supply by the second load.
It should be noted that, in an embodiment of the present invention, nmos pass transistor M3 and nmos pass transistor M4 drains by electric capacity C1 ground connection, this passive capacitive C1 is in order to virtual earth of increasing exchanges, two, left and right radio frequency forward signal branch road and radio frequency negative-going signal branch road can be made to show as at passive capacitive C1 place and to exchange symmetry, further increase the linearity of frequency mixer.This passive capacitive C1 is key element in this circuit, can not omit, otherwise can the appreciable impact linearity.In some embodiments of the invention, passive capacitive C1 also can substitute with passive resistance, and the resistance of passive resistance can be 5k ~ 20k ohm, preferred 10k ohm.
In one embodiment of the invention, the Input matching of radio frequency forward signal can comprise passive capacitive C4 and passive inductance L3, passive capacitive C4 is attempted by between nmos pass transistor M1 grid and source class, and passive inductance L3 is serially connected in nmos pass transistor M1 and between M2 common gate point V1 and nmos pass transistor M1 grid.The Input matching of radio frequency negative-going signal comprises passive capacitive C5 and passive inductance L4, passive capacitive C5 is attempted by between nmos pass transistor M2 grid and source class, and passive inductance L4 is serially connected in nmos pass transistor M1 and between M2 common gate point V1 and the grid of nmos pass transistor M2.
As shown in Figure 2, in another preferred embodiment of the present invention, frequently the Input matching of forward signal can also comprise passive capacitive C2 and passive resistance R1, passive resistance R1 is serially connected between passive inductance L3 and nmos pass transistor M1 and M2 common gate point V1, passive capacitive C2 one end is connected with passive inductance L3 tie point with passive resistance R1, other end ground connection.The Input matching of radio frequency negative-going signal can also comprise passive capacitive C3 and passive resistance R2, passive resistance R2 is serially connected between passive inductance L4 and nmos pass transistor M1 and M2 common gate point V1, passive capacitive C3 one end is connected with passive inductance L4 tie point with passive resistance R2, other end ground connection.
For increasing signal swing, the inductance L 1 of the signal path of left half branch road, the inductance L 2 of the signal path of right half branch road.As shown in Figure 2, passive inductance L1 is serially connected between nmos pass transistor M1 and tail current I1, and passive inductance L2 is serially connected between nmos pass transistor M2 and tail current I1.In other embodiments of the invention, passive inductance L1 can replace with the first passive resistance, passive inductance L2 can be replaced by the second passive resistance, namely the first passive resistance is serially connected between nmos pass transistor M1 and tail current I1, and the second passive resistance is serially connected between nmos pass transistor M2 and tail current I1.
Second level mixing unit comprises nmos pass transistor M5, nmos pass transistor M6, nmos pass transistor M7, the tail current I3 of tail current I2, M7, M8 of nmos pass transistor M8, M5, M6, the 3rd load and the 4th load, and tail current I2 and I3 controls the power consumption of second level frequency mixer.Wherein, be transferred to the source of nmos pass transistor M7 and M8 through the AC signal of ac coupling capacitor C10, the AC signal through ac coupling capacitor C11 is transferred to nmos pass transistor M5 and M6 source, nmos pass transistor M5 and M6 source; Nmos pass transistor M5 drain terminal is connected with M7 drain terminal, and nmos pass transistor M6 drain terminal is connected with M8 drain terminal; Intrinsic forward signal LO_p inputs from nmos pass transistor M5 and M8 grid end, intrinsic negative-going signal LO_n inputs from the grid end of nmos pass transistor M6 and M7, nmos pass transistor M5, M6, M7, M8 form Kilbert mixing structure, and forward IF_p and the negative sense IF_n of final low intermediate frequency signal transmit out from the drain terminal of nmos pass transistor M8 and M5 respectively; Nmos pass transistor M5 is connected with power supply by the 3rd load, and nmos pass transistor M8 is connected with power supply by the 4th load, and the C10 other end of electric capacity is by tail current I2 ground connection, and the other end of electric capacity C11 is by tail current I3 ground connection.
In some embodiments of the invention, the 3rd load can be passive electrical sense L9, and the 4th load can be passive electrical sense L10.Preferably, the 3rd load can also comprise with passive inductance L9 and the passive capacitive C12 connect, and the 4th load can also comprise with passive inductance L10 and the passive capacitive C13 connect.In other embodiments of the invention, the first load, the second load, the 3rd load and the 4th load can be all passive resistance.
As shown in Figure 2, for increasing the accuracy of bias voltage, high-linearity active double balanced mixer of the present invention can also comprise passive resistance R3 and passive resistance R4, passive resistance R3 is serially connected between nmos pass transistor M3 and nmos pass transistor M3 and M4 common gate point V2, and passive resistance R4 is serially connected between nmos pass transistor M4 and nmos pass transistor M3 and M4 common gate point V2.
In other embodiment more of the present invention, tail current I1, I2, I3 are realized by nmos pass transistor, and realize by current mirror is folding.The signal path of a left side half branch road of this first order mixing unit there are passive inductance L 1, passive inductance L5 and passive inductance L7, the signal path of right half branch road there are passive inductance L 2, passive inductance L6 and passive inductance L8, the object of these inductance makes the signal swing of first order mixing unit enough large, makes frequency mixer have the better linearity.
Refer to Fig. 3, Fig. 3 is the linearity simulation curve of high-linearity active double balanced mixer of the present invention, and wherein, abscissa is radio-frequency (RF) input power, and ordinate is low frequency power output.As shown in Figure 3, what curve 2 represented is three order harmonics data, and what curve 1 represented is single order harmonic data.As can be seen from Figure 3, the linearity (third order intermodulation point) of the high-linearity active double balanced mixer of the present invention's proposition is-3.2dBm.
Refer to Fig. 4, Fig. 4 is the noise curve schematic diagram of high-linearity active double balanced mixer of the present invention, and wherein, in figure, abscissa is for exporting low-IF frequency, and ordinate is noise factor.As can be seen from Figure 4, the noise curve (1.5MHz ~ 3.0MHz) under interested operating frequency of the high-linearity active double balanced mixer that the present invention proposes all is less than 5.2dB, namely meets system operation requirements.
Above-describedly be only the preferred embodiments of the present invention; described embodiment is also not used to limit scope of patent protection of the present invention; therefore the equivalent structure that every utilization specification of the present invention and accompanying drawing content are done changes, and in like manner all should be included in protection scope of the present invention.
Claims (10)
1. a high-linearity active double balanced mixer, is characterized in that, comprises first order mixing unit and second level mixing unit; Described first order mixing unit is positioned at one end of passive capacitive C10 and passive capacitive C11, and second level mixing unit is positioned at the other end of passive capacitive C10 and passive capacitive C11 electric capacity;
Described first order mixing unit comprises radio frequency forward signal branch road, tail current I1, passive capacitive C1 and radio frequency negative-going signal branch road;
Described radio frequency forward signal branch road comprises the Input matching of nmos pass transistor M1, nmos pass transistor M3, the first load and radio frequency forward signal; The source electrode of described nmos pass transistor M1 is the input of radio frequency forward signal RF_n;
Described radio frequency negative-going signal branch road comprises the Input matching of nmos pass transistor M2, nmos pass transistor M4, the second load and radio frequency negative-going signal; The source electrode of described nmos pass transistor M2 is the input of radio frequency negative-going signal RF_p; Wherein, described nmos pass transistor M1 and nmos pass transistor M2 common gate, described nmos pass transistor M3 and nmos pass transistor M4 common gate; The source electrode of described nmos pass transistor M1 and nmos pass transistor M2 is by described tail current I1 ground connection; Described nmos pass transistor M3 and nmos pass transistor M4 drains by electric capacity C1 ground connection;
Described nmos pass transistor M1 is equivalent to a cathode-input amplifier after the Input matching of radio frequency forward signal, and radio frequency forward signal exports from the drain electrode of described nmos pass transistor M1 after being total to grid and amplifying; The signal that described nmos pass transistor M1 drain electrode exports is ac-coupled to the grid of described nmos pass transistor M3 by passive capacitive C6, simultaneously, the signal that nmos pass transistor M1 drain electrode exports enters nmos pass transistor M3 source electrode by passive inductance L5, final signal outputs to one end of electric capacity 10 from nmos pass transistor M3 drain electrode, and described nmos pass transistor M3 drains connected with power supply by described first load;
Described nmos pass transistor M2 is equivalent to a cathode-input amplifier after the Input matching of radio frequency negative-going signal, and radio frequency negative-going signal exports from the drain electrode of described nmos pass transistor M2 after being total to grid and amplifying; The signal that described nmos pass transistor M2 drain electrode exports is ac-coupled to the grid of described nmos pass transistor M4 by passive capacitive C7, simultaneously, the signal that nmos pass transistor M2 drain electrode exports enters nmos pass transistor M4 source electrode by passive inductance L6, final signal outputs to one end of electric capacity 11 from nmos pass transistor M4 drain electrode, and described nmos pass transistor M4 drains connected with power supply by described second load;
Described second level mixing unit comprises nmos pass transistor M5, nmos pass transistor M6, nmos pass transistor M7, nmos pass transistor M8, tail current I2, tail current I3, the 3rd load and the 4th load; Wherein, be transferred to the source of described nmos pass transistor M7 and M8 through the AC signal of ac coupling capacitor C10, the AC signal through ac coupling capacitor C11 is transferred to described nmos pass transistor M5 and M6 source, nmos pass transistor M5 and M6 source; Described nmos pass transistor M5 drain terminal is connected with M7 drain terminal, and described nmos pass transistor M6 drain terminal is connected with M8 drain terminal; Intrinsic forward signal LO_p inputs from described nmos pass transistor M5 and M8 grid end, intrinsic negative-going signal LO_n inputs from the grid end of described nmos pass transistor M6 and M7, described nmos pass transistor M5, M6, M7, M8 form Kilbert mixing structure, and the forward IF_p of final low intermediate frequency signal and negative sense IF_n transmits out from the drain terminal of described nmos pass transistor M8 and M5 respectively; Described nmos pass transistor M5 is connected with power supply by the 3rd load, and described nmos pass transistor M8 is connected with power supply by the 4th load, and the C10 other end of described electric capacity is by described tail current I2 ground connection, and the C11 other end of described electric capacity is by described tail current I3 ground connection.
2. high-linearity active double balanced mixer according to claim 1, it is characterized in that, the Input matching of described radio frequency forward signal comprises passive capacitive C4 and passive inductance L3, described passive capacitive C4 is attempted by between described nmos pass transistor M1 grid and source class, and passive inductance L3 is serially connected between described nmos pass transistor M1 and M2 common gate point v1 and described nmos pass transistor M1 grid; The Input matching of described radio frequency negative-going signal comprises passive capacitive C5 and passive inductance L4, described passive capacitive C5 is attempted by between described nmos pass transistor M2 grid and source class, and passive inductance L4 is serially connected between the grid of described nmos pass transistor M1 and M2 common gate point V1 and described nmos pass transistor M2.
3. high-linearity active double balanced mixer according to claim 2, it is characterized in that, the Input matching of described radio frequency forward signal also comprises passive capacitive C2 and passive resistance R1, described passive resistance R1 is serially connected between described passive inductance L3 and described nmos pass transistor M1 and M2 common gate point V1, described passive capacitive C2 one end is connected with described passive inductance L3 tie point with described passive resistance R1, other end ground connection; The Input matching of described radio frequency negative-going signal also comprises passive capacitive C3 and passive resistance R2, described passive resistance R2 is serially connected between described passive inductance L4 and described nmos pass transistor M1 and M2 common gate point V1, described passive capacitive C3 one end is connected with described passive inductance L4 tie point with described passive resistance R2, other end ground connection.
4. high-linearity active double balanced mixer according to claim 1, it is characterized in that, also comprise passive inductance L1 and L2, described passive inductance L1 is serially connected between described nmos pass transistor M1 and described tail current I1, and described passive inductance L2 is serially connected between described nmos pass transistor M2 and described tail current I1.
5. high-linearity active double balanced mixer according to claim 1, it is characterized in that, also comprise the first passive resistance and the second passive resistance, described first passive resistance is serially connected between described nmos pass transistor M1 and described tail current I1, and described second passive resistance is serially connected between described nmos pass transistor M2 and described tail current I1.
6. high-linearity active double balanced mixer according to claim 1, is characterized in that, described first load is passive inductance L7, and described second load is passive inductance L8, and described 3rd load is passive inductance L9, and described 4th load is passive inductance L10.
7. high-linearity active double balanced mixer according to claim 6, it is characterized in that, described first load also comprises with described passive inductance L7 and the passive capacitive C8 connect, described second load also comprises with described passive inductance L8 and the passive capacitive C9 connect, described 3rd load also comprises with described passive inductance L9 and the passive capacitive C12 connect, and describedly also comprises with described passive inductance L10 and the passive capacitive C13 connect.
8. high-linearity active double balanced mixer according to claim 1, is characterized in that, described first load, the second load, the 3rd load and the 4th load are passive resistance.
9. high-linearity active double balanced mixer according to claim 1, it is characterized in that, also comprise passive resistance R3 and passive resistance R4, described passive resistance R3 is serially connected between described nmos pass transistor M3 and described nmos pass transistor M3 and M4 common gate point V2, and described passive resistance R4 is serially connected between described nmos pass transistor M4 and described nmos pass transistor M3 and M4 common gate point V2.
10. high-linearity active double balanced mixer according to claim 1, is characterized in that, described tail current I1, I2, I3 are realized by nmos pass transistor, and realizes by current mirror is folding.
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| CN201510953118.0A CN105577122B (en) | 2015-12-17 | 2015-12-17 | A kind of high-linearity active double balanced mixer |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106341087A (en) * | 2016-08-30 | 2017-01-18 | 吴韵秋 | Frequency mixer |
| CN107231129A (en) * | 2017-05-12 | 2017-10-03 | 成都通量科技有限公司 | Harmonic controling CMOS frequency mixers based on transformer device structure |
| CN108964614A (en) * | 2018-06-29 | 2018-12-07 | 南通朝旭环保科技有限公司 | Mixer |
| CN109361361A (en) * | 2018-12-07 | 2019-02-19 | 中国电子科技集团公司第五十四研究所 | A kind of ultra wide band high-linearity up-converter circuit |
Families Citing this family (1)
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| CN110535441A (en) * | 2019-09-06 | 2019-12-03 | 电子科技大学 | A kind of high-isolation broadband millimeter-wave frequency mixer applied to 5G communication |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6510314B1 (en) * | 2000-09-08 | 2003-01-21 | Visteon Global Technologies, Inc. | Mixer circuit with output stage for implementation on integrated circuit |
| CN101183878A (en) * | 2007-12-20 | 2008-05-21 | 复旦大学 | Low-power consumption wireless receiver radio frequency front end circuit |
| CN102075145A (en) * | 2011-01-11 | 2011-05-25 | 东南大学 | High-linearity folding image mixer |
| US20130143511A1 (en) * | 2011-12-06 | 2013-06-06 | Tensorcom, Inc. | Method and Apparatus of an Input Resistance of a Passive Mixer to Broaden the Input Matching Bandwidth of a Common Source/Gate LNA |
-
2015
- 2015-12-17 CN CN201510953118.0A patent/CN105577122B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6510314B1 (en) * | 2000-09-08 | 2003-01-21 | Visteon Global Technologies, Inc. | Mixer circuit with output stage for implementation on integrated circuit |
| CN101183878A (en) * | 2007-12-20 | 2008-05-21 | 复旦大学 | Low-power consumption wireless receiver radio frequency front end circuit |
| CN102075145A (en) * | 2011-01-11 | 2011-05-25 | 东南大学 | High-linearity folding image mixer |
| US20130143511A1 (en) * | 2011-12-06 | 2013-06-06 | Tensorcom, Inc. | Method and Apparatus of an Input Resistance of a Passive Mixer to Broaden the Input Matching Bandwidth of a Common Source/Gate LNA |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106341087A (en) * | 2016-08-30 | 2017-01-18 | 吴韵秋 | Frequency mixer |
| CN106341087B (en) * | 2016-08-30 | 2019-04-12 | 成都通量科技有限公司 | A kind of frequency mixer |
| CN107231129A (en) * | 2017-05-12 | 2017-10-03 | 成都通量科技有限公司 | Harmonic controling CMOS frequency mixers based on transformer device structure |
| CN108964614A (en) * | 2018-06-29 | 2018-12-07 | 南通朝旭环保科技有限公司 | Mixer |
| CN109361361A (en) * | 2018-12-07 | 2019-02-19 | 中国电子科技集团公司第五十四研究所 | A kind of ultra wide band high-linearity up-converter circuit |
| CN109361361B (en) * | 2018-12-07 | 2023-12-22 | 中国电子科技集团公司第五十四研究所 | Ultra-wideband high-linearity up-conversion circuit |
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