CN105577122B - A kind of high-linearity active double balanced mixer - Google Patents
A kind of high-linearity active double balanced mixer Download PDFInfo
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- CN105577122B CN105577122B CN201510953118.0A CN201510953118A CN105577122B CN 105577122 B CN105577122 B CN 105577122B CN 201510953118 A CN201510953118 A CN 201510953118A CN 105577122 B CN105577122 B CN 105577122B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1441—Balanced arrangements with transistors using field-effect transistors
Abstract
The present invention relates to a kind of high-linearity active double balanced mixers, it includes first order mixing unit and first order mixing unit, first order mixing unit is located at one end of passive capacitive C10 and passive capacitive C11, and second level mixing unit is located at the other end of passive capacitive C10 and passive capacitive C11 capacitances；First order mixing unit includes radio frequency forward signal branch, tail current I1, passive capacitive C1 and radio frequency negative-going signal branch, radio frequency forward signal branch is shown as exchanging at passive capacitive C1 symmetrically with radio frequency negative-going signal branch or so two branches, and second level mixing unit includes forming Kilbert by NMOS transistor M5, M6, M7, M8 to be mixed structure.Therefore, high-linearity active double balanced mixer provided by the invention had both realized the higher linearity and enough gains, and for input transistors, the problem of reducing mutual conductance, avoid voltage swing.
Description
Technical field
The present invention relates to the radio circuit fields of semiconductor integrated circuit, have more specifically to a kind of high linearity
Source double balanced mixer.
Background technology
The wireless communications market of rapid growth makes wireless communication technique towards low cost, the side of low-power consumption and high integration
To development.In wireless application, very big share of the portable device in occupation of market.The particularity of portable device is to integrated electricity
The power consumption on road proposes new requirement, especially becomes assessment with application field, battery is automatically controlled in medicine and produces
One important indicator of moral character energy.
After entering 90nm~55nm technology nodes, power problems are especially prominent, and the power dissipation density on unit area is drastically
Rise.Therefore, power consumption has become another key element after the traditional two elements i.e. speed and area of integrated circuit relaying.
The power problems of product must be first considered in design, and are carried out from system architecture to the series of optimum of bottom circuit design
To reduce circuit power consumption, prolong the service life.
Frequency mixer (Frequency mixer) is one kind of non-linear radio communication circuit, and frequency mixer is twice different frequencies
The input signal of rate is mixed into the output signal of one of specific frequency, is the key that wireless communication system radio-frequency receiver front-end
Module plays critical effect during receiving and down-conversion signal.Different receiver system frameworks, including heterodyne
Structure, Direct-conversion structure and low intermediate frequency structure etc., be required for one can be by radio frequency (RF) frequency down conversion to baseband intermediate frequency
(IF) function of the circuit module of frequency, this Key Circuit module is realized that therefore, the gain of frequency mixer is made an uproar by frequency mixer
Sound, linearity etc. will all directly affect the performance of entire receiver.
It will be apparent to those skilled in the art that a high performance frequency mixer does not need only to have conversion gain good enough, make
It obtains signal during down coversion simultaneously effectively to be amplified, and needs to have sufficiently low noise and the linearity so that is mixed
Frequency device has superior performance contribution to whole system.So in actual design, compromise proposal is generally used, is considered
Every factor takes into account the equilibrium of indices.
Referring to Fig. 1, circuit shown in FIG. 1 is a kind of (the also known as Kilbert mixing of traditional active double balanced mixer
Device) structural schematic diagram.As shown in Figure 1, the input pipe of NMOS transistor M1 and NMOS transistor M2 as radiofrequency signal, grid
Differential signal RF_n and RF_p from low-noise amplifier (Low Noise Amplifier, abbreviation LNA) are received respectively.
The input pipe of NMOS transistor M3, NMOS transistor M4, NMOS transistor M5 and NMOS transistor M6 as intrinsic signals,
The grid reception of NMOS transistor M3, NMOS transistor M6 come from voltage-controlled oscillator (Voltage Controlled
Oscillator, abbreviation VCO) intrinsic signals LO_p, NMOS transistor M4, NMOS transistor M5 grid receive come from VCO
Intrinsic signals LO_n.The drain electrode of NMOS transistor M3 is connected with the drain electrode of NMOS transistor M5, the low frequency letter after output mixing
Number IF_n, the drain electrode of NMOS transistor M4 are connected with the drain electrode of NMOS transistor M6, the low frequency signal IF_p after output mixing.
The source electrode of NMOS transistor M1 and the source electrode of NMOS transistor M2 are connected with inductance L2, L3 respectively, and are grounded by inductance L1.
However, for frequency mixer shown in FIG. 1, in order to realize that the higher linearity (is usually weighed with IIP3 indexs
Amount) and enough gains, needed for input transistors (NMOS transistor M1 and NMOS transistor M2) it is larger across
It leads, it will be apparent to those skilled in the art that in metal-oxide-semiconductor, the size of mutual conductance reflects control action of the gate source voltage to drain current,
On transfer characteristic curve, mutual conductance is slope of a curve, the problem of causing voltage swing in this way.
Therefore, it is current industry urgent need to solve the problem.
Invention content
The purpose of the present invention is to provide a kind of high-linearity active double balanced mixers suitable for RF application.For reality
Existing above-mentioned purpose, technical scheme is as follows：
A kind of high-linearity active double balanced mixer comprising first order mixing unit and second level mixing unit；Institute
One end that first order mixing unit is located at passive capacitive C10 and passive capacitive C11 is stated, second level mixing unit is located at passive capacitive
The other end of C10 and passive capacitive C11 capacitances；The first order mixing unit include radio frequency forward signal branch, tail current I1,
Passive capacitive C1 and radio frequency negative-going signal branch；The radio frequency forward signal branch includes NMOS transistor M1, NMOS transistor
M3, the first load and the input of radio frequency forward signal matching；The source electrode of the NMOS transistor M1 is radio frequency forward signal RF_n
Input terminal；The radio frequency negative-going signal branch includes that NMOS transistor M2, NMOS transistor M4, the second load and radio frequency are negative
It is matched to the input of signal；The source electrode of the NMOS transistor M2 is the input terminal of radio frequency negative-going signal RF_p；Wherein, described
NMOS transistor M1 and NMOS transistor M2 common gates, the NMOS transistor M3 and NMOS transistor M4 common gates；It is described
The source electrode of NMOS transistor M1 and NMOS transistor M2 are grounded by the tail current I1；The NMOS transistor M3 and NMOS is brilliant
Body pipe M4 source electrodes are grounded by capacitance C1；The NMOS transistor M1 is equivalent to one after the input of radio frequency forward signal matching
A cathode-input amplifier, radio frequency forward signal export after grid amplification altogether from the drain electrode of the NMOS transistor M1；It is described
The signal of NMOS transistor M1 drain electrode outputs is ac-coupled to the grid of the NMOS transistor M3 by passive capacitive C6, together
When, the signal of NMOS transistor M1 drain electrode output enters NMOS transistor M3 source electrodes by passive inductance L5, final signal from
NMOS transistor M3 drain electrodes are output to one end of capacitance C10, and the NMOS transistor M3 drain electrodes are by first load with electricity
Source is connected；The NMOS transistor M2 is equivalent to a cathode-input amplifier after the input of radio frequency negative-going signal matching, and radio frequency is negative
It is exported to signal from the drain electrode of the NMOS transistor M2 after grid amplification altogether；The NMOS transistor M2 drain electrodes output
Signal the grid of the NMOS transistor M4 is ac-coupled to by passive capacitive C7, meanwhile, NMOS transistor M2 drain electrodes are defeated
The signal gone out enters NMOS transistor M4 source electrodes by passive inductance L6, and final signal is output to from the M4 drain electrodes of NMOS transistors
One end of capacitance C11, the NMOS transistor M4 drain electrodes are connected by second load with power supply；The second level mixing is single
Member include NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, NMOS transistor M8, tail current I2, tail current I3,
Third loads and the 4th load；Wherein, by the AC signal of ac coupling capacitor C10 be transferred to the NMOS transistor M7 with
The source of M8 is transferred to the NMOS transistor M5 and M6 sources, NMOS crystal by the AC signal of ac coupling capacitor C11
Pipe M5 and M6 sources；The NMOS transistor M5 drain terminals are connected with M7 drain terminals, the NMOS transistor M6 drain terminals and M8 drain terminal phases
Even；Intrinsic forward signal LO_p is inputted from the NMOS transistor M5 and M8 grid ends, and intrinsic negative-going signal LO_n is from the NMOS
The grid end of transistor M6 and M7 inputs, and described NMOS transistor M5, M6, M7, M8 form Kilbert and be mixed structure, it is final it is low in
The positive IF_p and negative sense IF_n of frequency signal transmit out from the drain terminal of the NMOS transistor M8 and M5 respectively；The NMOS is brilliant
Body pipe M5 is loaded by third to be connected with power supply, and the NMOS transistors M8 is connected by the 4th load with power supply, the capacitance
The other end of C10 is grounded by the tail current I3, and the other end of the capacitance C11 is grounded by the tail current I2.
Preferably, the input matching of the radio frequency forward signal includes passive capacitive C2 and passive inductance L3, described passive
Capacitance C2 is attempted by between the NMOS transistor M1 grids and source level, passive inductance L3 be serially connected in the NMOS transistor M1 and
Between M2 common gates point V1 and the NMOS transistor M1 grids；The input matching of the radio frequency negative-going signal includes passive electrical
Hold C3 and passive inductance L4, the passive capacitive C3 is attempted by between the NMOS transistor M2 grids and source level, passive inductance
L4 is serially connected between the NMOS transistor M1 and M2 common gates point V1 and the grid of the NMOS transistor M2.
Preferably, the input matching of the radio frequency forward signal further includes passive capacitive C4 and passive resistance R1, the nothing
Source resistance R1 is serially connected between the passive inductance L3 and the NMOS transistor M1 and M2 common gate points V1, the passive electrical
Hold the one end C4 with the passive resistance R1 and the passive inductance L3 tie points to be connected, other end ground connection；The radio frequency negative sense letter
Number input matching further include passive capacitive C5 and passive resistance R2, the passive resistance R2 be serially connected in the passive inductance L4 with
Between the NMOS transistor M1 and M2 common gate points V1, the one end the passive capacitive C5 and the passive resistance R2 and the nothing
Source inductance L4 tie points are connected, other end ground connection.
Preferably, the high-linearity active double balanced mixer further includes passive inductance L1 and L2, the passive inductance
L1 is serially connected between the NMOS transistor M1 source electrodes and the tail current I1, and it is brilliant that the passive inductance L2 is serially connected in the NMOS
Between body pipe M2 source electrodes and the tail current I1.
Preferably, the high-linearity active double balanced mixer further includes the first passive resistance and the second passive resistance,
First passive resistance is serially connected between the NMOS transistor M1 source electrodes and the tail current I1, second passive electrical
Resistance is serially connected between the NMOS transistor M2 source electrodes and the tail current I1.
Preferably, first load is passive inductance L7, and second load is passive inductance L8, the third load
For passive inductance L9, the 4th load is passive inductance L10.
Preferably, first load further include with the passive inductance L7 and the passive capacitive C8 that connects, described second is negative
Load further include with the passive inductance L8 and the passive capacitive C9 that connects, the third load further include with the passive inductance L9 simultaneously
The passive capacitive C12 connect, it is described to further include and the passive inductance L10 and the passive capacitive C13 that connects.
Preferably, first load, the second load, third load and the 4th load are passive resistance.
Preferably, further include that passive resistance R3 and passive resistance R4, the passive resistance R3 are serially connected in the NMOS crystal
Between the pipe M3 and NMOS transistor M3 and M4 common gate points V2, the passive resistance R4 is serially connected in the NMOS transistor M4
Between the NMOS transistor M3 and M4 common gate points V2.
Preferably, described tail current I1, I2, I3 are realized by NMOS transistor, and are folded and realized by current mirror.
It can be seen from the above technical proposal that high-linearity active double balanced mixer provided by the invention is divided into two-stage,
Both the higher linearity and enough gains had been realized, and input transistors (NMOS transistor M1 and NMOS transistor M2) had been come
The problem of saying, reducing mutual conductance, avoid voltage swing.
Description of the drawings
Circuit shown in FIG. 1 is a kind of traditional active double balanced mixer schematic diagram
Fig. 2 is the structure block diagram of high-linearity active double balanced mixer of the present invention
Fig. 3 is the schematic diagram of the linearity simulation curve of high-linearity active double balanced mixer of the present invention
Fig. 4 is the noise curve schematic diagram of high-linearity active double balanced mixer of the present invention
Specific implementation mode
Below in conjunction with the accompanying drawings, the specific implementation mode of the present invention is described in further detail.
Referring to Fig. 2, Fig. 2 is the structure block diagram of high-linearity active double balanced mixer of the present invention.In this hair
In bright embodiment, high-linearity active double balanced mixer may include first order mixing unit and second level mixing unit.
As shown, first order mixing unit is located at one end of passive capacitive C10 and passive capacitive C11, second level mixing unit is located at
The other end of passive capacitive C10 and passive capacitive C11 capacitances；I.e. in terms of the position relationship arranged in figure, passive capacitive C10 and nothing
The left side of source capacitance C11 is first order mixing unit, is that the second level is mixed on the right of passive capacitive C10 and passive capacitive C11 capacitances
Frequency unit.
As shown in Fig. 2, first order mixing unit may include radio frequency forward signal branch, tail current I1, passive capacitive C1
With radio frequency negative-going signal branch.The tail current I1 of first order mixing unit controls the power consumption of first order mixing unit.In this hair
In bright embodiment, the source electrode of NMOS transistor M1 is the input terminal of radio frequency forward signal, and the source electrode of NMOS transistor M2 is to penetrate
The input terminal of frequency negative-going signal.
Radio frequency forward signal branch may include that NMOS transistor M1, NMOS transistor M3, the first load and radio frequency are positive
The input of signal matches.The source electrode of NMOS transistor M1 is the input terminal of radio frequency forward signal RF_n.For radio frequency forward signal
For, NMOS transistor M1 is equivalent to a cathode-input amplifier.Radio frequency negative-going signal branch may include NMOS transistor M2,
NMOS transistor M4, the second load and the input of radio frequency negative-going signal matching；The source electrode of NMOS transistor M2 is radio frequency negative sense letter
The input terminal of number RF_p.For radio frequency negative-going signal, NMOS transistor M2 is equivalent to a cathode-input amplifier.
In an embodiment of the present invention, the first load can be passive inductance L7, and the second load can be passive inductance L8,
Preferably, the first load can also include that can also include and nothing with passive inductance L7 and the passive capacitive C8 that connects, the second load
Source inductance L8 and the passive capacitive C9 connect.
Wherein, NMOS transistor M1 and NMOS transistor M2 common gates, NMOS transistor M3 and NMOS transistor M4 are total to grid
Pole；The source electrode of NMOS transistor M1 and NMOS transistor M2 are grounded by tail current I1；NMOS transistor M3 and NMOS transistor
M4 source electrodes are grounded by capacitance C1；NMOS transistor M1 is equivalent to a total grid amplification after the input of radio frequency forward signal matching
Device, radio frequency forward signal export after grid amplification altogether from the drain electrode of NMOS transistor M1.NMOS transistor M1 drain electrodes are defeated
The signal gone out is ac-coupled to the grid of NMOS transistor M3 by passive capacitive C6, meanwhile, NMOS transistor M1 drain electrode outputs
Signal NMOS transistor M3 source electrodes are entered by passive inductance L5, final signal is output to capacitance from NMOS transistor M3 drain electrodes
One end of C10；NMOS transistor M3 drain electrodes are connected by the first load with power supply.
NMOS transistor M2 is equivalent to a cathode-input amplifier, radio frequency negative sense letter after the input of radio frequency negative-going signal matching
Number by altogether grid amplification after from the drain electrode of NMOS transistor M2 output；The signal of NMOS transistors M2 drain electrode outputs passes through nothing
Source capacitance C7 is ac-coupled to the grid of NMOS transistor M4, meanwhile, the signal that NMOS transistor M2 drain electrodes export passes through passive
Inductance L6 enters NMOS transistor M4 source electrodes, and final signal is output to one end of capacitance C11 from NMOS transistor M4 drain electrodes,
NMOS transistor M4 drain electrodes are connected by the second load with power supply.
It should be noted that in an embodiment of the present invention, NMOS transistor M3 and NMOS transistor M4 source electrodes pass through electricity
Hold C1 ground connection, passive capacitive C1 is can to make the radio frequency forward signal branch of left and right two for virtual earth of increasing exchanges and penetrate
Frequency negative-going signal branch shows as exchange symmetrically at passive capacitive C1, further increases the linearity of frequency mixer.This is passive
Capacitance C1 is key element in this circuit, cannot omit, otherwise can significantly affect the linearity.In some embodiments of the present invention
In, passive capacitive C1 can also be substituted with passive resistance, and the resistance value of passive resistance can be 5k~20k ohm, preferably 10k ohm.
In one embodiment of the invention, the input matching of radio frequency forward signal may include passive capacitive C4 and nothing
Source inductance L3, passive capacitive C4 are attempted by between NMOS transistor M1 grids and source level, and passive inductance L3 is serially connected in NMOS crystal
Between pipe M1 and M2 common gate point V1 and NMOS transistor M1 grids.The input matching of radio frequency negative-going signal includes passive capacitive
C5 and passive inductance L4, passive capacitive C5 are attempted by between NMOS transistor M2 grids and source level, and passive inductance L4 is serially connected in
Between NMOS transistor M1 and M2 common gate point V1 and the grid of NMOS transistor M2.
As shown in Fig. 2, in another preferred embodiment of the present invention, the input matching of frequency forward signal can also wrap
Passive capacitive C2 and passive resistance R1 are included, passive resistance R1 is serially connected in passive inductance L3 and NMOS transistor M1 and M2 common gate
Between point V1, the one end passive capacitive C2 is connected with passive resistance R1 and passive inductance L3 tie points, other end ground connection.Radio frequency negative sense
Signal input matching can also include passive capacitive C3 and passive resistance R2, passive resistance R2 be serially connected in passive inductance L4 with
Between NMOS transistor M1 and M2 common gate point V1, the one end passive capacitive C3 and passive resistance R2 and passive inductance L4 tie points
It is connected, other end ground connection.
To increase signal swing, the inductance L1 of the signal path of left half branch, the inductance L2 of the signal path of right half branch.
As shown in Fig. 2, passive inductance L1 is serially connected between NMOS transistor M1 and tail current I1, passive inductance L2 is serially connected in NMOS crystalline substances
Between body pipe M2 and tail current I1.In other embodiments of the invention, passive inductance L1 can be replaced with the first passive resistance,
Passive inductance L2 can be replaced by the second passive resistance, i.e., the first passive resistance is serially connected in NMOS transistor M1 and tail current I1
Between, the second passive resistance is serially connected between NMOS transistor M2 and tail current I1.
Second level mixing unit includes NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, NMOS transistor
Tail current I3, third load and the 4th load of tail current I2, M7, M8 of M8, M5, M6, tail current I2 and I3 control second
The power consumption of grade frequency mixer.Wherein, the source of NMOS transistor M7 and M8 is transferred to by the AC signal of ac coupling capacitor C10
End, NMOS transistor M5 and M6 sources, NMOS transistor M5 and M6 are transferred to by the AC signal of ac coupling capacitor C11
Source；NMOS transistor M5 drain terminals are connected with M7 drain terminals, and NMOS transistor M6 drain terminals are connected with M8 drain terminals；Intrinsic forward signal
LO_p is inputted from NMOS transistor M5 and M8 grid ends, and intrinsic negative-going signal LO_n is inputted from the grid end of NMOS transistor M6 and M7,
NMOS transistor M5, M6, M7, M8 form Kilbert and are mixed structure, the positive IF_p and negative sense IF_n of final low intermediate frequency signal
It transmits out from the drain terminal of NMOS transistor M8 and M5 respectively；NMOS transistor M5 is loaded by third to be connected with power supply, NMOS
Transistor M8 is connected by the 4th load with power supply, and the other end of capacitance C10 is grounded by tail current I2, and capacitance C11's is another
End is grounded by tail current I3.
In some embodiments of the invention, third load can be passive inductance L9, and the 4th load can be passive electrical
Feel L10.Preferably, third load can also include that can also be wrapped with passive inductance L9 and the passive capacitive C12 that connects, the 4th load
It includes and passive inductance L10 and the passive capacitive C13 that connects.In other embodiments of the invention, the first load, the second load, the
Three loads and the 4th load all can be passive resistances.
As shown in Fig. 2, to increase the accuracy of bias voltage, high-linearity active double balanced mixer of the present invention can be with
Including passive resistance R3 and passive resistance R4, it is total with NMOS transistor M3 and M4 that passive resistance R3 is serially connected in NMOS transistors M3
Between grid point V2, passive resistance R4 is serially connected between NMOS transistor M4 and NMOS transistor M3 and M4 common gate point V2.
In some other embodiments of the present invention, tail current I1, I2, I3 are realized by NMOS transistor, and pass through electric current
Mirror, which folds, to be realized.There are passive inductance L1, passive inductance L5 and nothing on the signal path of half branch of a left side of the first order mixing unit
Source inductance L7 has passive inductance L2, passive inductance L6 and passive inductance L8 on the signal path of right half branch, these inductance
Purpose is to make the signal swing of first order mixing unit sufficiently large so that frequency mixer has the better linearity.
Referring to Fig. 3, Fig. 3 is the linearity simulation curve of high-linearity active double balanced mixer of the present invention, wherein horizontal
Coordinate is RF input power, and ordinate is low frequency output power.As shown in figure 3, the expression of curve 2 is three order harmonics data,
What curve 1 indicated is single order harmonic data.From figure 3, it can be seen that high-linearity active double balanced mixer proposed by the present invention
The linearity (third order intermodulation point) be -3.2dBm.
Referring to Fig. 4, Fig. 4 is the noise curve schematic diagram of high-linearity active double balanced mixer of the present invention, wherein figure
Middle abscissa is output low-IF frequency, and ordinate is noise coefficient.From fig. 4, it can be seen that high linearity proposed by the present invention
The noise curve of active double balanced mixer (1.5MHz~3.0MHz) under interested working frequency is respectively less than 5.2dB, i.e.,
Meet system operation requirements.
Above-described to be merely a preferred embodiment of the present invention, the embodiment is not to be protected to limit the patent of the present invention
Range, therefore equivalent structure variation made by every specification and accompanying drawing content with the present invention are protected, similarly should be included in
In protection scope of the present invention.
Claims (10)
1. a kind of high-linearity active double balanced mixer, which is characterized in that be mixed including first order mixing unit and the second level
Unit；The first order mixing unit is located at one end of passive capacitive C10 and passive capacitive C11, and second level mixing unit is located at
The other end of passive capacitive C10 and passive capacitive C11 capacitances；
The first order mixing unit includes radio frequency forward signal branch, tail current I1, passive capacitive C1 and radio frequency negative-going signal
Branch；
The radio frequency forward signal branch includes NMOS transistor M1, NMOS transistor M3, the first load and radio frequency forward signal
Input matching；The source electrode of the NMOS transistor M1 is the input terminal of radio frequency forward signal RF_n；
The radio frequency negative-going signal branch includes NMOS transistor M2, NMOS transistor M4, the second load and radio frequency negative-going signal
Input matching；The source electrode of the NMOS transistor M2 is the input terminal of radio frequency negative-going signal RF_p；Wherein, the NMOS crystal
Pipe M1 and NMOS transistor M2 common gates, the NMOS transistor M3 and NMOS transistor M4 common gates；The NMOS transistor
The source electrode of M1 and NMOS transistor M2 are grounded by the tail current I1；The NMOS transistor M3 and NMOS transistor M4 source electrodes
It is grounded by capacitance C1；
The NMOS transistor M1 is equivalent to a cathode-input amplifier, radio frequency forward direction letter after the input of radio frequency forward signal matching
Number by altogether grid amplification after from the drain electrode of the NMOS transistor M1 output；The signal of the NMOS transistor M1 drain electrodes output
The grid of the NMOS transistor M3 is ac-coupled to by passive capacitive C6, meanwhile, the letter of NMOS transistor M1 drain electrode outputs
Number NMOS transistor M3 source electrodes are entered by passive inductance L5, final signal is output to capacitance C10 from NMOS transistor M3 drain electrodes
One end, NMOS transistor M3 drain electrode is connected by first load with power supply；
The NMOS transistor M2 is equivalent to a cathode-input amplifier, radio frequency negative sense letter after the input of radio frequency negative-going signal matching
Number by altogether grid amplification after from the drain electrode of the NMOS transistor M2 output；The signal of the NMOS transistor M2 drain electrodes output
The grid of the NMOS transistor M4 is ac-coupled to by passive capacitive C7, meanwhile, the letter of NMOS transistor M2 drain electrode outputs
Number NMOS transistor M4 source electrodes are entered by passive inductance L6, final signal is output to capacitance C11 from NMOS transistor M4 drain electrodes
One end, NMOS transistor M4 drain electrode is connected by second load with power supply；
The second level mixing unit includes NMOS transistor M5, NMOS transistor M6, NMOS transistor M7, NMOS transistor
M8, tail current I2, tail current I3, third load and the 4th load；Wherein, it is passed by the AC signal of ac coupling capacitor C10
It is defeated by the source of the NMOS transistor M7 and M8, it is brilliant to be transferred to the NMOS by the AC signal of ac coupling capacitor C11
Body pipe M5 and M6 sources；The NMOS transistor M5 drain terminals are connected with M7 drain terminals, the NMOS transistor M6 drain terminals and M8 drain terminals
It is connected；Intrinsic forward signal LO_p is inputted from the NMOS transistor M5 and M8 grid ends, and intrinsic negative-going signal LO_n is from described
The grid end of NMOS transistor M6 and M7 input, and described NMOS transistor M5, M6, M7, M8 form Kilbert and be mixed structure, finally
The positive IF_p and negative sense IF_n of low intermediate frequency signal transmit out from the drain terminal of the NMOS transistor M8 and M5 respectively；It is described
NMOS transistor M5 is loaded by third to be connected with power supply, and the NMOS transistor M8 is connected by the 4th load with power supply, institute
The other end for stating capacitance C10 is grounded by the tail current I3, and the other end of the capacitance C11 is connect by the tail current I2
Ground.
2. high-linearity active double balanced mixer according to claim 1, which is characterized in that the radio frequency forward signal
Input matching include that passive capacitive C2 and passive inductance L3, the passive capacitive C2 are attempted by the NMOS transistor M1 grids
Between source level, passive inductance L3 is serially connected in the NMOS transistor M1 and M2 common gates point v1 and the NMOS transistor M1 grid
Between pole；The input matching of the radio frequency negative-going signal includes passive capacitive C3 and passive inductance L4, and the passive capacitive C3 is simultaneously
It is connected between the NMOS transistor M2 grids and source level, passive inductance L4 is serially connected in the NMOS transistor M1 and M2 common gates
Between point V1 and the grid of the NMOS transistor M2.
3. high-linearity active double balanced mixer according to claim 2, which is characterized in that the radio frequency forward signal
Input matching further include that passive capacitive C4 and passive resistance R1, the passive resistance R1 are serially connected in the passive inductance L3 and institute
Between stating NMOS transistor M1 and M2 common gate point V1, the one end the passive capacitive C4 and the passive resistance R1 and described passive
Inductance L3 tie points are connected, other end ground connection；The input matching of the radio frequency negative-going signal further includes passive capacitive C5 and passive
Resistance R2, the passive resistance R2 be serially connected in the passive inductance L4 and NMOS transistor M1 and M2 common gate points V1 it
Between, the one end the passive capacitive C5 is connected with the passive resistance R2 and the passive inductance L4 tie points, other end ground connection.
4. high-linearity active double balanced mixer according to claim 1, which is characterized in that further include passive inductance L1
And L2, the passive inductance L1 are serially connected between the NMOS transistor M1 source electrodes and the tail current I1, the passive inductance
L2 is serially connected between the NMOS transistor M2 source electrodes and the tail current I1.
5. high-linearity active double balanced mixer according to claim 1, which is characterized in that further include the first passive electrical
Resistance and the second passive resistance, first passive resistance be serially connected in the NMOS transistor M1 source electrodes and the tail current I1 it
Between, second passive resistance is serially connected between the NMOS transistor M2 source electrodes and the tail current I1.
6. high-linearity active double balanced mixer according to claim 1, which is characterized in that first load is nothing
Source inductance L7, second load are passive inductance L8, and the third load is passive inductance L9, and the 4th load is passive
Inductance L10.
7. high-linearity active double balanced mixer according to claim 6, which is characterized in that first load is also wrapped
It includes and further includes and the passive inductance L8 and the nothing that connects with the passive inductance L7 and the passive capacitive C8 that connects, second load
Source capacitance C9, third load further include also being wrapped with the passive inductance L9 and the passive capacitive C12 that connects, the 4th load
It includes and the passive inductance L10 and the passive capacitive C13 that connects.
8. high-linearity active double balanced mixer according to claim 1, which is characterized in that first load, the
Two loads, third load and the 4th load are passive resistance.
9. high-linearity active double balanced mixer according to claim 1, which is characterized in that further include passive resistance R3
It is serially connected in the grid of the NMOS transistor M3 and the NMOS transistor M3 and M4 with passive resistance R4, the passive resistance R3
Between common gate point V2, the passive resistance R4 be serially connected in the grid of the NMOS transistor M4 and the NMOS transistor M3 and
Between M4 common gate points V2.
10. high-linearity active double balanced mixer according to claim 1, which is characterized in that the tail current I1,
I2, I3 are realized by NMOS transistor, and are folded and realized by current mirror.
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| CN110535441A (en) * | 2019-09-06 | 2019-12-03 | 电子科技大学 | A kind of high-isolation broadband millimeter-wave frequency mixer applied to 5G communication |
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| CN106341087B (en) * | 2016-08-30 | 2019-04-12 | 成都通量科技有限公司 | A kind of frequency mixer |
| CN107231129B (en) * | 2017-05-12 | 2021-01-08 | 成都通量科技有限公司 | Harmonic control CMOS mixer based on transformer structure |
| CN108964614A (en) * | 2018-06-29 | 2018-12-07 | 南通朝旭环保科技有限公司 | Mixer |
| CN109361361B (en) * | 2018-12-07 | 2023-12-22 | 中国电子科技集团公司第五十四研究所 | Ultra-wideband high-linearity up-conversion circuit |
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| US8626106B2 (en) * | 2011-12-06 | 2014-01-07 | Tensorcom, Inc. | Method and apparatus of an input resistance of a passive mixer to broaden the input matching bandwidth of a common source/gate LNA |
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| US6510314B1 (en) * | 2000-09-08 | 2003-01-21 | Visteon Global Technologies, Inc. | Mixer circuit with output stage for implementation on integrated circuit |
| CN101183878A (en) * | 2007-12-20 | 2008-05-21 | 复旦大学 | Low-power consumption wireless receiver radio frequency front end circuit |
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