CN102567767B - Demodulator circuit of electronic tag of RFID (radio frequency identification) system - Google Patents
Demodulator circuit of electronic tag of RFID (radio frequency identification) system Download PDFInfo
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Abstract
The invention discloses a demodulator circuit of an electronic tag of an RFID system. Different from the conventional design, the demodulator circuit acquires a demodulation signal directly from a power supply PWR_DEMO outputted by a rectifier, and achieves demodulation, amplification, shaping and outputting of a weak signal by using an asymmetric circuit design. Specifically, the demodulator circuit conducts demodulation by using envelope detection method, and adopts a secondary comparison circuit. The demodulator circuit of the electronic tag of the RFID system provided by the invention can achieve demodulation of 10% ASK (amplitude shift keying) modulated signals, which are defined as type B according to the standard of ISO/IEC (International Organization for Standardization/International Electrotechnical Commission) 14443-3.
Description
Technical field
The present invention relates to a kind of rf analog front-end circuit of electronic tag of rfid system, particularly relate to the demodulator circuit in described rf analog front-end circuit.
Background technology
RFID (radio frequency identification, radio-frequency (RF) identification) is a kind of contactless automatic identification technology.A rfid system at least comprises transponder (transponder) and interrogator (interrogator) two parts.Transponder claims again electronic tag (tag).Interrogator claims again read write line (reader), is the equipment that electronic tag is read and/or write.
Described electronic tag comprises antenna, rf analog front-end circuit, digital baseband circuit, storage unit (such as EEPROM etc.) conventionally.Conventional rf analog front-end main circuit will comprise:
Rectifier (Rectifier): convert the alternating voltage being coupled on antenna to DC voltage.For rf analog front-end circuit and whole electronic label chip.
Voltage stabilizer (Regulator): the voltage stabilization of rectifier output is lived, as the power supply of the each module of electronic tag.
Detuner (Demodulator): demodulation is out from modulation signal by data message.
Clock obtains and produces circuit: conventionally HF frequency range (for example 13.56MHz) can directly be obtained clock from carrier wave, directly or after frequency division as the clock of digital baseband circuit; Or utilize local oscillator to produce the clock of needed clock signal as digital baseband circuit.
Modulator (Modulator): produce control signal by digital baseband circuit and change the impedance of electronic tag, thereby the signal amplitude of read write line induction is changed, the uploading of settling signal.
Other circuit: comprise ESD (electrostatic defending) circuit etc.
ISO/IEC 14443 agreements are to be operated in the near field standard agreement of (communication distance is less than 10cm), relate to PCD (local coupling equipment, be equivalent to read write line) with PICC (neighbouring card is equivalent to electronic tag) between two-way communication.The signal that this protocol definition electronic tag receives is ASK (Amplitude Shift Keying, amplitude shift keying, claims again amplitude-shift keying) modulation signal.Electronic tag can not directly be processed this signal, must be restored through detuner, could send into digital signal form the remainder (for example digital baseband circuit) of electronic label chip.
According to the difference of signal sending and receiving mode, ISO/IEC 14443-3 has defined TYPE A, two kinds of card types of TYPE B, and their difference is mainly the depth of modulation of carrier wave and the coded system of binary number.When TYPE A type is stuck in PCD to PICC transmission signal, be to transmit signal by the radio-frequency carrier of 13.56MHz.It adopts scheme is synchronous, improved Miller coded system, transmits by 100%ASK.In the time that PICC transmits signal to PCD, transmit signal by modulated carrier, use the subcarrier of 847KHz to transmit Manchester coding.TYPE Type B is stuck in PCD and transmits when signal to PICC, is also the radio-frequency carrier signal by 13.56MHz, but what adopt is asynchronous, nrz encoding mode, by the scheme transmitting with 10%ASK.In the time that PICC transmits signal to PCD, be that the BPSK coding adopting is modulated.
At present mainly contain two kinds of modes for the demodulation of ASK modulation signal: coherent demodulation method and envelope detection method.Coherent demodulation method need to have one to keep the coherent carrier with frequency homophase with ASK modulation signal, necessary phaselocked loop or the narrow band filter of adopting in principle of extraction, and circuit is comparatively complicated.Envelope detection method adopts secondary comparator circuit, and for the 100%ASK modulation signal of TYPE category-A type, demodulator circuit is simple in structure.Only modulation signal directly need be sent in demodulator circuit by antenna end, through the effect of resistance capacitance detecting circuit, the time constant that control discharges and recharges, just can filter out the high frequency carrier of 13.56MHz, interact with the control signal of control circuit again, can obtain the digital baseband signal after required demodulation, send into digital circuit and process.But for the 10%ASK modulation signal of Type category-B type, because its height amplitude difference is relatively very little, it designs with regard to quite complicated and difficulty, and general circuit design more cleverly could realize the demodulation of signal.
Summary of the invention
Technical matters to be solved by this invention is to provide the demodulator circuit in a kind of analog front circuit of electronic tag of rfid system, can meet the demodulation requirement of the TYPE category-B type ASK modulation signal of ISO/IEC 14443-3 standard definition.
For solving the problems of the technologies described above, the demodulator circuit of the electronic tag of rfid system of the present invention comprises 13 MOS transistor, 2 resistance, 1 and 2 phase inverters of 1,1 operational amplifier A of 1 capacitor C;
The operating voltage VCC of the voltage stabilizing of the rectifier output of the electronic tag of rfid system, the supply voltage PWR_DEMO with modulation signal that removes carrier wave, reference voltage Vref are as the input of described demodulator circuit;
The base stage of the first MOS transistor M1 is connected with collector, and connects the operating voltage VCC of voltage stabilizing by the first resistance R 1; The grounded emitter of the first MOS transistor M1;
The base stage of the second MOS transistor M2 is connected with collector, and emitter connects the supply voltage PWR_DEMO with modulation signal that removes carrier wave;
The base stage of the 3rd MOS transistor M3 connects the base stage of the first MOS transistor M1, and the collector of the 3rd MOS transistor M3 connects the base stage of the second MOS transistor M2, the grounded emitter of the 3rd MOS transistor M3;
The base earth of the 4th MOS transistor M4, emitter connects the base stage of the second MOS transistor M2;
The base stage of the 5th MOS transistor M5 connects the collector of the 4th MOS transistor M4, and the collector of the 5th MOS transistor M5 connects the supply voltage PWR_DEMO with modulation signal that removes carrier wave;
The base stage of the 6th MOS transistor M6 connects the base stage of the first MOS transistor M1, and the collector of the 6th MOS transistor M6 connects the emitter of the 5th MOS transistor M5, the grounded emitter of the 6th MOS transistor M6;
The collector of the 7th MOS transistor M7 connects the base stage of the second MOS transistor M2 by the second resistance R 2, the emitter of the 7th MOS transistor M7 connects the emitter of the 5th MOS transistor M5;
The collector of the 8th MOS transistor M8 connects the collector of the 7th MOS transistor M7, and the emitter of the 8th MOS transistor M8 connects the supply voltage PWR_DEMO with modulation signal that removes carrier wave;
The base stage of the 9th MOS transistor M9 connects the base stage of the first MOS transistor M1, the grounded emitter of the 9th MOS transistor M9;
The base stage of the tenth MOS transistor M10 connects the collector of the 7th MOS transistor M7, and the collector of the tenth MOS transistor M10 connects the base stage of the 8th MOS transistor M8, and the emitter of the tenth MOS transistor M10 connects the collector of the 9th MOS transistor M9;
The base stage of the 11 MOS transistor M11 is by the first capacitor C 1 ground connection, and emitter connects the collector of the 9th MOS transistor M9;
The base stage of the 12 MOS transistor M12 is connected with collector, and receives the base stage of the 8th MOS transistor M8, and the emitter of the 12 MOS transistor M12 connects the supply voltage PWR_DEMO with modulation signal that removes carrier wave;
The base stage of the 13 MOS transistor M13 connects the base stage of the 12 MOS transistor M12, the collector of the 13 MOS transistor M13 connects the collector of the 11 MOS transistor M11, and the emitter of the 13 MOS transistor M13 connects the supply voltage PWR_DEMO with modulation signal that removes carrier wave;
The collector of positive input termination the 11 MOS transistor M11 of the first operational amplifier A 1, negative input termination reference voltage Vref;
The output terminal of input termination the first operational amplifier A 1 of the first phase inverter I1, the base stage of output termination the 7th MOS transistor M7 of the first phase inverter I1;
The output terminal of input termination the first phase inverter I1 of the second phase inverter I2, the output terminal output restituted signal Data of the second phase inverter I2.
The demodulator circuit of the electronic tag of rfid system of the present invention can be realized the demodulation of 10% ASK modulation signal of the TYPE category-B type of ISO/IEC 14443-3 standard definition.
Brief description of the drawings
Fig. 1 is rectifier in the analog front circuit of electronic tag of rfid system of the present invention and the schematic diagram of demodulator circuit;
Fig. 2 is the schematic diagram of the analog front circuit of the electronic tag of rfid system of the present invention;
Fig. 3 is the schematic diagram of ASK signal VRF and med signal VMID.
Description of reference numerals in figure:
M1～M13 is respectively the first MOS transistor to the 13 MOS transistor; R1, R2 are respectively the first resistance, the second resistance; C1～C3 is respectively the first electric capacity to the three electric capacity; A1 is operational amplifier; I1, I2 are respectively the first phase inverter, the second phase inverter.
Embodiment
Refer to Fig. 1, this is a specific embodiment of the demodulator circuit of the electronic tag of rfid system of the present invention, this embodiment part more than dotted line is rectifier circuit, below dotted line, part is demodulator circuit, and rectifier and detuner are all the ingredients in the analog front circuit of electronic tag.
Demodulator circuit wherein comprises 13 MOS transistor M1～M13,2 resistance R 1 and R2,1,1 operational amplifier A of 1 capacitor C 1 and 2 phase inverter I1 and I2.Its particular circuit configurations is as follows:
The base stage of the first MOS transistor M1 is connected with collector, and connects the operating voltage VCC of voltage stabilizing by the first resistance R 1; The grounded emitter of the first MOS transistor M1.
The base stage of the second MOS transistor M2 is connected with collector, and emitter connects the supply voltage PWR_DEMO with modulation signal that removes carrier wave.
The base stage of the 3rd MOS transistor M3 connects the base stage of the first MOS transistor M1, and the collector of the 3rd MOS transistor M3 connects the base stage of the second MOS transistor M2, the grounded emitter of the 3rd MOS transistor M3.
The base earth of the 4th MOS transistor M4, emitter connects the base stage of the second MOS transistor M2.
The base stage of the 5th MOS transistor M5 connects the collector of the 4th MOS transistor M4, and the collector of the 5th MOS transistor M5 connects the supply voltage PWR_DEMO with modulation signal that removes carrier wave.
The base stage of the 6th MOS transistor M6 connects the base stage of the first MOS transistor M1, and the collector of the 6th MOS transistor M6 connects the emitter of the 5th MOS transistor M5, the grounded emitter of the 6th MOS transistor M6.
The collector of the 7th MOS transistor M7 connects the base stage of the second MOS transistor M2 by the second resistance R 2, the emitter of the 7th MOS transistor M7 connects the emitter of the 5th MOS transistor M5.
The collector of the 8th MOS transistor M8 connects the collector of the 7th MOS transistor M7, and the emitter of the 8th MOS transistor M8 connects the supply voltage PWR_DEMO with modulation signal that removes carrier wave.
The base stage of the 9th MOS transistor M9 connects the base stage of the first MOS transistor M1, the grounded emitter of the 9th MOS transistor M9.
The base stage of the tenth MOS transistor M10 connects the collector of the 7th MOS transistor M7, and the collector of the tenth MOS transistor M10 connects the base stage of the 8th MOS transistor M8, and the emitter of the tenth MOS transistor M10 connects the collector of the 9th MOS transistor M9.
The base stage of the 11 MOS transistor M11 is by the first capacitor C 1 ground connection, and emitter connects the collector of the 9th MOS transistor M9.
The base stage of the 12 MOS transistor M12 is connected with collector, and receives the base stage of the 8th MOS transistor M8, and the emitter of the 12 MOS transistor M12 connects the supply voltage PWR_DEMO with modulation signal that removes carrier wave.
The base stage of the 13 MOS transistor M13 connects the base stage of the 12 MOS transistor M12, the collector of the 13 MOS transistor M13 connects the collector of the 11 MOS transistor M11, and the emitter of the 13 MOS transistor M13 connects the supply voltage PWR_DEMO with modulation signal that removes carrier wave.
The collector of positive input termination the 11 MOS transistor M11 of the first operational amplifier A 1, negative input termination reference voltage Vref.
The output terminal of input termination the first operational amplifier A 1 of the first phase inverter I1, the base stage of output termination the 7th MOS transistor M7 of the first phase inverter I1.
The output terminal of input termination the first phase inverter I1 of the second phase inverter I2, the output terminal output restituted signal Data of the second phase inverter I2.
Rectifier circuit in Fig. 1 comprises 8 MOS transistor M14～M21,2 capacitor C 2 and C3,3 resistance R 3～R5.Its particular circuit configurations is as follows:
The second capacitor C 2 is connected between antenna port 1 and antenna port 2.
The base stage of the 14 MOS transistor M14 connects antenna port 2, and collector connects antenna port 1, grounded emitter.
The base stage of the 15 MOS transistor M15 connects antenna port 1, and collector connects antenna port 2, grounded emitter.
The base stage of the 16 MOS transistor M16 and emitter all connect antenna port 1, and collector connects the output terminal of the operating voltage VCC of voltage stabilizing.
The base stage of the 17 MOS transistor M17 and emitter all connect antenna port 2, and collector connects the output terminal of the operating voltage VCC of voltage stabilizing.
The base stage of the 18 MOS transistor M18 and emitter all connect antenna port 1 by the 4th resistance R 4, and collector connects the output terminal of the supply voltage PWR_DEMO with modulation signal that removes carrier wave.
The base stage of the 19 MOS transistor M19 and emitter all connect antenna port 2 by the 3rd resistance R 3, and collector connects the output terminal of the supply voltage PWR_DEMO with modulation signal that removes carrier wave.
The base stage of the 20 MOS transistor M20 connects the output terminal of the operating voltage VCC of voltage stabilizing, the equal ground connection of collector and emitter.
One end of the 3rd capacitor C 3 connects the output terminal of the operating voltage VCC of voltage stabilizing, other end ground connection.
The base stage of the 21 MOS transistor M21 and collector all connect the output terminal of clock signal PWR_CLK, grounded emitter.
One termination antenna port 1 of the 5th resistance R 5, the output terminal of another termination clock signal PWR_CLK.
As shown in Figure 1, the operating voltage VCC of the voltage stabilizing of rectifier output, the supply voltage PWR_DEMO with modulation signal that removes carrier wave, reference voltage Vref are as three inputs of demodulator circuit.
In Fig. 1, the first MOS transistor M1, the 3rd MOS transistor M3, the 5th MOS transistor M5, the 6th MOS transistor M6, the 7th MOS transistor M7, the 9th MOS transistor M9, the tenth MOS transistor M10, the 11 MOS transistor M11, the 14 MOS transistor M14, the 15 MOS transistor M15, the 16 MOS transistor M16, the 17 MOS transistor M17, the 18 MOS transistor M18, the 19 MOS transistor M19, the 20 MOS transistor M20, the 21 MOS transistor M21 are NMOS.The second MOS transistor M2, the 4th MOS transistor M4, the 8th MOS transistor M8, the 12 MOS transistor M12, the 13 MOS transistor M13 are PMOS.
Demodulator circuit of the present invention is different from conventional design, is directly to reach restituted signal from the power supply PWR_DEMO of rectifier output, adopts a kind of asymmetrical circuit design by faint signal demodulation amplification and shaping output.Particularly, demodulator circuit of the present invention adopts envelope detection method to carry out demodulation, and adopts secondary comparator circuit.The supply voltage PWR_DEMO with modulation signal that processes removal carrier wave through rectifier rectification sends into demodulator circuit, first becomes V1 through the dividing potential drop of the second MOS transistor M2 and the 3rd MOS transistor M3.V1 sends into the anode VIP of the first order differential pair being made up of the tenth MOS transistor M10 and the 11 MOS transistor M11 on the one hand after the sluggish processing of the second resistance R 2, V1 sends into the negative terminal VIN of this differential pair on the other hand after integrating capacitor C1, after this differential pair relatively amplifies two signals of anode and negative terminal, comparer A1 through the operating voltage VCC of voltage stabilizing reverts to stable output signal, then is reduced to digital signal Data through the phase inverter I1, the I2 shaping that are similarly VCC stabilized power source.
The course of work of demodulator circuit is: in the time that the signal of input is high level, because integrator (is made up of the 4th transistor M4 and the first capacitor C 1, in the time being input as high level, charges to the first capacitor C 1; In the time being input as low level, discharge from the first capacitor C 1) effect, the voltage of VIP end is higher than the voltage of VIN end, V2 is high level, therefore, output Data is 1.Now, V3 is low, the 8th MOS transistor M8 is in conducting state, the electric current of the 8th MOS transistor M8 flows through the second resistance R 2, make the voltage of VIP end higher than VIN end certain voltage Δ V, and the ceiling voltage of VIN end can only reach V1, this has ensured the voltage that the voltage of VIP end is held higher than VIN all the time, in the period that is high level at signal, output Data keeps 1.
In the time that the signal of input is low level, the 19 MOS transistor M19 ends rapidly, and the voltage of VIP end is lower than the voltage of VIN end, and V2 is low level, and Data is 0.Now V3 is 1, the 7th MOS transistor M7 conducting, electric current flows into the 6th MOS transistor M6 and the 7th MOS transistor M7 by the second resistance R 2, V1 is higher than VIP end certain voltage Δ V like this, and the voltage of VIN end is reduced at most V1, this voltage that has ensured VIP end is all the time lower than the voltage of VIN end, and in signal is low level period, output Data remains 0.
The transmission cycle that the time constant discharging and recharging of described integrator is fetched data, is worth by setting the first suitable capacitor C 1, regulates the breadth length ratio of the 4th MOS transistor M4, the groove time (pause width) that just can obtain exporting data.Pressure drop Δ V in the second resistance R 2 gets tens millivolts of magnitudes.The initial current of whole circuit is provided by biasing circuit.Described biasing circuit is made up of the first resistance R 1 and the first MOS transistor M1.Because this demodulator circuit is directly connected with rectifier circuit, in order not make this circuit reduce the supply voltage PWR_DEMO of output, by the Current Control of this circuit in microampere order magnitude range.
Refer to Fig. 2, this is the structural representation of the analog front circuit of the electronic tag of rfid system of the present invention, comprising rectifier and detuner, and between rectifier and detuner, there are the operating voltage VCC of voltage stabilizing, two signals connections of the supply voltage PWR_DEMO with modulation signal of removing carrier wave.
Refer to Fig. 3, the ASK signal that needs demodulation is VRF, VRF signal is got to intermediate value processing by integrating circuit and obtain signal VMID.The positive and negative two ends of signal VRF and signal VMID being sent into respectively to operational amplifier, amplifying circuit compares and enlarges processing to VRF and VMID, if VRF is lower than VMID, obtain low-voltage output, on the contrary, if VRF, higher than VMID, exports and obtains high power supply voltage.Because signal VMID is along with signal VRF changes, it is a kind of dynamically real-time comparison, as long as control the capacity resistance cime constant of integrator well, make integrator catch up with the variation of signal VRF, just can by high and low the simulation of ASK signal in real time be reduced to high level and ground level, so just produce baseband signal, sent into the processing of decoding of follow-up DLC (digital logic circuit).
The demodulator circuit of the electronic tag of rfid system of the present invention, can realize the demodulation of 10% ASK modulation signal of the TYPE category-B type that defines in ISO15693 and ISO14443B agreement.
Claims (3)
1. a demodulator circuit for the electronic tag of rfid system, is characterized in that, comprises 13 MOS transistor, 2 resistance, 1 electric capacity (C1), 1 operational amplifier (A1) and 2 phase inverters;
The operating voltage (VCC) of the voltage stabilizing of the rectifier output of the electronic tag of rfid system, the supply voltage with modulation signal (PWR_DEMO) of removing carrier wave, reference voltage (Vref) are as the input of described demodulator circuit;
The base stage of the first MOS transistor (M1) is connected with collector, and connects the operating voltage (VCC) of voltage stabilizing by the first resistance (R1); The grounded emitter of the first MOS transistor (M1);
The base stage of the second MOS transistor (M2) is connected with collector, and emitter connects the supply voltage with modulation signal (PWR_DEMO) of removing carrier wave;
The base stage of the 3rd MOS transistor (M3) connects the base stage of the first MOS transistor (M1), the collector of the 3rd MOS transistor (M3) connects the base stage of the second MOS transistor (M2), the grounded emitter of the 3rd MOS transistor (M3);
The base earth of the 4th MOS transistor (M4), emitter connects the base stage of the second MOS transistor (M2);
The base stage of the 5th MOS transistor (M5) connects the collector of the 4th MOS transistor (M4), and the collector of the 5th MOS transistor (M5) connects the supply voltage with modulation signal (PWR_DEMO) of removing carrier wave;
The base stage of the 6th MOS transistor (M6) connects the base stage of the first MOS transistor (M1), the collector of the 6th MOS transistor (M6) connects the emitter of the 5th MOS transistor (M5), the grounded emitter of the 6th MOS transistor (M6);
The collector of the 7th MOS transistor (M7) connects the base stage of the second MOS transistor (M2) by the second resistance (R2), the emitter of the 7th MOS transistor (M7) connects the emitter of the 5th MOS transistor (M5);
The collector of the 8th MOS transistor (M8) connects the collector of the 7th MOS transistor (M7), and the emitter of the 8th MOS transistor (M8) connects the supply voltage with modulation signal (PWR_DEMO) of removing carrier wave;
The base stage of the 9th MOS transistor (M9) connects the base stage of the first MOS transistor (M1), the grounded emitter of the 9th MOS transistor (M9);
The base stage of the tenth MOS transistor (M10) connects the collector of the 7th MOS transistor (M7), the collector of the tenth MOS transistor (M10) connects the base stage of the 8th MOS transistor (M8), and the emitter of the tenth MOS transistor (M10) connects the collector of the 9th MOS transistor (M9);
The base stage of the 11 MOS transistor (M11) is by the first electric capacity (C1) ground connection, and emitter connects the collector of the 9th MOS transistor (M9);
The base stage of the 12 MOS transistor (M12) is connected with collector, and receive the base stage of the 8th MOS transistor (M8), the emitter of the 12 MOS transistor (M12) connects the supply voltage with modulation signal (PWR_DEMO) of removing carrier wave;
The base stage of the 13 MOS transistor (M13) connects the base stage of the 12 MOS transistor (M12), the collector of the 13 MOS transistor (M13) connects the collector of the 11 MOS transistor (M11), and the emitter of the 13 MOS transistor (M13) connects the supply voltage with modulation signal (PWR_DEMO) of removing carrier wave;
The collector of positive input termination the 11 MOS transistor (M11) of the first operational amplifier (A1), negative input termination reference voltage (Vref);
The output terminal of input termination first operational amplifier (A1) of the first phase inverter (I1), the base stage of output termination the 7th MOS transistor (M7) of the first phase inverter (I1);
The output terminal of input termination first phase inverter (I1) of the second phase inverter (I2), the output terminal output restituted signal (Data) of the second phase inverter (I2).
2. the demodulator circuit of the electronic tag of rfid system according to claim 1, it is characterized in that, described the first MOS transistor (M1), the 3rd MOS transistor (M3), the 5th MOS transistor (M5), the 6th MOS transistor (M6), the 7th MOS transistor (M7), the 9th MOS transistor (M9), the tenth MOS transistor (M10), the 11 MOS transistor (M11) are NMOS;
The second MOS transistor (M2), the 4th MOS transistor (M4), the 8th MOS transistor (M8), the 12 MOS transistor (M12), the 13 MOS transistor (M13) are PMOS.
3. the demodulator circuit of the electronic tag of rfid system according to claim 1, it is characterized in that, described the 4th MOS transistor (M4) and the first electric capacity (C1) have formed an integrator, in the time being input as high level, described integrator is given the first electric capacity (C1) charging; In the time being input as low level, described integrator discharges from the first electric capacity (C1).
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| CN201010589060.3A CN102567767B (en) | 2010-12-15 | 2010-12-15 | Demodulator circuit of electronic tag of RFID (radio frequency identification) system |
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| KR101330483B1 (en) * | 2012-07-26 | 2013-11-15 | 엘에스산전 주식회사 | Rfid tag device |
| CN103683991A (en) * | 2013-11-28 | 2014-03-26 | 成都位时通科技有限公司 | Power supply circuit stable in power supply |
| CN103715920A (en) * | 2013-12-11 | 2014-04-09 | 杭州电子科技大学 | Rectifier circuit and radio frequency identification tag circuit chip comprising the same |
| WO2015170479A1 (en) * | 2014-05-09 | 2015-11-12 | パナソニックＩｐマネジメント株式会社 | Rectifier circuit, and rectifier and wireless power supply device equipped with same |
| CN104866888B (en) * | 2015-04-20 | 2018-03-06 | 卓捷创芯科技（深圳）有限公司 | Suitable for the rectification circuit and passive RF label of the amplitude-modulated signal of pulsewidth modulation |
| CN104935424B (en) * | 2015-05-29 | 2019-01-04 | 清华大学 | For removing the device of carrier signal |
| EP3107208B1 (en) * | 2015-06-15 | 2018-08-15 | STMicroelectronics International N.V. | Demodulator circuit and method for demodulation |
| CN106599971B (en) * | 2016-12-12 | 2019-06-07 | 北京智芯微电子科技有限公司 | A kind of electronic tag power rectifier circuit |
| CN111049262A (en) * | 2019-11-26 | 2020-04-21 | 国网江苏省电力有限公司盐城供电分公司 | Join in marriage net construction safety quality management and control sensor for platform based on electric power thing allies oneself with power |
| CN112683953B (en) * | 2021-01-14 | 2022-11-25 | 东莞理工学院 | Internet of things-based constructed wetland micro-polluted water quality detection sensor and detection device |
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| CN101789921A (en) * | 2009-01-23 | 2010-07-28 | 中芯国际集成电路制造(上海)有限公司 | Amplitude shift keying demodulator and method |
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| CN101789921A (en) * | 2009-01-23 | 2010-07-28 | 中芯国际集成电路制造(上海)有限公司 | Amplitude shift keying demodulator and method |
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