CN102710260B - Divide-by-four injection locked frequency divider circuit with low power consumption and wide lock range - Google Patents
Divide-by-four injection locked frequency divider circuit with low power consumption and wide lock range Download PDFInfo
- Publication number
- CN102710260B CN102710260B CN201210206110.4A CN201210206110A CN102710260B CN 102710260 B CN102710260 B CN 102710260B CN 201210206110 A CN201210206110 A CN 201210206110A CN 102710260 B CN102710260 B CN 102710260B
- Authority
- CN
- China
- Prior art keywords
- pipe
- cross
- circuit
- injection
- couplings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
The invention belongs to the technical field of integrated circuits and particularly discloses a divide-by-four injection locked frequency divider circuit with low power consumption and wide lock range. The divide-by-four injection locked frequency divider circuit is composed of two stages of divide-by-two injection locked frequency dividers with identical structures, circuit stages are coupled by adopting a capacitor, and each circuit stage is composed of an inductor, a crossed coupling pipe, two injection pipes, a coupling capacitor and a biasing circuit. For the structure of the circuit, two injection manners including a direct injection manner and a tail current source injection manner are adopted at the same time, so that the circuit has the advantages of the two injection manners simultaneously, injection signals are inversion signals, an injection end is a grid electrode of an MOS (Metal Oxide Semiconductor) tube, and the divide-by-two injection locked frequency dividers can be directly cascaded. The circuit disclosed by the invention can be powered by dual-power-supply voltage, is suitable for a low power supply voltage environment, is low in direct-current power consumption and can be used to realize a wider lock range. The circuit is of a differential structure and can be realized by using CMOS (Complementary Metal Oxide Semiconductor), BiMOS (Bi-state Metal Oxide Semiconductor) and other processes.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of being applied to except four injection locking frequency dividers (ILFD) circuit in the frequency synthesizer circuit of broadband low-power consumption, can be used for frequency microwave frequency synthesizer etc. needs in the analog integrated circuit of low-power consumption, wide lock-in range.
Background technology
Along with communication and the development of semiconductor technology, various mobile communication and Wireless Data Transmission develop rapidly, and simultaneously, people require more and more stronger to the two-forty of wireless communication technology and large bandwidth, this impels people constantly to go to develop the wireless communication technology of more high frequency band resource and research hyperfrequency.And simultaneously, wireless lan communication lsi is but towards the future development of highly integrated SOC (system on a chip), low-power consumption has become the inevitable requirement of Wireless IC design, and the local oscillation signal of now low-power consumption produces circuit and also becomes extremely important.Local oscillation signal for centimeter wave and millimeter wave produces the high band frequency divider in circuit, if continue to adopt traditional CML (CML) circuit, its power consumption sharply can increase along with the increase of operating frequency, injection locking frequency divider (ILFD) based on LC not only can be operated in very high frequency range, and it also has obviously advantage in low-power consumption.Injection locking frequency divider is two frequency-doubled signals that injection one is stronger in an oscillating circuit, thus draws oscillator and make it 1/2 frequency locking onto Injection Signal.But the shortcoming of injection locking frequency divider is that its operating frequency range is very limited, the deviation of the aspects such as technique, temperature, voltage can have a strong impact on the stability of injection locking frequency divider.Therefore, wide lock-in range injection locking frequency divider becomes again a very large design challenge.
For traditional injection locking frequency divider, the Q value of its lock-in range and resonant tank has much relations, and the circuit lock-in range of high q-factor is less, the circuit lock-in range of low reactance-resistance ratio is larger, but power dissipation ratio is comparatively large, and its output voltage swing is often less, and this is very unfavorable to late-class circuit.On the other hand, for the circuit that operating frequency is very high, through one-level except after two-divider, its frequency is still very high, if at this moment adopt CML circuit frequency division, still there is comparatively serious power problems.Therefore, the injection locking frequency divider with high frequency division ratio becomes new study hotspot.The injection locking frequency divider framework of current high frequency division ratio mainly adopts single resonance loop frequency divider, wherein except three, except four-divider more, but the harmonic component that single resonance loop produces high frequency division ratio is more difficult, so lock-in range is very limited.But its prime output voltage swing of cascade connection type high frequency division ratio injection locking frequency divider is little, second harmonic component is large, this makes rear class more be difficult to realize wide lock-in range, and the lock-in range therefore except four injection locking frequency dividers is little more many than the lock-in range except two injection locking frequency dividers.If insert the whole phase amplifying circuit of filtering at inter-stage, power consumption and the area of whole frequency divider link will certainly be increased.
Summary of the invention
The object of the invention is to design that a kind of power electric is forced down, lock-in range is wide, DC power is little in frequency comprehensive circuit except four injection locking frequency dividers (ILFD), centimeter wave or millimeter wave frequency band can be operated in.
The present invention's design in frequency comprehensive circuit except four injection locking frequency dividers, by identical the forming except two injection locking frequency dividers of two-layer configuration, as shown in Figure 1.All adopt capacitive coupling to realize DC-isolation between the input signal of circuit and first order injection locking frequency divider, between first order injection locking frequency divider and second level injection locking frequency divider, between second level injection locking frequency divider and output.DC offset voltage V
b1, V
b2, V
b3, V
b4inputted by outside, and by exchanging isolation resistance R1, R2, R3, R4, be carried on the grid of direct ascending pipe M1, tail current source capsule pipe M2, directly ascending pipe M5, tail current source capsule pipe M6 respectively, as shown in Figure 2.
Wherein, each two injection locking frequency dividers that remove are made up of load inductance and load capacitance, cross-couplings pipe, directly ascending pipe and tail current source capsule.Wherein directly ascending pipe M1 and direct ascending pipe M5 two transistors adopt directly injection, and input signal is coupled on their grid, and Injection Current is directly injected in resonant tank by their source-drain electrode and goes, by bias voltage V
b1, V
b3regulate their bias voltage; Tail current source capsule M2 and tail current source capsule M6 two transistors adopt tail current source to inject, input signal is coupled on their grid, Injection Signal is injected in resonant tank and goes by cross-couplings pipe M3, cross-couplings pipe M4 and cross-couplings pipe M7, cross-couplings pipe M8, by bias voltage V again after they are anti-phase
b2, V
b4regulate their bias voltage.Input signal added on direct ascending pipe M1 and tail current source capsule M2 grid is inversion signal, and on direct ascending pipe M5 and tail current source capsule M6 grid, added signal is also inversion signal, as shown in Figure 2.
Cross-couplings pipe M3, cross-couplings pipe M4 and cross-couplings pipe M7, cross-couplings pipe M8 provide negative resistance for resonant circuit.Wherein the common source of cross-couplings pipe M3, cross-couplings pipe M4 terminates in the drain electrode of tail current pipe M2; The drain electrode of cross-couplings pipe M3 is connected with cross-couplings pipe M4 grid and is attempted by the output node V of the first order
x-, the drain electrode of cross-couplings pipe M4 is connected with cross-couplings pipe M3 grid and is attempted by the output node V of the first order
x+; The common source of cross-couplings pipe M7, cross-couplings pipe M8 terminates in the drain electrode of tail current pipe M6; The drain electrode of cross-couplings pipe M7 is connected with cross-couplings pipe M8 grid and is attempted by the output node V of the first order
out-, the drain electrode of cross-couplings pipe M8 is connected with cross-couplings pipe M7 grid and is attempted by the output node V of the first order
out+, as shown in Figure 2.
Inductance L 1, inductance L 2, inductance L 3, inductance L 4 are load inductances of circuit.Their end is connected on power supply, and the other end is connected on the output node of corresponding resonant tank, as shown in Figure 2.
The load capacitance of circuit is made up of circuit parasitic capacitance and successive load, and their total equivalent capacitys are respectively C
lx-, C
lx+, C
lout-, C
lout+, as shown in Figure 2.
The lock-in range of this circuit is about two frequencys multiplication of the self-resonant frequency of the first order " except two injection locking frequency dividers ", and input signal is two-way inversion signal; The self-resonant frequency of the first order " except two injection locking frequency dividers " is about two frequencys multiplication of the self-resonant frequency of the second level " except two injection locking frequency dividers ", the differential signal that the first order produces divides two-way to be input in the second level " except two injection locking frequency dividers " through coupling capacitance to go, the second level " except two injection locking frequency dividers ", and produce difference output then.
The input circuit of circuit of the present invention realizes by every straight coupling capacitance and biasing resistor.Input signal is directly transferred on the grid of ascending pipe by coupling capacitance; Gate bias voltage is controlled through biasing resistor by control voltage.The input impedance of entering viewed from Vin+ is mainly the series impedance of capacitance C1, directly ascending pipe M1 grid capacitance and resonant tank, the input impedance of entering viewed from Vin-is mainly the series impedance of capacitance C2 and tail current source ascending pipe M2 grid capacitance, they are capacitive reactances mainly, compares the load being suitable as prime oscillation circuit.If need test, 50 Ω impedance matchings separately need be added.
Circuit of the present invention adopts inter-stage capacitive coupling, and the output of previous stage is directly coupled to by coupling capacitance on the grid of ascending pipe of rear stage, does not adopt the whole phase amplifying circuit of inter-stage filtering, in order to avoid produce extra power consumption and area.
The output of circuit of the present invention is suitable for connecing capacitive load or inductive load, and can affect the Q value of second level resonant tank as connect resistive load, circuit working state also can be affected.
The direct grid current bias voltage V of each ascending pipe of circuit of the present invention
b1, V
b2, V
b3, V
b4inputted by outside, they are on the DC power of circuit, lock-in range, output voltage swing and export the performances such as higher harmonic components and have very large impact, should be optimized according to real work situation.Especially the directly gate bias voltage of ascending pipe, it on circuit characteristic impact clearly suitably improves it and obviously can increase lock-in range.When the input amplitude of oscillation is limited, and when requiring larger lock-in range, the grid bias of direct ascending pipe should be made higher than supply voltage, and this circuit suitable services is in multi-power source voltage circuit.
The input signal of the direct ascending pipe of circuit of the present invention is directly added on its grid by coupling capacitance; Its source electrode and drain electrode are directly parallel in difference output two ends, and Injection Current is directly injected in resonant tank and goes.
The tail current source ascending pipe of circuit of the present invention, doubles as ascending pipe and tail current source capsule simultaneously.Circuit direct power consumption can be controlled by controlling its gate bias voltage.Its input signal is the inversion signal of direct ascending pipe grid input signal, and is directly added on its gate by coupling capacitance.Input voltage signal, after it is anti-phase, is formed Injection Current, is added on the public source of cross-couplings pipe, and be injected in resonant tank by the mixing effect of cross-couplings pipe and go.
The resonant tank of circuit of the present invention is made up of load inductance, cross-couplings pipe, directly ascending pipe and load circuit.Realize low-power consumption and must adopt the inductance that inductance value is larger, operating frequency be improved and just should reduce parasitic capacitance.For reducing parasitic capacitance and supply voltage, only NMOS cross-couplings pipe or NPN BJT cross-couplings pipe should be adopted.
Principal character of the present invention and operation principle:
The principal character of circuit of the present invention is, have modified the classical circuit structure except two injection locking frequency dividers, do not adopt the whole phase amplifying circuit of the filtering of inter-stage, but by two frequency dividers through capacitive coupling cascade, so just be conducive to reducing power consumption and area, as shown in Figure 1.This circuit adopts anti-phase input and Dual Implantations, alleviates the load produced front stage circuits, has organically combined the advantage of two kinds of circuit simultaneously, achieved wider lock-in range.
Should be all capacitive coupling except the input of two injection locking frequency dividers, the impedance of entering viewed from input is capacitive reactances, be applicable to, directly as the load of previous stage resonant tank, avoiding to add buffer circuit between itself and front stage circuits because having resistive load, as shown in Figure 2.
Should be inversion signal except the input signal of two injection locking frequency dividers, two-way input be connected on the differential input end of prime respectively, would not produce very large load like this, as shown in Figure 2 to single-port.
Directly injection and tail current source should be adopted to inject two kinds of injection modes except two injection locking frequency dividers simultaneously, have the advantage of two kinds of injection modes concurrently.
Direct injection Injection Current is directly injected into resonant tank go, and ascending pipe doubles as mutual conductance pipe and mixer tube, has higher injection efficiency, as shown in Figure 4.Its advantage be directly the pulse current injectingt of source-drain electrode in resonant tank, there is very high injection efficiency, shortcoming forms path when being its conducting between differential output nodes, injects Q value and the output voltage swing that obviously can affect resonant tank like this, injects and circuit can be made too by force no longer to vibrate.As adopted separately direct injection, lock-in range is limited, and incoming frequency depart from its local frequency more time output voltage swing very little, very unfavorable to subordinate's circuit, be not suitable for direct cascade except four injection locking frequency dividers.
It is be injected on the source electrode of cross-couplings pipe by the current signal of two frequencys multiplication that tail current source injects, the Injection Current near resonant tank local frequency is produced by the mixing effect of cross-couplings pipe, and be injected in resonant tank and go, injection efficiency is lower, as shown in Fig. 5 (a).The common source node of cross-couplings pipe has larger parasitic capacitance, and parasitic capacitance can cause Injection Current to lose; And cross-couplings pipe doubles as negative resistance and produces circuit and mixting circuit, and now the injection phase place of Injection Current is restricted, and injection efficiency is lower simultaneously.If replace current source (as Suo Shi Fig. 5 (b)) with an inductance, at this moment foreign current can be injected on cross-couplings pipe common source node, can injection efficiency be improved but can area be increased.
Circuit structure shown in Fig. 5 is not suitable for the direct cascade carrying out circuit, because signal input node is the source electrode of cross-couplings pipe, it is a low-impedance node, if the less capacitive load that maybe can only drive of input current just must increase one-level trsanscondutance amplifier, is equivalent to inter-stage buffer circuit.
But make structure shown in Fig. 5 into shown in Fig. 6 structure, input node just only has capacitive load, directly can be linked in the resonant tank of previous stage like this and go, and not affect its Q value.Now tail current pipe carries out tail current control simultaneously and converts input voltage signal to current signal.
Simultaneously, the electric current that tail current source ascending pipe consumes also is the electric current that cross-couplings pipe flows through simultaneously, this makes it in resonant tank during Injection Current, also it is the time of cross-couplings pipe conducting, Injection Signal reduces the angle of flow (as shown in Figure 7) of cross-couplings pipe, improve their current utilization efficiency, be conducive to improving output voltage swing.From time domain waveform, at this moment the load inductance of this node charges, and Injection Current charges to load inductance, is conducive to induction charging, therefore favourable to output voltage swing, as shown in Figure 7.
This circuit structure have employed simultaneously and directly injects and tail current source injection (as shown in Figure 2), utilize and directly inject, achieve higher injection efficiency, tail current source is utilized to inject, further raising injection efficiency, improve output voltage swing, to improve the lock-in range except four injection locking frequency dividers after cascade simultaneously.
Accompanying drawing explanation
Fig. 1 is the structured flowchart that the present invention removes four injection locking frequency dividers.
Fig. 2 is the circuit theory diagrams that the present invention removes four injection locking frequency dividers.
Fig. 3 is spiral inductance.Wherein, (a) dual-port spiral inductance, (b) is with tapped spiral inductance.
Fig. 4 is for directly to inject injection locking frequency divider.The source-drain electrode of ascending pipe is connected in the differential output nodes of differential oscillator.
Fig. 5 is for being current source injection locking frequency divider.Wherein, (a) adopts tail current source, and (b) replaces tail current source with inductance.
Fig. 6 is that grid input tail current source injects injection locking frequency divider.Input signal is carried on the grid of tail current pipe, produces Injection Current by controlling tail current size.
Fig. 7 is that incoming frequency is 27GHz, and signal magnitude is 0dBm to first order when carrying out Transient except four injection locking frequency dividers except two-divider current-voltage waveform.Curve (a) is tail current source current, the electric current of curve (b) cross-couplings Guan Zhongyi transistor, and curve (c) is load inductance electric current, and curve (d) is corresponding output node voltage, and curve (e) is another output node voltage.
Fig. 8 is the relation emulating lock-in range and the input signal size obtained.Abscissa is incoming frequency, and ordinate is the input signal power that output signal frequency can be made to be locked in 1/2 frequency place of incoming frequency.
Embodiment
Remove four injection locking frequency dividers with a low-power consumption, incoming frequency in the wide lock-in range of 26.25GHz ~ 30.25GHz and be designed to example.
Shown in design circuit Fig. 2, add a fully-differential amplifier as load circuit.Adopt TSMC 0.13 μm of RF CMOS 1P8M technique, emulation tool is Cadence SpectreRF, adopts 800mV supply voltage.Wherein V
b1=V
b3=1.2V, V
b2and V
b4make current mirror bias into reduce process deviation, actual value is at about 600mV.
Wherein metal-oxide-semiconductor is all radio frequency NMOS tube, and resistance is high value polysilicon resistance, and electric capacity is MIM capacitor, and inductance is with tapped on-chip spiral inductor, the 8th layer of metal routing.A L1 and L2 1.67nH inductance realizes, a L3 and L4 4.15nH inductance realizes.
Input signal size is the single-ended peak-to-peak value of 0dBm(is 632mV) differential signal time, locking frequency scope is 26.25GHz to 30.25GHz, and DC power is 1.5mW.Fig. 7 is this circuit Transient waveform, and Fig. 8 is the relation emulating lock-in range and the input signal size obtained.
Concrete simulation result is as following table:
。
Claims (1)
1. the wide lock-in range of low-power consumption except four injection locking frequency divider circuit, it is characterized in that by identical the forming except two injection locking frequency dividers of two-layer configuration; All adopt capacitive coupling to realize DC-isolation between the input signal of circuit and first order injection locking frequency divider, between first order injection locking frequency divider and second level injection locking frequency divider, between second level injection locking frequency divider and output; DC offset voltage V
b1, V
b2, V
b3, V
b4inputted by outside, and by exchanging isolation resistance R1, R2, R3, R4, be carried on the grid of direct ascending pipe M1, tail current source capsule M2, directly ascending pipe M5, tail current source capsule M6 respectively;
Wherein, each two injection locking frequency dividers that remove are made up of load inductance and load capacitance, cross-couplings pipe, directly ascending pipe and tail current source capsule; Wherein directly ascending pipe M1 and direct ascending pipe M5 two transistors adopt directly injection, and input signal is coupled on their grid, and Injection Signal is directly injected in resonant tank by their source-drain electrode, by bias voltage V
b1, V
b3regulate their bias voltage; Tail current source capsule M2 and tail current source capsule M6 two transistors adopt tail current source to inject, input signal is coupled on their grid, Injection Signal is injected in resonant tank and goes by cross-couplings pipe M3, cross-couplings pipe M4 and cross-couplings pipe M7, cross-couplings pipe M8, by bias voltage V again after they are anti-phase
b2, V
b4regulate their bias voltage; Input signal added on direct ascending pipe M1 and tail current source capsule M2 grid is inversion signal, and on direct ascending pipe M5 and tail current source capsule M6 grid, added signal is also inversion signal; Cross-couplings pipe M3 and cross-couplings pipe M4, cross-couplings pipe M7 and cross-couplings pipe M8 provide negative resistance for resonant tank; Wherein the common source of cross-couplings pipe M3, cross-couplings pipe M4 terminates in the drain electrode of tail current pipe M2; The drain electrode of cross-couplings pipe M3 is connected with cross-couplings pipe M4 grid and is attempted by the output node V of the first order
x-, the drain electrode of cross-couplings pipe M4 is connected with cross-couplings pipe M3 grid and is attempted by the output node V of the first order
x+; The common source of cross-couplings pipe M7, cross-couplings pipe M8 terminates in the drain electrode of tail current pipe M6; The drain electrode of cross-couplings pipe M7 is connected with cross-couplings pipe M8 grid and is attempted by the output node V of the second level
out-, the drain electrode of cross-couplings pipe M8 is connected with cross-couplings pipe M7 grid and is attempted by the output node V of the second level
out+; Inductance L 1, inductance L 2, inductance L 3, inductance L 4 are load inductances of circuit; Their end is connected on power supply, and the other end is connected on the output node of corresponding resonant tank; The load capacitance of circuit is made up of circuit parasitic capacitance and successive load;
Described resonant tank refers to: at direct ascending pipe M1, tail current source capsule M2, cross-couplings pipe M3, cross-couplings pipe M4, directly all have parasitic capacitance between ascending pipe M5, tail current source capsule M6, cross-couplings pipe M7, these active devices of cross-couplings pipe M8 arbitrary node separately, these parasitic capacitances and inductance L 1, inductance L 2, inductance L 3, inductance L 4, electric capacity C1, electric capacity C2, electric capacity C3, electric capacity C4, resistance R1, resistance R2, resistance R3, resistance R4 form a passive device network; This passive device network is at node V
x-and V
x+between form the shunt-resonant circuit that resonance frequency is f1, at node V
out-and V
out+between form the shunt-resonant circuit that resonance frequency is f2; F1 is about the twice of f2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210206110.4A CN102710260B (en) | 2012-06-21 | 2012-06-21 | Divide-by-four injection locked frequency divider circuit with low power consumption and wide lock range |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210206110.4A CN102710260B (en) | 2012-06-21 | 2012-06-21 | Divide-by-four injection locked frequency divider circuit with low power consumption and wide lock range |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102710260A CN102710260A (en) | 2012-10-03 |
| CN102710260B true CN102710260B (en) | 2015-03-04 |
Family
ID=46902853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210206110.4A Expired - Fee Related CN102710260B (en) | 2012-06-21 | 2012-06-21 | Divide-by-four injection locked frequency divider circuit with low power consumption and wide lock range |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102710260B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107124181B (en) * | 2017-03-28 | 2021-06-04 | 复旦大学 | Injection locking frequency divider circuit with wide locking range |
| CN108768302A (en) * | 2018-05-18 | 2018-11-06 | 南京邮电大学 | One kind removing three injection locking frequency dividers |
| CN110690897B (en) * | 2019-09-30 | 2023-05-30 | 西安电子科技大学 | Low-power injection locking frequency divider with wide frequency band locking range |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200845591A (en) * | 2007-05-08 | 2008-11-16 | Univ Nat Taiwan Science Tech | Injection-locked frequency divider |
| CN101777871A (en) * | 2009-01-09 | 2010-07-14 | 复旦大学 | Injection locking frequency divider |
| CN102158228A (en) * | 2011-04-19 | 2011-08-17 | 复旦大学 | Very low voltage millimeter wave injection-locked dichotomous frequency divider |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7961058B2 (en) * | 2009-05-29 | 2011-06-14 | The Hong Kong University Of Science And Technology | Frequency divider using an injection-locking-range enhancement technique |
-
2012
- 2012-06-21 CN CN201210206110.4A patent/CN102710260B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200845591A (en) * | 2007-05-08 | 2008-11-16 | Univ Nat Taiwan Science Tech | Injection-locked frequency divider |
| CN101777871A (en) * | 2009-01-09 | 2010-07-14 | 复旦大学 | Injection locking frequency divider |
| CN102158228A (en) * | 2011-04-19 | 2011-08-17 | 复旦大学 | Very low voltage millimeter wave injection-locked dichotomous frequency divider |
Non-Patent Citations (1)
| Title |
|---|
| 应用于高频低功耗系统的1.2V 10GHz注入锁定分频器;尹江伟等;《复旦学报(自然科学版)》;20081231;第47卷(第6期);第685-690页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102710260A (en) | 2012-10-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102104363B (en) | Tera-hertz silica-based quadrupler and frequency multiplier | |
| CN103475310B (en) | Low power consumption injection locked frequency tripler | |
| US20100301955A1 (en) | Frequency divider using an injection-locking-range enhancement technique | |
| CN106487382A (en) | A kind of injection locking frequency divider of multimode frequency dividing | |
| CN107248847A (en) | A kind of difference Kao Bizi voltage controlled oscillators | |
| CN104052405A (en) | System and method for frequency doubler | |
| Kumar | A low power voltage controlled oscillator design | |
| CN201039084Y (en) | Low-amplitude error and low-phase noise RF voltage controlled surge based on capacitance compensation | |
| CN102710260B (en) | Divide-by-four injection locked frequency divider circuit with low power consumption and wide lock range | |
| CN102291132B (en) | Current-mode-logic-based high speed high-oscillation amplitude divide-by-two frequency divider circuit | |
| CN101931396B (en) | Prescaler with clock-controlled transistor | |
| CN111313892B (en) | Wide locking range switchable dual-core injection locking frequency divider | |
| CN204013484U (en) | A kind of novel low-voltage frequency divider | |
| CN206077360U (en) | Signal enhancing source coupled logic frequency divider | |
| Hemmati et al. | A CMOS quadrature VCO with optimized Colpitts topology for low-voltage applications | |
| CN106452435B (en) | Signal enhancing pre-divider | |
| Neeraja et al. | Review of Ultra Low Power Receiver Front-end Designs | |
| CN103208990B (en) | The pre-frequency dividing circuit of a kind of novel high speed | |
| CN104333329B (en) | Injection enhanced low-power wide-locking-scope injection locking tripler | |
| CN105262484A (en) | Method and circuit for realizing injection locking of ring oscillator | |
| Chao et al. | A 2.9 mW 53.4–79.4 GHz frequency-tracking injection-locked frequency divider with 39.2% locking range in 65nm CMOS | |
| TWI411221B (en) | Injection-locked frequency divider/doubler using switched cross-coupled transistors | |
| CN105743496A (en) | Numerically controlled oscillator working under near-threshold power voltage | |
| Majd et al. | Low-power high-Gm quadrature LC-VCO using darlington cell | |
| Ma et al. | Current-mode cmos active inductor with applications to low-voltage oscillators |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150304 Termination date: 20180621 |