CN101409554A - Loop filter circuit for charge pump phase-locked loop - Google Patents
Loop filter circuit for charge pump phase-locked loop Download PDFInfo
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Abstract
The invention provides a loop filter circuit used in a charge pump phase-locked loop. The charge pump phase-locked loop comprises a frequency and phase discriminator, a charge pump, a loop filter, a frequency divider and a voltage-controlled oscillator; the front end of the loop filter is connected with the charge pump and the rear end is connected with the voltage-controlled oscillator; the loop filter circuit comprises a control logic, a front buffer circuit, a time delay switch and a rear filter circuit; when the time delay switch is conducted, the whole loop filter circuit can operate normally; but when the time delay switch is off, the charge pump is conducted with the front buffer circuit and is not conducted with the rear filter circuit; the time delay circuit of the time delay switch refers delays time of the clock, and the on-off of the time delay switch is controlled by the control logic of the loop filter circuit; by adopting the circuit, the problem of stray reference caused by the mismatching of the upper and lower branch currents in the charge pump is solved, and the performance of the loop filter circuit of the charge pump phase-locked loop is improved.
Description
Technical field
The present invention relates to the phase-locked loop field, relate in particular to the loop filtering circuit that is used for charge pump phase lock loop.
Background technology
Phase-locked loop is used widely in communication transceiver.In the high speed wire communication, phase-locked loop is used for clock recovery and clock generating.In radio communication, phase-locked loop is used to produce local oscillations and modulation, demodulation.Because present nearly all integrated phase lock all is to adopt the charge pump phase lock loop structure, surface analysis mainly is based on charge pump phase locking loop circuit down.
Shown in Figure 1 is the block diagram of a typical charge pump phase-locked loop.This phase-locked loop is made up of phase discriminator, charge pump, loop filtering circuit, frequency divider and voltage controlled oscillator (VCO).Described loop filtering circuit adopts low pass filter usually.Whole loop has constituted negative feedback structure, differs if the signal behind input signal and the voltage controlled oscillator frequency division exists, and then phase discriminator will differ and carry out integration, be converted into electric current by charge pump, changes the size of VCTRL, and regulating frequency is exported to reach balance.Like this, during loop-locking, voltage controlled oscillator is accurately exported the signal of N times of incoming frequency.
For desirable charge pump phase lock loop, after locking, do not differ between the feedback clock of reference clock and voltage controlled oscillator, the charge pump output charge is zero.Control voltage of voltage-controlled oscillator remains unchanged.And in the circuit of reality, because multiple non-ideal factor, make charge pump behind pll lock, although the net charge of output is zero (it is stable to keep pressuring controlling oscillator frequency), but charge pump output shows as the alternating current of existence and reference clock same frequency on time domain, make to occur on the control voltage of voltage-controlled oscillator and the alternating voltage of reference clock same frequency, and then the modulation voltage controlled oscillator, the spuious appearance of reference caused.These non-ideal factors mainly comprise three aspects: charge pump is current mismatch, the leakage current of loop filtering circuit and the path delay mismatch of UP and Down Continuity signal of branch road up and down.Factors such as the switch-charge of charge pump is injected in addition and electric charge is shared, clock feed-through effect and the ground coupling of integrated circuit lining also can bring reference spuious.Wherein, the branch current mismatch is the leading reason that produces with reference to spuious about the charge pump.
In existing charge pump phase-locked loop design, the current source of the last branch road of charge pump is to flow to subsequently low pass filter from power supply, can only adopt the PMOS current source; And the branch current source is to flow to ground from low pass filter down, can only adopt the NMOS current source to realize.Because NMOS and PMOS itself are exactly various types of devices, even in present state-of-the-art manufacturing process, also can't guarantee their coupling.Simultaneously owing to phase-locked loop control voltage need change in the scope of a broad, because the influence of the output resistance that current source is limited, the change of phase-locked loop control voltage is opposite to the influence of NMOS current source and PMOS current source, just be subjected to phase-locked loop control voltage influence and when becoming big, the PMOS current source will diminish when the NMOS current source under same phase-locked loop control voltage condition.This has just further worsened the mismatch of branch road up and down.
When branch current source mismatch up and down, phase-locked loop only flows into filter in each compare cycle net charge is zero, and filter output voltage could keep stablizing, and phase-locked loop just can maintain lock-out state.The net charge that guarantees to flow into filter is zero, up and down the time of current lead-through inevitable variant, the time of the conducting that electric current is little is longer.
Behind pll lock, phase-locked loop is being operated on the reference clock frequency of cycle, and charge pump just produces alternating current relatively constantly.On time domain, alternating current just is carved with by a relatively large margin relatively the time, after UP and Down signal ended, does not have new electric current to inject subsequently, and the electric current alternating component is zero.At this moment the alternating voltage on the low pass filter thereafter comes from previous electric current injection.Therefore, for existing low-pass loop filter, time-domain response is the linear superposition of the time-domain response of the whole transient pulse electric currents in front.
Suppose that in the loop filtering circuit of existing charge pump phase-locked loop, last branch current is 1.2mA, ON time is 2ns; Following branch current is 0.8mA, and ON time is 3ns.Behind pll lock, charge pump is in each compare cycle, the electric current of output as shown in Figure 2, although the net charge of importing on this feasible filter is zero, but on time domain, electric charge is to inject earlier to pull out (perhaps opposite) again, and this can form the alternating component that frequency is reference frequency and harmonic wave thereof by filter impedance, thereby modulation VCO produces with reference to spuious.Fig. 3 is the frequency spectrum of charge pump output current.By Fig. 3, can know and see that static phase makes that the charge pump output frequency is the electric current of reference frequency and each harmonic composition thereof.After this electric current flows into low pass filter, can form the voltage of same frequency.Although low pass filter subsequently can be to this alternating voltage filtering, because low pass filter usually for stability reasons, can not surpass two, three rank, and loop bandwidth is generally 1/10 of reference frequency in integer phase-locked loop the inside; The loop filtering circuit of low pass suppresses limited to this alternating component like this, thereby forms with reference to spuious in phase-locked loop output.Be illustrated in figure 4 as existing 3 rank low pass loop filtering circuit, it comprises three parallel branches, and wherein, first route capacitor C 2 formed, and second route resistance R 1 formed with capacitor C 1 polyphone, and the 3rd route resistance R 2 formed with capacitor C 3 polyphones.
In order to improve the problem of the current mismatch up and down that has charge pump now, two kinds of methods are arranged at present: method 1: as shown in Figure 5, current source branch up and down and a feedback control loop by a mirror image, a current source size-controlled in feedback control loop in the branch road up and down makes the wherein variation of an other electric current of current tracking.Thereby improve mismatch problems.Its exemplary operation principle wherein, in order to alleviate the electric charge sharing problem, has also been introduced a dummy argument branch road as shown in Figure 5.There are several problems in this circuit, and one is that feedback control loop can only limit the charge pump output voltage scope in less charge pump output voltage scope work.Another problem is the feedback control loop limited bandwidth, and when fluctuation took place charge pump output voltage, when being injected into the loop filtering circuit if any electric current, feedback control loop needed certain stabilization time.In addition, because current source is controlled by operational amplifier, make the output noise of charge pump far exceed simple charge pump.Method 2: as shown in Figure 6,, a branch road is adjusted to the another one branch road mated by a branch current being used the mode of inching.This method also has problems: because charge pump output voltage is uncertain, change with operating frequency and technology, variations in temperature, be difficult to by fine setting stable matching on the another one branch road of branch current.
Summary of the invention
The spuious problem of reference that branch current source mismatch is brought about the objective of the invention is to solve in the charge pump, and a kind of loop filtering circuit that is used for charge pump phase lock loop is provided.
Mentality of designing of the present invention is: introduce a delay switch, thereby utilize the discreteness of charge pump phase lock loop output current in time-domain fully, make the spuious inhibition of reference of phase-locked loop be improved.
Design of the present invention is as follows:
A kind of loop filtering circuit that is used for charge pump phase lock loop, described charge pump phase lock loop comprises phase frequency detector, charge pump, loop filtering circuit, frequency divider and voltage controlled oscillator, the preceding termination charge pump of described loop filtering circuit, back termination voltage-controlled oscillator (VCO) is characterized in that: described loop filtering circuit comprises control logic, front end buffer circuit, delay switch and rear end filter circuit; When described delay switch conducting, whole loop filtering circuit operate as normal, and when described delay switch disconnects, described charge pump and the connection of described front end buffer circuit, and obstructed with described rear end filter circuit; The delay circuit of described delay switch is with the reference clock time-delay of the outside input of described phase frequency detector, and be input to the reference clock of described phase frequency detector as the actual use of phase-locked loop, and the disconnection of described delay switch and conducting are by the control logic control of described loop filtering circuit.
Wherein, described delay switch is comprised the steps: by described control logic control
(1) after described pll lock, lock indication signal is imported into described control logic;
(2) delay circuit of described delay switch is delayed time the reference clock of the outside input of described phase frequency detector, and is input to the reference clock of described phase frequency detector as the actual use of phase-locked loop;
(3) judge by described control logic, the preceding Tb second at the rising edge of the reference clock of the actual use of described phase-locked loop, disconnect described delay switch;
(4) described delay switch is disconnected Tb+Ta conducting again after second;
Wherein, the Ta value is finished the required time of frequency discrimination phase demodulation process greater than described charge pump, can finish frequency discrimination phase demodulation process in the time at Ta to guarantee described charge pump, the Tb value is greater than disconnecting the required time of described delay switch, to guarantee before the rising edge of reference clock arrives, disconnecting described delay switch.
Further, described loop filtering circuit is a low pass filter.
Further, described loop filtering circuit adopts one or more technologies that are selected from the following technology group to realize that described technology group comprises complementary metal oxide semiconductors (CMOS) (CMOS) technology, bipolar and complementary metal oxide semiconductors (CMOS) (BICMOS) technology.
The present invention also provides the charge pump phase lock loop that includes described loop filtering circuit.
Wherein, described loop filtering circuit by integrated setting in phase-locked loop intergrated circuit.
Wherein, described loop filtering circuit is set at outside the phase-locked loop intergrated circuit.
Employing the invention solves in the charge pump the spuious problem of reference that branch current source mismatch is up and down brought, and has improved the performance of the loop filtering circuit of charge pump phase lock loop.
Description of drawings
Fig. 1 is a typical phase-locked loop circuit block diagram in the prior art;
The charge pump output AC electric current that Fig. 2 causes for static phase;
Fig. 3 is the frequency spectrum of Fig. 2 electric current;
Fig. 4 is the existing loop filtering circuit that is used for phase-locked loop;
Fig. 5 is for improving a kind of schematic block circuit diagram of the current mismatch up and down that has charge pump now;
Fig. 6 is for improving the another kind of schematic block circuit diagram of the current mismatch up and down that has charge pump now;
Fig. 7 is the schematic diagram of an embodiment of the loop filtering circuit that is used for phase-locked loop of the present invention;
Fig. 8 is the timing waveform of the control signal of the delay switch of the loop filtering circuit that is used for phase-locked loop of the present invention;
Fig. 9 is the realization logic according to a kind of Ta of the present invention and Tb;
Figure 10 is specific embodiment under a kind of CMOS technology of the loop filtering circuit that is used for phase-locked loop of the present invention;
Figure 11 for charge pump current by behind the existing loop filtering circuit, the residual reference frequency and the amplitude of each harmonic thereof;
Figure 12 adopts the present invention, behind the loop filtering circuit, and the residual reference frequency and the amplitude of each harmonic thereof;
Figure 13 for charge pump current by behind the existing loop filtering circuit, the residual reference frequency and the amplitude of each harmonic thereof;
Figure 14 adopts the present invention, behind the loop filtering circuit, and the residual reference frequency and the amplitude of each harmonic thereof;
Figure 15 is the interchange time domain waveform of existing loop filtering circuit output voltage;
Figure 16 adopts the present invention, behind the loop filtering circuit, and the interchange time domain waveform of loop filtering circuit output voltage.
Embodiment
As shown in Figure 7, in one embodiment of the invention, charge pump phase lock loop comprises phase frequency detector, charge pump, loop filtering circuit, frequency divider and voltage controlled oscillator, wherein, and the preceding termination charge pump of loop filtering circuit, back termination voltage-controlled oscillator (VCO).Described loop filtering circuit comprises front end buffer circuit, delay switch S1 and the rear end filter circuit that is made of capacitor C 2_1.Described rear end filter circuit comprises three parallel branches, and wherein, the 3rd route capacitor C 2_2 forms, and second route resistance R 1 formed with capacitor C 1 polyphone, and the 3rd route resistance R 2 formed with capacitor C 3 polyphones.Delay switch S1 is set between front end buffer circuit and the rear end filter circuit, and delay switch S1 can delay time to the reference clock signal of described phase frequency detector, and the disconnection of described delay switch S1 and conducting are controlled by described control logic.
At first, phase-locked loop is operated in non-linear working state before locking, at this moment, causes capacitor C 2_1 saturated for fear of the excessive electric current of charge pump, needs maintained switch S1 to be conducting state all the time.At this moment, the effect of capacitor C 2_1 and C2_2 is equivalent to a capacitor C 2, and whole loop filtering circuit is equivalent to existing three rank low-pass loop filter.
The operating state of phase-locked loop is by the lock detecting signal indication of phase-locked loop.Behind pll lock, charge pump just produces alternating current relatively constantly.On time domain, alternating current just is carved with by a relatively large margin relatively the time, after UP and Down signal ended, does not have new electric current to inject subsequently, and the electric current alternating component is zero.
If use traditional low pass loop filtering circuit, then, suppress although be subjected to filter circuit comparing big transient current constantly directly by filter circuit, still have bigger AC signal and appear at the filter circuit output, as Figure 15.
When adopting filter circuit of the present invention, Tb second before relatively constantly, switch disconnects, and when coming temporarily relatively constantly, big transient current just flows into C2_1.And because switch disconnects, this moment, the filter circuit output can not be affected.At Ta after second.More finish, UP and DOWN finish, owing to there is not the net charge input, at this moment the voltage on the C2_1 tends towards stability, and is equivalent to C2_1 as a buffer capacitor to the current impulse of instantaneous AC charge pump.The buffering back is for the filter circuit after the switch, and input is the voltage on the C2_1, rather than front current impulse relatively constantly.Because the voltage on the C2_1 tends towards stability, amplitude is very little.So it is just very little that AC signal appears at the filter circuit output, as Figure 16.
C2_1 and C2_2 sum can be equal to the C2 of traditional filter circuit the inside, can guarantee that like this loop filtering circuit equivalent is in traditional filter circuit behind switch conduction.Need guarantee that C2_1 can not occur being charged to the saturated C2_1 that determines by charge pump after locking according to the electric current of charge pump.For example, suppose that maximum static phase is 2ns, charge pump current is 1mA, and the charge pump output voltage scope is that then C2_1 need be greater than 7pF to 1.5V. for 0.3V.For common design, this requirement is satisfied than being easier to.And C2_1 just can get C2-C2_1.Certainly, also can be according to bringing the actual design parameter into, such as the gain of VCO, the electric current of charge pump, frequency dividing ratio, reference frequency and the loop bandwidth and the spuious inhibition that need are brought traditional charge pump phase lock loop loop design formula into and are determined concrete capacitance.
Be illustrated in figure 8 as the timing waveform of control signal of the delay switch of loop filtering circuit of the present invention.Be illustrated in figure 9 as realization logic according to a kind of Ta of the present invention and Tb.The requirement of control logic be before the rising edge of reference clock Tb second, make switch disconnect; At reference clock later Ta after second, switch conduction.Then, Tb second before the rising edge of reference clock next time, switch disconnects once more, the rising edge Ta second of conducting more later, so circulation.The pulse duration of charge pump output current is depended in the selection of Ta, and requirement is at Ta in the time, the frequency discrimination phase demodulation process of finishing of phase frequency detector and charge pump.Simultaneously, the time of Ta is subjected to the constraint of loop stability.(more than 10 times, charge pump phase lock loop must meet this requirement usually) can be approximated to a continuous system to phase-locked loop when reference frequency is far longer than PLL loop bandwidth.At this moment, can become a delay unit that is inserted between charge pump and the loop filtering circuit to the equivalence time of delay of Ta
This is equivalent to increase on the angle in the transfer function of representing with mould value and angle of phase-locked loop
, be equal in complex number plane, the phase place of the transfer function of phase-locked loop is moved down
On phase margin, phase margin has reduced
Ta chooses other relating to parameters with phase-locked loop, by the concrete numerical value of concrete application decision.But being the phase margin of phase-locked loop itself, total constraints adds the extra phase lag that the loop time-delay brings
, should satisfy the stability requirement of phase-locked loop.For example, the loop bandwidth when phase-locked loop is
(open-loop gain exists
The place is 0dB), at this moment phase margin descends than existing loop filter
If
T
a=20ns, phase margin decrease are 0.1 °, can ignore T this moment fully
aThe phase margin of bringing changes.The selection of Tb need be considered the turn-off time of switch.Need guarantee that before the reference rising edge came, switch turn-offed.
As shown in figure 10, be specific embodiment under a kind of CMOS technology of the present invention.In Figure 10, switch constitutes complementary switch by Pmos and NMOS.For clock feedthrough and the electric charge injection effect that reduces switch, the signal SWP and the SWN of control switch done RC filtering, purpose is to reduce control signal to rise and descending slope, thereby reduces clock feedthrough and electric charge injection effect.
As shown in figure 11, for through behind the existing filter, at the frequency spectrum of the voltage waveform of filter output.The design parameter that is adopted is: reference frequency is 40MHZ, and last branch current is 1.2mA, and ON time is 2ns; Following branch current is 0.8mA, and ON time is 3ns.R1=430 ohm, C1 are 8.2nF, and C2 is 470pF, and R2 is 5K, and C3 is 120pF.This low pass filter-3dB, frequency is 250KHZ, applied PLL loop bandwidth is 100K.Because reference frequency is 400 times of loop bandwidth, reference frequency can obtain more inhibition.As shown in figure 12, behind the loop filtering circuit of charge pump current through the present invention's proposition, the frequency spectrum of filter output.Can see that the loop filtering circuit that the present invention proposes can suppress 20dB to the reference frequency place more.When being applied to the integer phase-locked loop, loop bandwidth is 1/10 of a reference frequency usually;
As shown in figure 13, for through behind the existing filter, at the frequency spectrum of the voltage waveform of filter output.Wherein, reference frequency is 1MHZ, and PLL loop bandwidth is 100K.As shown in figure 14, behind the loop filtering circuit of charge pump current through the present invention's proposition, the frequency spectrum of filter output.Can see that the loop filtering circuit that the present invention proposes can suppress 70dB to the reference frequency place more.
As shown in figure 15, be the interchange time domain waveform of existing loop filtering circuit output voltage, wherein, reference frequency is 1MHZ, and PLL loop bandwidth is 100K.As shown in figure 16, for adopting the present invention, behind the loop filtering circuit, the interchange time domain waveform of loop filtering circuit output voltage, wherein, reference frequency is 1MHZ, and PLL loop bandwidth is 100K.
Claims (10)
1, a kind of loop filtering circuit that is used for charge pump phase lock loop, described charge pump phase lock loop comprises phase frequency detector, charge pump, loop filtering circuit, frequency divider and voltage controlled oscillator, the preceding termination charge pump of described loop filtering circuit, back termination voltage-controlled oscillator (VCO) is characterized in that: described loop filtering circuit comprises control logic, front end buffer circuit, delay switch and rear end filter circuit; When described delay switch conducting, whole loop filtering circuit operate as normal, and when described delay switch disconnects, described charge pump and the connection of described front end buffer circuit, and obstructed with described rear end filter circuit; The delay circuit of described delay switch is with the reference clock time-delay of the outside input of described phase frequency detector, and be input to the reference clock of described phase frequency detector as the actual use of phase-locked loop, and the disconnection of described delay switch and conducting are by the control logic control of described loop filtering circuit.
2, be used for the loop filtering circuit of charge pump phase lock loop according to claim 1, it is characterized in that, described front end buffer circuit is a capacitor loop.
3, be used for the loop filtering circuit of charge pump phase lock loop according to claim 1, it is characterized in that, described delay switch is comprised the steps: by described control logic control
(1) after described pll lock, lock indication signal is imported into described control logic;
(2) delay circuit of described delay switch is delayed time the reference clock of the outside input of described phase frequency detector, and is input to the reference clock of described phase frequency detector as the actual use of phase-locked loop;
(3) judge by described control logic, the preceding Tb second at the rising edge of the reference clock of the actual use of described phase-locked loop, disconnect described delay switch;
(4) described delay switch is disconnected Tb+Ta conducting again after second;
Wherein, the Ta value is finished the required time of frequency discrimination phase demodulation process greater than described charge pump, finishes frequency discrimination phase demodulation process to guarantee described charge pump in the time at Ta, and the Tb value is greater than disconnecting the required time of described delay switch, to guarantee before the rising edge of reference clock arrives, disconnecting described delay switch.
As being used for the loop filtering circuit of charge pump phase lock loop as described in the claim 2, it is characterized in that 4, described delay switch is comprised the steps: by described control logic control
(1) after described pll lock, lock indication signal is imported into described control logic;
(2) delay circuit of described delay switch is delayed time the reference clock of described phase frequency detector, and is input to described control logic;
(3) judge by described control logic, the preceding Tb second at the rising edge of described reference clock, disconnect described delay switch;
(4) described delay switch is disconnected Tb+Ta conducting again after second;
Wherein, the Ta value is finished the required time of frequency discrimination phase demodulation process greater than described charge pump, finishes frequency discrimination phase demodulation process to guarantee described charge pump in the time at Ta, and the Tb value is greater than the required time of the described delay switch of conducting, to guarantee before the rising edge of reference clock arrives, disconnecting described delay switch.
5, be used for the loop filtering circuit of charge pump phase lock loop according to claim 1, it is characterized in that, described loop filtering circuit is a low pass filter.
6, the loop filtering circuit that is used for charge pump phase lock loop according to claim 1, it is characterized in that, described loop filtering circuit adopts one or more technologies that are selected from the following technology group to realize that described technology group comprises complementary metal oxide semiconductors (CMOS) (CMOS) technology, bipolar and complementary metal oxide semiconductors (CMOS) (BICMOS) technology.
7, as being used for the loop filtering circuit of charge pump phase lock loop as described in the claim 2, it is characterized in that, described loop filtering circuit adopts one or more technologies that are selected from the following technology group to realize that described technology group comprises complementary metal oxide semiconductors (CMOS) (CMOS) technology, bipolar and complementary metal oxide semiconductors (CMOS) (BICMOS) technology.
8. a charge pump phase lock loop is characterized in that, it includes each described loop filtering circuit in the claim 1 to 7.
9, charge pump phase lock loop as claimed in claim 8 is characterized in that, described loop filtering circuit by integrated setting in phase-locked loop intergrated circuit.
10, charge pump phase lock loop as claimed in claim 8 is characterized in that, described loop filtering circuit is set at outside the phase-locked loop intergrated circuit.
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| CN2007101757269A CN101409554B (en) | 2007-10-11 | 2007-10-11 | Loop filter circuit for charge pump phase-locked loop |
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| CN2007101757269A CN101409554B (en) | 2007-10-11 | 2007-10-11 | Loop filter circuit for charge pump phase-locked loop |
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