CN104767523A - Second-order switch low-pass filter in charge pump phase-locked loop and locking method adopting second-order switch low-phase filter to achieve loop circuit - Google Patents
Second-order switch low-pass filter in charge pump phase-locked loop and locking method adopting second-order switch low-phase filter to achieve loop circuit Download PDFInfo
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Abstract
The invention discloses a second-order switch low-pass filter in a charge pump phase-locked loop and a locking method adopting the second-order switch low-phase filter to achieve a loop circuit and relates to the field of charge pump phase-locked loop rapid locking. The second-order switch low-pass filter in the charge pump phase-locked loop and the locking method adopting the second-order switch low-phase filter to achieve the loop circuit aim at solving the problem that the big VCO control voltage shake is caused by the fact that an exiting mode of enlarging loop circuit bandwidth is used for shortening phase-locked loop locking time. The Icp signal output end of a charge pump serves as the Icp signal input end of a second-order switch low-pass filtering unit, the Vctrll signal input end and the signal input end of the second-order switch low-pass filtering unit are connected with the Vctrll signal output end and the signal output end of a switch control unit respectively, UP and DW signals serve as the input ends of the switch control unit, a pulse width identification unit is adopted to identify the pulse width output by a phase frequency detector of the charge pump phase-locked loop, the accurate adjustment of the phase frequency detector on the VCO control voltage is guaranteed, and the shortening of the locking time is achieved. The second-order switch low-pass filter in the charge pump phase-locked loop and the locking method adopting the second-order switch low-phase filter to achieve the loop circuit can be used in charge pump phase-locked loop systems.
Description
Technical field
The present invention relates in charge pump phase locking loop circuit and increase loop bandwidth and shake large situation with the VCO control voltage shortened caused by locking time.Belong to charge pump phase lock loop quick lock in field.
Background technology
Charge pump phase lock loop system, as shown in Figure 1, reference signal enters the input of phase frequency detector (PFD), the two paths of signals that phase frequency detector exports is UP signal and DW signal, this two paths of signals is input to charge pump (CP), Icp signal is exported by charge pump, this signal enters in loop filter (LPF), the filtering signal output of loop filter connects the filtering signal input of voltage controlled oscillator (VCO), the input of frequency divider is entered by the output outputting oscillation signal of voltage controlled oscillator, the output of frequency divider connects the input of phase frequency detector, loop filter in charge pump phase locking loop circuit adopts second-order low-pass filter structure, can the effective noise introduced of filtering input signal and charge pump.For a charge pump phase lock loop system, as shown in Figure 4, loop filter, except the radio-frequency component in filtering low frequency charge pumping electric current, also needs to keep the control voltage to rear class voltage controlled oscillator.
In the phase-locked loop of structure as shown in Figure 4, phase-locked loop by Vctrl in the process of the last locking that powers on situation of change as shown in Figure 5.When the frequency phase-difference that the signal that pre-frequency division exports and loop divider feed back signal is larger, the pulse duration that PFD exports is wider, and Vctrl signal fluctuation is larger; The difference on the frequency feeding back signal along with pre-divider output signal and loop divider reduces, and the pulse duration that PFD exports reduces gradually, and Vctrl signal fluctuation reduces gradually.Be reduced to a certain degree gradually along with Vctrl signal fluctuation, between electric capacity C2 and resistance R1, the switching of switch will occupy main status to the interference of Vctrl signal, even switch becomes a great resistance thus changes the loop bandwidth calculated, and finally causes whole loop losing lock.As everyone knows, for charge pump phase lock loop system, it is not linear, but a discrete-time system, the situation that the switch that there is UP and DW signal controlling disconnects simultaneously, differs comparatively large due to electric capacity C1 and C2 capacitance and between them, the resistance R of kilo-ohm level exists, therefore when UP and my DW signal disconnect simultaneously, there is voltage difference between electric capacity C2 and electric capacity C1, the electric charge on C2 and the electric charge on C1 will be redistributed.Therefore decline after causing the rising of the voltage cycle of Vctrl, phase frequency detector can not play completely to the corrective action of VCO again, makes the magnitude of voltage of Vctrl increase in fluctuation.And exactly because this fluctuation can cause the prolongation of loop-locking time.
Summary of the invention
The present invention is that the VCO control voltage brought to shorten phase lock loop lock on time to solve existing increase loop bandwidth mode shakes large problem.Second order switch low pass filter in charge pump phase lock loop is now provided and adopts this second order switch low pass filter to realize the locking means of loop.
Second order switch low pass filter in charge pump phase lock loop, it comprises second order switch low-pass filter unit and switch control unit (2),
The Icp signal input part of described second order switch low-pass filter unit connects the Icp signal output part of previous stage structure charge pump, the Vctrll signal output part of the Vctrll signal input part connecting valve control unit of second order switch low-pass filter unit, second order switch low-pass filter unit
signal input part connecting valve control unit
signal output part,
The UP signal output part of phase frequency detector as the UP signal input part of switch control unit,
The DW signal output part of phase frequency detector as the DW signal input part of switch control unit,
The Vctrl signal output part of second order switch low-pass filter unit is as the signal output part of second order switch low pass filter.
According to the second order switch low pass filter in charge pump phase lock loop, second order switch low-pass filter unit comprises cmos switch, resistance R1, electric capacity C1 and electric capacity C2,
Switch control unit comprises pulse duration recognition unit, NAND gate, NOR gate and inverter,
Icp signal output part one end of contact resistance R1 and a signal input part of cmos switch simultaneously of previous stage structure charge pump, the other end of resistance R1 connects one end of electric capacity C1, and the other end of electric capacity C1 connects power supply ground,
The Vctrl signal output part of cmos switch connects one end of electric capacity C2, and the other end of electric capacity C2 connects power supply ground,
The Vctrll signal input part of cmos switch connects the Vctrll signal output part of NAND gate and the input of inverter simultaneously,
Cmos switch
signal input part connects inverter
signal output part,
An input of NAND gate connects the pulse signal output end p of pulse duration recognition unit, and another input of NAND gate connects the output q of NOR gate,
UP signal output part connects a pulse signal input terminal of pulse duration recognition unit and a signal input part of NOR gate simultaneously,
DW signal output part connects another pulse signal input terminal of pulse duration recognition unit and another input of NOR gate simultaneously.
Second order switch low pass filter in charge pump phase lock loop realizes the locking means of loop,
UP signal input part and DW signal input part are high level and high-level pulse width is not less than the minimum identification width of pulsewidth recognition unit, then pulsewidth recognition unit output pulse signal p is high level,
Deliver to the input of NAND gate together with described pulse signal p and UP signal and the DW signal result q after NOR gate, now the Vctrll signal output part of NAND gate is the anti-of the output q of NOR gate,
the output q of signal output part AND OR NOT gate consistent, cmos switch now closes during the low pass filter discharge and recharge of second order switch at charge pump, stop disconnecting during the low pass filter discharge and recharge of second order switch at charge pump, block on electric capacity C2 and the loop that between electric capacity C1, electric charge is redistributed, within the time period of non-discharge and recharge, make magnitude of voltage on electric capacity C2 keep, realize the locking of loop.
Second order switch low pass filter in charge pump phase lock loop realizes the locking means of loop,
UP signal input part or DW signal input part are high level and high-level pulse width is less than the minimum identification width of pulsewidth recognition unit, then the pulse signal p of pulsewidth recognition unit is low level,
Deliver to the input of NAND gate together with described pulse signal p and UP signal and the DW signal result q after NOR gate, now the Vctrll signal output part of NAND gate is high level, NOR gate
signal output part is low level, Vctrll signal output part and
signal output part all controls cmos switch in second-order low-pass filter unit and closes always, and loop completes PGC demodulation by self-characteristic.
Beneficial effect of the present invention: the present invention, the Vctrll signal that the switching of the cmos switch in second order switch low-pass filter unit is exported by switch control unit and
signal controlling.Adopt cmos switch to slacken when UP and DW signal is low level, because the electric charge between electric capacity C2 and electric capacity C1 moves, decline again after causing the voltage rise of Vctrl, and the fluctuation of the Vctrl magnitude of voltage caused.
The present invention adopts pulsewidth recognition unit to identify the pulse duration that charge pump phase lock loop phase frequency detector (PFD) exports, when arbitrary signal in UP or the DW signal that PFD exports is high level and high-level pulse width is not less than the minimum identification width of pulsewidth recognition unit, high level recognition unit output end p is high level, the input of NAND gate is delivered to the result q of UP and DW signal after NOR gate, now the Vctrll signal output part of NAND gate is the anti-of q
signal output part is consistent with q, cmos switch now, stops disconnecting during second order switch low pass filter discharge and recharge (UP or DW signal is low high level) at charge pump to closed time the discharge and recharge of second order switch low pass filter (UP or DW signal is arbitrary is high level) at charge pump.Block on electric capacity C2 and the loop that between electric capacity C1, electric charge is redistributed, within the time period of non-discharge and recharge, electric capacity makes magnitude of voltage on C2 keep, thus ensures that phase frequency detector accurately adjusts VCO control voltage, and then realizes shortening locking time.
But when arbitrary signal in UP or the DW signal that PFD exports is high level but high-level pulse width is less than the minimum identification width of pulsewidth recognition unit or is low level, high level recognition unit output end p is low level, the input of NAND gate is delivered to the result q of UP and DW signal after NOR gate, now the Vctrll signal output part of NAND gate is high level
signal output part is low level.Vctrll and
this closes cmos switch in the second-order low-pass filter unit of signal controlling always, and the second-order low-pass filter that now charge pump phase lock loop is traditional with band is as good as, so charge pump phase lock loop relies on loop self-characteristic to complete the locking of last phase place.
In process described above, as shown in Figure 8, there is not the situation that rising as shown in Figure 5 declines again in Vctrl signal to VCO control waveform, and approximately linear rises.
Can see that from Fig. 8 after improving, circuit is to the change of VCO control signal Vctrl, the final constant required time of Vctrl signal value in comparison diagram 8 and Fig. 5, the circuit after improvement comparatively before circuits shortens about 10us.
Before and after contrast improves, the output signal eye pattern of phase-locked loop, verifies further.From Fig. 5 and Fig. 8, after the 70us that powers on, the VCO control signal Vctrl of two circuit all becomes straight line, is similar to and thinks that two loops have all locked.Therefore to get initial time be 70.0015us to the signal exported two circuit VCO, and the end time is 80us, and the cycle is the eye Diagram Analysis of 4.4444ns (calculate gained stablize output signal frequency be 450MHz), obtains result as shown in Fig. 9 to Figure 12.The rising edge and the trailing edge that output signal eye pattern before and after being improved by comparison circuit are known, and second order switch filter can shorten the locking time of phase-locked loop.
Accompanying drawing explanation
Fig. 1 is the principle schematic of charge pump phase lock loop system;
Fig. 2 is the work schedule graph of a relation of switch control unit when the phase frequency detector output pulse width described in embodiment four is greater than pulse duration recognition unit minimum value, UP is that phase frequency detector exports UP signal, DW is that phase frequency detector exports DW signal, p is pulse duration recognition unit output signal, q is UP and DW signal or non-output signal, Vctrll and
for a pair reversed-phase output signal of switch control unit;
Fig. 3 is the work schedule graph of a relation of switch control unit when the phase frequency detector output pulse width described in embodiment five is less than pulse duration recognition unit minimum value;
Fig. 4 is the low pass filter of electrically charged pump;
Fig. 5 be improve before CPPLL power on locking Vctrl signal graph;
Fig. 6 is the principle schematic of the second order switch low pass filter in the charge pump phase lock loop described in embodiment one;
Fig. 7 is the principle schematic of the second order switch low pass filter in the charge pump phase lock loop described in embodiment two;
Fig. 8 be improve after charge pump phase lock loop power on locking Vctrl signal graph;
Fig. 9 is for improving front pll output signal rising edge eye pattern, and in figure, the coordinate of A is (960.91 psecs, 900.063 millivolts), the coordinate of B is (1.73601 nanoseconds, 900.07 millivolts), the coordinate of △ AB is (775.098 psecs, 7.45238 microvolts);
Figure 10 is for improving rear pll output signal rising edge eye pattern, and in figure, the coordinate of A is (1.74561 nanoseconds, 900.002 millivolts), the coordinate of B is (1.83843 nanoseconds, 900.002 millivolts), the coordinate of △ AB is (92.8252 psecs, 37.8532 receive volt);
Figure 11 is for improving front pll output signal trailing edge eye pattern, and in figure, the coordinate of A is (2.11127 nanoseconds, 900.002 millivolts), the coordinate of B is (2.88623 nanoseconds, 900.005 millivolts), the coordinate of △ AB is (774.965 psecs, 2.60163 microvolts);
Figure 12 is for improving rear pll output signal trailing edge eye pattern, and in figure, the coordinate of A is (2.89588 nanoseconds, 900 millivolts), the coordinate of B is (2.98872 nanoseconds, 900 millivolts), the coordinate of △ AB is (92.8359 psecs, 30.671 receive volt).
Embodiment
Embodiment one: illustrate present embodiment, the second order switch low pass filter in the charge pump phase lock loop described in present embodiment with reference to Fig. 6, it comprises second order switch low-pass filter unit 1 and switch control unit 2,
The Icp signal input part of described second order switch low-pass filter unit 1 connects the Icp signal output part of previous stage structure charge pump 11, the Vctrll signal output part of the Vctrll signal input part connecting valve control unit 2 of second order switch low-pass filter unit 1, second order switch low-pass filter unit 1
signal input part connecting valve control unit 2
signal output part,
The UP signal output part of phase frequency detector as the UP signal input part of switch control unit 2,
The DW signal output part of phase frequency detector as the DW signal input part of switch control unit 2,
The Vctrl signal output part of second order switch low-pass filter unit 1 is as the signal output part of second order switch low pass filter.
Embodiment two: illustrate present embodiment with reference to Fig. 7, present embodiment is described further the second order switch low pass filter in the charge pump phase lock loop described in embodiment one, in present embodiment, second order switch low-pass filter unit 1 comprises cmos switch 3, resistance R1, electric capacity C1 and electric capacity C2
Switch control unit 2 comprises pulse duration recognition unit 7, NAND gate 8, NOR gate 9 and inverter 10,
Icp signal output part one end of contact resistance R1 and a signal input part of cmos switch 3 simultaneously of previous stage structure charge pump 11, the other end of resistance R1 connects one end of electric capacity C1, and the other end of electric capacity C1 connects power supply ground,
The Vctrl signal output part of cmos switch 3 connects one end of electric capacity C2, and the other end of electric capacity C2 connects power supply ground,
The Vctrll signal input part of cmos switch 3 connects the Vctrll signal output part of NAND gate 8 and the input of inverter 10 simultaneously,
Cmos switch 3
signal input part connects inverter 10
signal output part,
An input of NAND gate 8 connects the pulse signal output end p of pulse duration recognition unit 7, and another input of NAND gate 8 connects the output q of NOR gate 9,
UP signal output part connects a pulse signal input terminal of pulse duration recognition unit 7 and a signal input part of NOR gate 9 simultaneously,
DW signal output part connects another pulse signal input terminal of pulse duration recognition unit 7 and another input of NOR gate 9 simultaneously.
Embodiment three: illustrate present embodiment with reference to Fig. 7, present embodiment is described further the second order switch low pass filter in the charge pump phase lock loop described in embodiment one, in present embodiment, charge pump (11) comprises a voltage source U1, No. two voltage source U2, a K switch 1 and No. two K switch 2
The positive pole of a described voltage source U1 connects power supply, the negative pole of a voltage source U1 connects one end of a K switch 1, the other end of a K switch 1 connects one end of No. two K switch 2, the other end of No. two K switch 2 connects the positive pole of No. two voltage source U2, the control end of a K switch 1 connects the UP signal input part of phase frequency detector, and the control end of No. two K switch 2 connects the DW signal input part of phase frequency detector.
Embodiment four: illustrate present embodiment with reference to Fig. 2, present embodiment is the locking means that second order switch low pass filter in the charge pump phase lock loop according to embodiment one realizes loop, in present embodiment,
UP signal input part and DW signal input part are high level and high-level pulse width is not less than the minimum identification width of pulsewidth recognition unit 7, then pulsewidth recognition unit 7 output pulse signal p is high level,
Deliver to the input of NAND gate 8 together with described pulse signal p and UP signal and the DW signal result q after NOR gate 9, now the Vctrll signal output part of NAND gate 8 is the anti-of the output q of NOR gate 9,
the output q of signal output part AND OR NOT gate 9 consistent, cmos switch 3 now closes during the low pass filter discharge and recharge of second order switch at charge pump, stop disconnecting during the low pass filter discharge and recharge of second order switch at charge pump, block on electric capacity C2 and the loop that between electric capacity C1, electric charge is redistributed, within the time period of non-discharge and recharge, make magnitude of voltage on electric capacity C2 keep, realize the locking of loop.
Embodiment five: illustrate present embodiment with reference to Fig. 3, present embodiment is the locking means that second order switch low pass filter in the charge pump phase lock loop according to embodiment one realizes loop, in present embodiment,
UP signal input part or DW signal input part are high level and high-level pulse width is less than the minimum identification width of pulsewidth recognition unit 7, then the pulse signal p of pulsewidth recognition unit 7 is low level,
Deliver to the input of NAND gate 8 together with described pulse signal p and UP signal and the DW signal result q after NOR gate 9, now the Vctrll signal output part of NAND gate 8 is high level, NOR gate 9
signal output part is low level, Vctrll signal output part and
signal output part all controls cmos switch 3 in second-order low-pass filter unit and closes always, and loop completes PGC demodulation by self-characteristic.
Claims (5)
1. the second order switch low pass filter in charge pump phase lock loop, is characterized in that, it comprises second order switch low-pass filter unit (1) and switch control unit (2),
The Icp signal input part of described second order switch low-pass filter unit (1) connects the Icp signal output part of previous stage structure charge pump (11), the Vctrll signal output part of Vctrll signal input part connecting valve control unit (2) of second order switch low-pass filter unit (1), second order switch low-pass filter unit (1)
signal input part connecting valve control unit (2)
signal output part,
The UP signal output part of phase frequency detector as the UP signal input part of switch control unit (2),
The DW signal output part of phase frequency detector as the DW signal input part of switch control unit (2),
The Vctrl signal output part of second order switch low-pass filter unit (1) is as the signal output part of second order switch low pass filter.
2. the second order switch low pass filter in charge pump phase lock loop according to claim 1, is characterized in that, second order switch low-pass filter unit (1) comprises cmos switch (3), resistance R1, electric capacity C1 and electric capacity C2,
Switch control unit (2) comprises pulse duration recognition unit (7), NAND gate (8), NOR gate (9) and inverter (10),
Icp signal output part one end of contact resistance R1 and a signal input part of cmos switch (3) simultaneously of previous stage structure charge pump (11), the other end of resistance R1 connects one end of electric capacity C1, and the other end of electric capacity C1 connects power supply ground,
The Vctrl signal output part of cmos switch (3) connects one end of electric capacity C2, and the other end of electric capacity C2 connects power supply ground,
The Vctrll signal input part of cmos switch (3) connects the Vctrll signal output part of NAND gate (8) and the input of inverter (10) simultaneously,
Cmos switch (3)
signal input part connects inverter (10)
signal output part,
An input of NAND gate (8) connects the pulse signal output end p of pulse duration recognition unit (7), and another input of NAND gate (8) connects the output q of NOR gate (9),
UP signal output part connects a pulse signal input terminal of pulse duration recognition unit (7) and a signal input part of NOR gate (9) simultaneously,
DW signal output part connects another pulse signal input terminal of pulse duration recognition unit (7) and another input of NOR gate (9) simultaneously.
3. the second order switch low pass filter in charge pump phase lock loop according to claim 1, is characterized in that, charge pump (11) comprises a voltage source U1, No. two voltage source U2, a K switch 1 and No. two K switch 2,
The positive pole of a described voltage source U1 connects power supply, the negative pole of a voltage source U1 connects one end of a K switch 1, the other end of a K switch 1 connects one end of No. two K switch 2, the other end of No. two K switch 2 connects the positive pole of No. two voltage source U2, the control end of a K switch 1 connects the UP signal input part of phase frequency detector, and the control end of No. two K switch 2 connects the DW signal input part of phase frequency detector.
4. the second order switch low pass filter in charge pump phase lock loop according to claim 1 realizes the locking means of loop, it is characterized in that,
UP signal input part and DW signal input part are high level and high-level pulse width is not less than the minimum identification width of pulsewidth recognition unit (7), then pulsewidth recognition unit (7) output pulse signal p is high level,
The input of NAND gate (8) is delivered to together with described pulse signal p and UP signal and the DW signal result q after NOR gate (9), now the Vctrll signal output part of NAND gate (8) is the anti-of the output q of NOR gate (9)
the output q of signal output part AND OR NOT gate (9) consistent, cmos switch (3) now closes during the low pass filter discharge and recharge of second order switch at charge pump, stop disconnecting during the low pass filter discharge and recharge of second order switch at charge pump, block on electric capacity C2 and the loop that between electric capacity C1, electric charge is redistributed, within the time period of non-discharge and recharge, make magnitude of voltage on electric capacity C2 keep, realize the locking of loop.
5. the second order switch low pass filter in charge pump phase lock loop according to claim 1 realizes the locking means of loop, it is characterized in that,
UP signal input part or DW signal input part are high level and high-level pulse width is less than the minimum identification width of pulsewidth recognition unit (7), then the pulse signal p of pulsewidth recognition unit (7) is low level,
The input of NAND gate (8) is delivered to together with described pulse signal p and UP signal and the DW signal result q after NOR gate (9), now the Vctrll signal output part of NAND gate (8) is high level, NOR gate (9)
signal output part is low level, Vctrll signal output part and
signal output part all controls cmos switch (3) in second-order low-pass filter unit and closes always, and loop completes PGC demodulation by self-characteristic.
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| CN201510166393.8A CN104767523B (en) | 2015-04-09 | 2015-04-09 | Second order in charge pump phase lock loop is switched low-pass filter and the locking means of loop is realized using second order switch low-pass filter |
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| CN201510166393.8A CN104767523B (en) | 2015-04-09 | 2015-04-09 | Second order in charge pump phase lock loop is switched low-pass filter and the locking means of loop is realized using second order switch low-pass filter |
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