CN103956382A - Groove power device structure and manufacturing method thereof - Google Patents
Groove power device structure and manufacturing method thereof Download PDFInfo
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- CN103956382A CN103956382A CN201410165169.2A CN201410165169A CN103956382A CN 103956382 A CN103956382 A CN 103956382A CN 201410165169 A CN201410165169 A CN 201410165169A CN 103956382 A CN103956382 A CN 103956382A
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- groove
- power device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Abstract
The invention discloses a groove power device structure and a manufacturing method thereof. The groove power device structure comprises an active area and a terminal, wherein a groove is formed in a first photolithography mask layer from the outermost periphery of the active area to the edge of the device, an LOCOS area is arranged on a second photolithography mask layer, a contact hole is formed in the second photolithography mask layer, a source electrode and a grid electrode are arranged on a fourth photolithography mask layer, and groove isolation is combined with LOCOS. On the basis of advantages of various terminal structures, the structure is simple in process, low in cost, small in occupied area and wide in voltage application range and the like.
Description
Technical field
The present invention relates to semiconductor device and manufacture method technical field thereof, especially a kind of trench power device structure and manufacture method thereof.
Background technology
At present, metal oxide semiconductor field effect tube (MOSFET), igbt (IGBT), trench metal barrier Schottky diode (TMBS) and super barrier diode (SBD) etc. is several of paramount importance power devices.At industrial electronic, there is their ample scope for abilities in all fields of household electrical appliances industry and consumer electronics.Switching power circuit, all be unable to do without their figure in rectification circuit and drive circuit.Power device requires the large electric current of forward, oppositely large voltage.Invent since power device, improve its reverse voltage endurance capability and just become an important topic.
The voltage endurance capability of power device is made up of two parts: the one, and active area is withstand voltage, and the 2nd, terminal is withstand voltage, and wherein either party is withstand voltage not, just can not meet the demands.The problem of withstand voltage of active area is relatively simple, as long as select suitable material and technology just can realize.And terminal is withstand voltage quite different, it is not only relevant with material and technique, also relevant with the terminal structure of device, so need to do special processing.If Fig. 1 is not for doing any improved terminal structure, due to equipotential surface bending, electric field collects, and raises internal field, causes withstand voltage reduction.So just occur that a lot of new constructions are to improve terminal voltage endurance capability, such as: LOCOS structure, potential dividing ring structure, field plate structure and groove isolation construction etc.Improvement structure mentioned above, its basic ideas increase equipotential surface radius of curvature nothing more than, to reach the effect that reduces surface field or knot electric field.
Nowadays, people take above-described terminal structure or several combining structure wherein, design many satisfactory power devices.But generally speaking, each terminal structure has its advantage, has again its deficiency.Such as the advantage of potential dividing ring structure is that technique is relatively simple, and that shortcoming is area occupied is large and affected by environment larger, needs protective mulch, the principle of utilizing electric field to end at trenched side-wall for groove isolation construction as shown in Figure 2 improves withstand voltage object to reach, the method device below 100V is feasible, because voltage is lower, depletion layer can not be walked around channel bottom and past extension, but along with the increasing of voltage, depletion layer is and then down expansion also, just have the risk of walking around groove, in order to solve this risk, only add deep trench, can bring the easy premature breakdown problem of channel bottom so simultaneously, so just formed channel bottom puncture cannot be simultaneously satisfied with P-N junction breakdown problem, so trench isolations only be suitable for lower than 100V product.
Summary of the invention
The goal of the invention of patent of the present invention is: avoid the deficiencies in the prior art, a kind of trench power device structure and manufacture method thereof are provided.
For achieving the above object, the technical scheme that the present invention takes is: include source region and terminal two-part structure, wherein, active area outermost makes a circle, and groove starts until device edge, groove is located in ground floor reticle, second layer reticle is provided with LOCOS region, and second layer reticle is provided with contact hole, and the 4th layer photoetching version is provided with source electrode and grid.
Further, the described trench isolations of taking combines with LOCOS.
Further, the 4th described layer photoetching version is metal level.
The present invention also provides a kind of manufacture method of trench power device structure, and its step is as follows:
Step 1, selects suitable material use ground floor reticle to form groove, deposit or thermal process growth one deck silicon nitride;
Step 2, utilizes second layer reticle to output LOCOS region, removes the silicon nitride in LOCOS region, with chemistry or the long thermal oxide layer of physical process;
Step 3, then the not silicon nitride removal of opened areas, long grid oxygen, depositing polysilicon, polysilicon returns and is carved into raw material silicon surface, and tagma is injected and is advanced, and source region is injected and is advanced;
Step 4, deposit separator, utilizes the 3rd reticle perforate, hole etching;
Step 5, depositing metal, utilizes the 4th layer photoetching version to form source electrode and grid.
In sum, owing to having adopted technique scheme, the invention has the beneficial effects as follows:
1, the advantage based on various terminal structures, makes technique of the present invention simple, with low cost, and area occupied is considerably less and have advantages such as very wide voltage adaptation scope.
2,, under the same terms, take structure that trench isolations combines with LOCOS than low at least one the order of magnitude of the electric leakage of traditional structure.
3, voltage endurance capability is stronger, and under the same terms, conventional art punctures at 34V, and punctures to 40V after taking trench isolations to combine with LOCOS.
4, terminal size is little, and it is withstand voltage that the terminal of 10um just can realize 30V, and conventional art will be realized equal performance, and size is at least 40um, so take technology that trench isolations combines with LOCOS only to account for only to account for traditional 1/4, even can accomplish less.
Brief description of the drawings
Fig. 1 does any improved terminal structure;
Fig. 2 is that trench isolations only goes for the product structure lower than 100V;
Fig. 3 is the result of calculation figure that takes trench isolations to combine with LOCOS;
Fig. 4 is that potential dividing ring technology terminal punctures calculated curve;
Fig. 5 is MOSFET single tube vertical view;
Fig. 6 is ground floor reticle, and active area and terminal trenches form figure;
Fig. 7 is second layer reticle, and LOCOS structure forms figure;
Fig. 8 removes silicon nitride, only surplus peripheral oxide layer figure;
Fig. 9 forms grid oxygen and grid polycrystalline in groove;
Figure 10 is source region and tagma formation figure;
Figure 11 is source, grid contact hole formation figure;
Figure 12 is the tangential profile of figure five B-B.
Mark in figure: 1-source metal, 2-gate metal layer, 3-oxide isolation layer thing, 4-polycrystalline, 5-contact hole, 6-grid oxygen, 7-groove one, 8-groove two, 9-field oxygen, 10-.
Embodiment
Below in conjunction with accompanying drawing, patent of the present invention is described in detail.
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
As shown in Fig. 5, Figure 12, groove power device of the present invention includes source region and terminal two parts (taking a kind of power device MOSFET as example), wherein, active area outermost makes a circle, and groove starts until device edge, groove is located in ground floor reticle, second layer reticle is provided with LOCOS region, and second layer reticle is provided with contact hole, and the 4th layer photoetching version is provided with source electrode and grid.
Further, the described trench isolations of taking combines with LOCOS.
Further, the 4th described layer photoetching version is metal level.
The present invention also provides a kind of manufacture method of trench power device structure, and its step is as follows:
Step 1, selects suitable material use ground floor reticle to form groove, deposit or thermal process growth one deck silicon nitride;
Step 2, utilizes second layer reticle to output LOCOS region, removes the silicon nitride in LOCOS region, with chemistry or the long thermal oxide layer of physical process;
Step 3, then the not silicon nitride removal of opened areas, long grid oxygen, depositing polysilicon, polysilicon returns and is carved into raw material silicon surface, and tagma is injected and is advanced, and source region is injected and is advanced;
Step 4, deposit separator, utilizes the 3rd reticle perforate, hole etching;
Step 5, depositing metal, utilizes the 4th layer photoetching version to form source electrode and grid.
Scheme one, Fig. 5 is the single tube vertical view of MOSFET or IGBT, has a tangent plane, B-B in figure., the complete section of B-B shows as Figure 12.The forming process of selective analysis B-B below, from Fig. 6 to Figure 11, details are as follows respectively.
Fig. 6: N-type substrate, crystal orientation <100>, the oxide layer of deposit or thermal process growth 2000A-20000A is as hard mask, ground floor photoetching, form groove figure, hard mask wet method or dry etching be to substrate surface, groove dry etching, the round and smooth etching in bottom, wet method or dry method are removed hard mask completely.
Fig. 7: by the silicon nitride of deposit or thermal process growth 200A-20000A, second layer photoetching, all removing to the silicon nitride of device edge from isolated groove inner side, the oxide layer of thermal process growth 2000A-20000A.
Fig. 8: the silicon nitride that all etches away active area by wet method or dry method.
Fig. 9: the grid oxygen of the long 50A-3000A of thermal process, depositing polysilicon, polysilicon returns and is carved into and flute surfaces horizontal level.
Figure 10: tagma is injected and advanced, source region is injected and is advanced.
Figure 11: the oxide layer of deposit or thermal process growth 2000A-20000A, as separator, forms contact hole region by the 3rd layer photoetching, wet method or dry etching separator be to substrate surface, dry etching substrate 0.3um-1um.
Figure 12: evaporation or sputter 1um-5um metal level are as electrode layer, and the 4th layer photoetching version definition grid, source region, carved metal level to open by wet method or dry method.The final structure forming as shown in figure 12.
Wherein above-mentioned in the time of etching groove, utilize the load effect of etching groove, vary in size according to groove dimensions, have a mind to make peripheral etching groove to obtain more deeply, in active area, etching groove obtains more shallow, peripheral groove can better be blocked electric field like this, and active area groove forms the MOSFET elementary cell meeting the demands.Stopping groove from electric field counts outward, due to the very thick oxide layer of one deck of having grown in groove, follow-up body injects, source is injected and can not be passed, and the region that causes body, source to be injected ends at the inner side by groove, and electric field is only present in the inner side by groove thus, and can be toward extension, add P-N and be perpendicular to trenched side-wall, also just do not had the phenomenons such as electric field collects, reach the object of effective raising voltage endurance capability.From counting outward by groove, channel bottom is all grown thick oxide layer, effectively resistance to compression, and the thickness of oxide layer can be adjusted thickness according to measuring body size.In principle, this peripheral structure can be accomplished infinity voltage, and it is very little to take the area of device.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any amendment of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (5)
1. a trench power device structure, include source region and terminal two-part structure, it is characterized in that, active area outermost makes a circle, and groove starts until device edge, groove is located in ground floor reticle, second layer reticle is provided with LOCOS region, and second layer reticle is provided with contact hole, and the 4th layer photoetching version is provided with source electrode and grid.
2. trench power device structure according to claim 1, is characterized in that: take trench isolations to combine with LOCOS.
3. trench power device structure according to claim 1, is characterized in that: the 4th layer photoetching version is metal level.
4. the manufacture method of trench power device structure according to claim 1, is characterized in that: step 1, and select suitable material use ground floor reticle to form groove, deposit or thermal process growth one deck silicon nitride; Step 2, utilizes second layer reticle to output LOCOS region, removes the silicon nitride in LOCOS region, with chemistry or the long thermal oxide layer of physical process; Step 3, then the not silicon nitride removal of opened areas, long grid oxygen, depositing polysilicon, polysilicon returns and is carved into raw material silicon surface, and tagma is injected and is advanced, and source region is injected and is advanced; Step 4, deposit separator, utilizes the 3rd reticle perforate, hole etching; Step 5, depositing metal, utilizes the 4th layer photoetching version to form source electrode and grid.
5. the manufacture method of trench power device structure according to claim 4, it is characterized in that: in the time of etching groove, utilize the load effect of etching groove, vary in size according to groove dimensions, have a mind to make peripheral etching groove to obtain more deeply, in active area, etching groove obtains more shallow.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410165169.2A CN103956382A (en) | 2014-04-16 | 2014-04-16 | Groove power device structure and manufacturing method thereof |
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| CN201410165169.2A CN103956382A (en) | 2014-04-16 | 2014-04-16 | Groove power device structure and manufacturing method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6388286B1 (en) * | 1998-10-26 | 2002-05-14 | North Carolina State University | Power semiconductor devices having trench-based gate electrodes and field plates |
| US20040056302A1 (en) * | 2002-09-19 | 2004-03-25 | Grebs Thomas E. | Buried gate-field termination structure |
| US20040195620A1 (en) * | 2003-03-28 | 2004-10-07 | Mosel Vitelic, Inc. | Termination structure of DMOS device |
| CN101371343A (en) * | 2006-01-25 | 2009-02-18 | 飞兆半导体公司 | Self-aligned trench MOSFET structure and method of manufacture |
| CN102623500A (en) * | 2011-01-20 | 2012-08-01 | 飞兆半导体公司 | Trench power MOSFET with reduced on-resistance |
-
2014
- 2014-04-16 CN CN201410165169.2A patent/CN103956382A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6388286B1 (en) * | 1998-10-26 | 2002-05-14 | North Carolina State University | Power semiconductor devices having trench-based gate electrodes and field plates |
| US20040056302A1 (en) * | 2002-09-19 | 2004-03-25 | Grebs Thomas E. | Buried gate-field termination structure |
| US20040195620A1 (en) * | 2003-03-28 | 2004-10-07 | Mosel Vitelic, Inc. | Termination structure of DMOS device |
| CN101371343A (en) * | 2006-01-25 | 2009-02-18 | 飞兆半导体公司 | Self-aligned trench MOSFET structure and method of manufacture |
| CN102623500A (en) * | 2011-01-20 | 2012-08-01 | 飞兆半导体公司 | Trench power MOSFET with reduced on-resistance |
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