CN103956330A - 用于集成电路及类似物的侧堆叠互连 - Google Patents
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Abstract
在示例性实施例中,多个集成电路在区块中堆叠彼此之上。在区块的第一侧上可访问每个集成电路上的多个引线。绝缘层形成在区块的第一侧上;导电过孔形成在绝缘层中并且耦合至引线;导电层形成在绝缘层上并且耦合至导电过孔;以及导电通路形成在导电层中。绝缘层、导电过孔和导电层的额外层可以形成在第一绝缘层和第一导电层的顶部上,以便形成去往集成电路引线的更复杂的互连通路。
Description
技术领域
本公开涉及一种集成电路及类似物的堆叠。
背景技术
近些年来,对于增加电路板上计算资源的持续需求已导致集成电路的一个在另一个顶部上的堆叠。在这些情形下,通常使用垂直穿过单个集成电路的平面的硅通孔(TSV)来形成集成电路之间的连接。这些TSV的使用并非没有困难,因为集成电路上极大的区域必需专用于由TSV所占据的区域以及围绕每个TSV的避免集成电路的半导体中应力效应所需的额外区域(通常称作排除区域)。
发明内容
本发明涉及一种用于互连诸如集成电路之类的堆叠电路的改进方法和结构。
在示意性实施例中,多个集成电路在区块中一个堆叠在另一个顶部上。每个集成电路上的多个引线可在区块的第一侧上访问。绝缘层形成在区块的第一侧上;导电过孔形成在绝缘层中并且耦合至引线;导电层形成在绝缘层上并且耦合至导电过孔;以及导通通路形成在导电层中。绝缘层、导电过孔和导电层的额外层可以形成在第一绝缘层和第一导电层的顶部上以便形成至来自集成电路的引线的更复杂的互连通路。
附图说明
本领域人员将由以下详细说明明确本发明的这些目标和优点,其中:
图1A和图1B是在实践本发明中使用的集成电路的示意性实施例的顶视图和截面图;
图2是描述了本发明的示意性方法的流程图;
图3A至图3G描述了在图2的方法的各个阶段处形成的集成电路堆叠的示意性示例;以及
图4A至图4B描述了备选的堆叠配置。
应当知晓的是附图并未按照比例绘制。
具体实施方式
图1A和图1B示出了在本发明方法中使用的集成电路100的示意性实施例。应当理解,用于形成集成电路的初始材料是如下半导体衬底,即,在当今的现有技术工艺中通常是直径大至12英寸(300毫米(mm))的硅晶片。使用本领域已知的技术在半导体衬底的一个表面中形成大量相同的集成电路。关于这些技术的进一步细节描述在以下文献中:S.A.Campbell,The Science and Engineering of Microelectronic Fabrication(2 nd ed))(Oxford2001);J.D.Plummer等人,Silicon VLSI Technology Fundamentals,Practice and Modeling (Prentice Hall2000)(Prentice Hall2000);M.T.Bohr等人,The High-kSolution,IEEE Spectrum(2007年十月);E.P.Gusev等人,AdvancedHigh-k Dielectric Stacks with PolySi and Metal Gates:Recent Progressand Current Challenges,IBM J.Res&Dev..,第50卷,第4/5期(2006年七月/九月),在此引用所有这些文献全文以作参考。
通常,每个集成电路为矩形,并且在每个侧上测量尺寸小于一英寸(25mm)。结果,数百个相同的集成电路通常形成在单个半导体晶片上。集成电路通常在晶片上沿行和列对准。在形成了集成电路之后,沿着行和列划片,并且沿着划片线裂开晶片以便分隔或单独的化出单个集成电路。
在典型的集成电路中,在集成电路两个主要表面的至少一个表面上形成键合焊盘;并且集成电路通过形成至键合焊盘的连接而连接至诸如其他集成电路或印刷电路板之类的其他电路。键合焊盘继而通过形成在位于键合焊盘之间绝缘层中的导电通路以及形成在半导体衬底中的电路元件而连接至集成电路中各种电路元件。在本发明中,如下所述,通过如下的导电通路来制造去往在半导体衬底中形成的电路元件的连接,该导电通路被带出至集成电路的四个侧之一。
图1A示出了在实践本发明中使用的示意性集成电路100的顶视图。图1B示出了沿着图1A的线B-B的截面图。电路100包括半导体衬底110,以及在衬底110的一个主要表面112上的一个或多个绝缘层120。在靠近表面112的衬底110中形成诸如MOS或双极晶体管之类的各种有源电路元件,以及诸如电阻器、电容器等等的无源电路元件。导电通路130形成在绝缘层中以使得晶体管和无源元件相互耦合并且耦合至位于集成电路外部的结构。如图1A和图1B所示,一些导电通路132-135延伸至集成电路100的第一侧,侧105。
图2是描述了本发明的方法的示意性实施例的流程图。图3A至图3G描述了在图2的方法各个阶段处的集成电路堆叠。在步骤210处,诸如电路100之类的多个单独的集成电路定向、堆叠并且粘合在一起以形成集成电路堆叠300,其中在电路100上的单独的导电通路132-135延伸至堆叠的相同侧。因此,如图3A所示,堆叠300是矩形平行六面体,具有四个侧面310、320、330、340,顶面350和底面360,该矩形平行六面体具有多个相同尺寸和形状的单独的集成电路100。单个或多个的粘合层370使得每个集成电路100紧固至相邻的集成电路。示意性地,每个粘合层是具有良好自平坦化、良好粘合性、对于裂纹低易感性、以及低湿润吸收的热固聚合物。这些聚合物的示例是苯并环丁烯和SU-83000。在堆叠的顶部处,钝化层375保护在最上部的集成电路100上的导电通路。
每个集成电路100具有延伸至堆叠相同侧面的导电通路。出于示意性说明目的,对于每个集成电路而言,示出了延伸至堆叠300的面310的四个这类通路132-135。然而应当理解是,四个通路仅是示意性地,并且本发明可以由具有其他数目的通路实践,并且最可能地由具有延伸至堆叠一个侧的显著更多的通路实践。
在本发明一些实施例中,单独的集成电路可以是相同的。在其他实施例中,可以使用不同的集成电路并且甚至不同种类的电路。例如但不限于,一些电路可以是存储器电路,并且其他电路可以是逻辑电路。或者,例如但不限于,一些电路可以已经采用不同的半导体制造技术制成,或者具有不同的性能、不同的容量或不同的操作速度。一些电路可以仅包括无源元件。一些可以处理光学信号。替代地,并非所有电路都必需是集成电路。在不同电路用于相同堆叠的情形下,从这些不同电路延伸至堆叠的面的导电通路的数目可以是不同的。
在步骤220处,导电通路延伸至的面被制备用于进一步处理。这涉及到暴露导电通路的端部以及在导电通路所延伸至的堆叠的面上形成基本上光滑的工作表面。示意性地,通过化学机械抛光来形成基本上光滑的工作表面。
在步骤230处,在工作表面上形成绝缘层。图3B在堆叠已旋转90度以使得侧面310朝上之后从侧面340描绘了在导电通路132的深度处的堆叠300。集成电路100、粘合层370和导电通路132具有与如图3A所示的相同的元件。在侧面310上形成的基本上光滑的工作表面标识为元件312。示意性地为二氧化硅层或磷硅玻璃的绝缘层被标识为元件380。
在步骤240处,在绝缘层380中形成孔385。如图3C所示,孔385从绝缘层380的外侧表面延伸至工作表面312,在此它们与导电通路132-135相交。
在步骤250处,采用诸如铜之类的导电材料填充孔385,由此形成了与导电通路132-135的欧姆连接。示意性地,通过填充孔并且也覆盖绝缘层380的导电材料的均厚沉积(blanket deposition)来填充孔。随后移除沉积在绝缘层的外侧表面上的材料以便在孔中留下如图3D所示连接至导电通路132-135的隔离的导电过孔387。
在步骤260处,如图3E所示在绝缘层380的外侧表面382上以及在导电过孔387上形成导电层390。示意性地,导电层可以是金属,诸如铝、铜、或掺铜的铝。
在步骤270处,如图3F所示处理导电层390以形成连接至导电过孔387的单独的导电通路395。图3F是在堆叠300的侧面310处直接看到的视图。应当知晓,图3F中所示特定通路仅是示意性的。所执行的工艺使用了本领域已知的传统光刻技术。这些技术产生了将部分导电层390向下移除至绝缘层380的外侧表面382;以及导电层的保留的部分构成了导电通路395。
步骤230至270可以重复多次,以构建绝缘材料和导电通路的额外层。因此,可以在导电通路的顶部以及绝缘层380的暴露表面382上形成另一绝缘层。可以在绝缘层中形成孔,该孔从绝缘层的上部表面延伸至与导电通路395的交叉点。可以在绝缘层的外侧表面上形成导电层;以及可以处理导电层以形成类似于通路395的、连接至导电过孔并且最终连接至导电通路132-135的另一层导电通路。
可以重复该方法步骤,以形成最终耦合至堆叠中集成电路100上导电引线的许多层导电通路。最终,在步骤280处,在外侧表面上形成键合焊盘398以在导电通路与区块外部的结构之间提供连接;以及外侧表面具有钝化层以保护结构。图3G是类似于图3F的侧视图,但是描述了具有键合焊盘398的外侧面310。
如对于本领域技术人员明显,可以在本发明的精神和范围内实施多种变化。例如,尽管已在硅制造技术的情形中描述本发明,本发明也可以实践用于其他半导体制造技术,诸如砷化镓和其他III-V族材料系统。并未提供用于形成绝缘层、导电过孔和导电层的特定细节,因为许多这些工艺在工业领域中是已知的。例如,在Campbell和Plummer的上述教科书中描述许多这些工艺的细节,在此全文引用以作参考。尽管已经以单层形式描述了实施例,应当理解,可以由提供多个功能的多个子层来形成单层。
为了便于简化以及避免模糊本发明,仅仅已经描述了半导体制造工艺的主要步骤。也应当理解的是,因为并非必需用于理解本发明,已经省略了许多额外的步骤和细节。
尽管已经针对电路的单个堆叠描述了本发明,但是可以使用用于堆叠电路的各种设置来实践本发明。除了图3A至图3G中所示的“一维”堆叠之外,本发明也可是实施为“二维”堆叠。例如,作为在单个垂直列中设置电路的替代,可以如图4A所示在多个列410、420、430、440中设置电路,由此添加了去往堆叠结构的水平部件。在该实施例中,每个列410、420、430、440可以类似于包括多个单元400的堆叠300,其中每一个包括诸如电路100之类的衬底、衬底上的诸如层120之类的一个或多个绝缘层、诸如通路132-135之类的位于绝缘层中并且延伸至堆叠一个面的多个导电通路,以及诸如粘合层370之类的将衬底固接至堆叠中下一衬底的粘合层。作为粘合层的替代,每个堆叠中最上部单元具有类似于层375的钝化层,以保护最上部单元上的导电通路。额外的粘合层402用于将每个堆叠固接至其相邻的堆叠。
此外,作为其中每个层中的单元边缘与下一层中单元边缘对准的如图4A所示的设置的替代,相邻层中的单元可以是重叠的(或者交错的),类似于砖墙中通常重叠的砖块,由此形成了机械上更稳固的结构。图4B中示出了一种这样的备选设置。其包括结构450中的45个单元400,具有五倍电路宽和十倍电路高。图4B的单元可以类似于图4A的单元400,并且因此具有相同的元件数目。每个单元400通过粘合层452固接至相同层中的相邻单元。
单元400可以是相同的,或者如上所述,可以在一个结构中组合不同种类的电路。例如,诸如逻辑电路和存储器电路之类的不同种类集成电路可以组合在单个结构中,如图4A或图4B所示。由不同半导体制造工艺制造的电路,或者借由示例方式但是不限于此的具有不同性能、不同容量或者不同操作速度的电路可以组合在单个结构中。类似地,可以在结构410-450中包含仅仅包括无源元件的电路以及用于处理光学信号的电路。为了适应温度改变,建议由相同材料制成单元,或者由在结构的预期工作温度范围之上具有类似热膨胀系数的材料制成。
在图4A和图4B所示的结构中,每个单元具有相同的高度和宽度。然而,如同在砖墙中的构建中,可以通过恰当组合不同尺寸的单元来适应具有不同高度和/或宽度的单元。具有不同厚度的单元也可以用于图4A和图4B的结构。
仍然可以在本发明的精神和范围内实施其他变化。
Claims (27)
1.一种用于形成集成电路结构的方法,包括:
在堆叠中组装多个集成电路,所述集成电路具有延伸至所述堆叠的第一侧的导电通路;
在所述堆叠的所述第一侧上形成绝缘层;以及
在所述绝缘层中形成耦合至所述集成电路的所述导电通路的导电路径。
2.根据权利要求1所述的方法,进一步包括,在形成所述绝缘层之前平坦化所述堆叠的所述第一侧,以便暴露延伸至所述第一侧的所述导电通路。
3.根据权利要求1所述的方法,进一步包括:
在所述绝缘层中形成从所述绝缘层的外侧表面延伸至所述导电通路的孔;以及
在所述孔中形成连接至所述导电通路的导电过孔。
4.根据权利要求1所述的方法,其中,在所述绝缘层中形成导电路径的步骤包括:
形成穿过所述绝缘层延伸并且连接至所述导电通路的导电过孔;
在所述绝缘层的表面上形成连接至所述导电过孔的导电层;以及
在所述绝缘层的所述表面上的所述导电层中形成路径。
5.根据权利要求1所述的方法,其中,在所述绝缘层中形成导电路径的步骤包括:
在所述绝缘层中形成从所述绝缘层的外侧表面延伸至所述导电通路的孔;
在所述孔中形成连接至所述导电通路的导电过孔;
在所述绝缘层的表面上形成连接至所述导电过孔的导电层;以及
在所述绝缘层的所述表面上的所述导电层中形成路径。
6.根据权利要求1所述的方法,进一步包括粘合所述集成电路以形成所述堆叠的步骤。
7.一种用于形成半导体器件的方法,包括:
在堆叠中组装多个集成电路,每个所述集成电路包括半导体衬底、以及由在所述衬底上形成的至少第一绝缘区域所分开的多个第一导电通路;
在所述堆叠的第一侧上形成第二绝缘区域;以及
在所述第二绝缘区域中形成耦合至所述第一导电通路的第二导电通路。
8.根据权利要求7所述的方法,进一步包括,在形成所述第二绝缘区域之前平坦化所述堆叠的所述第一侧,以便暴露所述第一导电通路。
9.根据权利要求7所述的方法,进一步包括:
在所述第二绝缘区域中形成从所述第二绝缘区域的外侧表面延伸至所述第一导电通路的孔;以及
在所述孔中形成连接至所述第一导电通路的导电过孔。
10.根据权利要求7所述的方法,其中,在所述第二绝缘区域中形成第二导电通路的步骤包括:
形成穿过所述第二绝缘区域延伸并且连接至所述第一导电通路的导电过孔;
在所述第二绝缘区域的表面上形成连接至所述导电过孔的导电层;以及
在所述第二绝缘区域的所述表面上的所述导电层中限定路径。
11.根据权利要求7所述的方法,其中,在所述绝缘层中形成第二导电通路的步骤包括:
在所述第二绝缘区域中形成从所述第二绝缘区域的外侧表面延伸至所述第一导电通路的孔;
在所述孔中形成连接至所述第一导电通路的导电过孔;
在所述第二绝缘区域的表面上形成连接至所述导电过孔的导电层;以及
在所述第二绝缘区域的所述表面上的所述导电层中形成路径。
12.根据权利要求7所述的方法,进一步包括粘合所述集成电路以形成所述堆叠的步骤。
13.根据权利要求7所述的方法,进一步包括步骤:
在所述第二绝缘区域上形成第三绝缘区域;以及
在所述第三绝缘区域中形成耦合至所述第二导电通路的第三导电通路。
14.一种半导体器件,包括:
多个集成电路,堆叠在彼此之上以形成堆叠;
每个所述集成电路包括半导体衬底、以及由在所述衬底上形成的至少第一绝缘区域分开的多个第一导电通路;
第二绝缘区域,在所述堆叠的第一侧上,以及
多个第二导电通路,在所述第二绝缘区域中形成并且耦合至所述多个第一导电通路。
15.根据权利要求14所述的半导体器件,进一步包括在所述集成电路之间的粘合层。
16.根据权利要求14所述的半导体器件,其中,所述第二导电通路在所述第二绝缘层上的金属化层中形成。
17.根据权利要求14所述的半导体器件,其中,所述第二导电通路包括:
导电过孔,穿过所述第二绝缘层延伸并且连接至所述第一导电通路;以及
路径,限定在所述第二绝缘层的表面上的导电层中并且连接至所述导电过孔。
18.根据权利要求14所述的半导体器件,进一步包括:
第三绝缘区域,在所述第二绝缘层上,以及
多个第三导电通路,在所述第三绝缘区域中形成并且耦合至所述多个第二导电通路。
19.根据权利要求14所述的半导体器件,其中,所述多个第一导电通路延伸至所述堆叠的所述第一侧。
20.一种半导体器件,包括:
多个电路,每个电路具有在其第一表面上的第一导电通路,所述电路按二维相互堆叠以形成具有至少两个层的区块,其中至少两个电路在每个层中,至少多个所述电路是集成电路;
绝缘层,在所述区块的第一侧上;以及
第二导电通路,穿过所述绝缘层延伸并且耦合至所述第一导电通路。
21.根据权利要求20所述的器件,进一步包括在所述电路之间的粘合层。
22.根据权利要求20所述的器件,其中,所述第二导电通路形成在所述绝缘层上的金属化层中。
23.根据权利要求20所述的器件,其中,所述第二导电通路包括:
导电过孔,穿过所述绝缘层延伸并且连接至所述第一导电通路;以及
路径,限定在所述绝缘层的表面上的导电层中并且连接至所述导电过孔。
24.根据权利要求20所述的器件,其中,所述多个第一导电通路延伸至所述第一侧。
25.根据权利要求20所述的器件,其中,设置所述电路的层以使得所述电路的边缘相互对准。
26.根据权利要求20所述的器件,其中,设置所述电路的层以使得相邻层中电路的边缘相互不对准。
27.根据权利要求20所述的器件,其中,所述区块中每个所述电路是集成电路。
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US5567654A (en) * | 1994-09-28 | 1996-10-22 | International Business Machines Corporation | Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging |
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