CN103943481B - Method for avoiding negative bias temperature instability of device - Google Patents

Method for avoiding negative bias temperature instability of device Download PDF

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Publication number
CN103943481B
CN103943481B CN201410162847.XA CN201410162847A CN103943481B CN 103943481 B CN103943481 B CN 103943481B CN 201410162847 A CN201410162847 A CN 201410162847A CN 103943481 B CN103943481 B CN 103943481B
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Prior art keywords
negative bias
temperature instability
bias temperature
device negative
chlorine
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CN201410162847.XA
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CN103943481A (en
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朱双龙
胡鹏超
刘景富
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation

Abstract

The invention provides a method for avoiding negative bias temperature instability of a device. The method includes the steps that a wet method deposition process is utilized to replace a dry method deposition process to deposit a grid electrode oxidation layer; after the grid electrode oxidation layer is deposited, oxidizing gas is fed into an oxidation process cavity in which the device to be processed is placed through a high-temperature heat oxidation process so that a grid electrode isolation film can grow. When the grid electrode isolation film grows through the high-temperature heat oxidation process, dichlorosilane is mixed into the oxidizing gas, and then the high-temperature heat oxidation process of the grid electrode isolation film can be finished.

Description

The method for improving device Negative Bias Temperature Instability
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to one kind by improve furnace process come The method for improving device Negative Bias Temperature Instability.
Background technology
When PMOS device works, when grid is under back bias voltage, after applying certain hour, the threshold value of device is electric Pressure absolute value constantly increases, and drain current and mutual conductance constantly reduce, and this effect can be more significantly with the increase of bias.
In existing processing procedure, grid oxic horizon (oxide of Gate 1) deposits the work of (Wet deposition) using wet method Skill, can introduce H-shaped into H+ in technical process, be drifted about to grid direction in the presence of gate electric field, and some can be oxidized break Sunken capture forms positive oxide trapped charge, and this Partial charge can cause the drift of threshold voltage, and grid-control ability to die down, in phase With under grid voltage and under drain voltage, inversion layer degree reduction, saturation current reduces, and device drive energy declines；Another portion Divide H+ also to be acted on the Si -- H bond continuation at interface and cause that Si-H is decomposed and formed H2, leave the interface trap i.e. suspension of trivalent silicon Key, and the generation of interface trap will cause the increase of surface scattering rate, so as to influence carrier mobility, mutual conductance etc..Thus, make The Negative Bias Temperature Instability NBTI (Negativebiastemperature instability) for obtaining device is affected.
The content of the invention
The technical problems to be solved by the invention are directed to and there is drawbacks described above in the prior art, there is provided one kind can pass through The method for improving furnace process to improve device Negative Bias Temperature Instability.
In order to realize above-mentioned technical purpose, according to the present invention, there is provided one kind improves device Negative Bias Temperature Instability Method, wherein substituting wet deposition process using dry method depositing operation deposits grid oxic horizon；And in deposition grid oxygen Change after layer, be passed through oxidizing gas in the oxidation technology chamber that placed pending device to grow using high-temperature thermal oxidation technique Gate isolation film.
Preferably, during using high-temperature thermal oxidation technique growth gate isolation film, mixed in oxidizing gas Dichlorosilane is completing the high-temperature thermal oxidation technique of gate isolation film.
Preferably, the method for improving device Negative Bias Temperature Instability is used to manufacture PMOS.
Preferably, the method for improving device Negative Bias Temperature Instability is used to manufacture NMOS.
Preferably, the method for improving device Negative Bias Temperature Instability is used to manufacture CMOS.
Therefore, the combination by using dry method depositing operation and high-temperature thermal oxidation technique of the invention is with changes and improvements boiler tube Technique, the generation of H+ in technical process is thus reduced, so as to reduce the boundary at the interface between gate oxide and substrate Face trap (Si dangling bonds), finally reduces the drift of threshold voltage, improves the Negative Bias Temperature Instability NBTI of device.
Brief description of the drawings
With reference to accompanying drawing, and by reference to following detailed description, it will more easily have more complete understanding to the present invention And its adjoint advantages and features is more easily understood, wherein：
Fig. 1 schematically shows the side of improvement device Negative Bias Temperature Instability according to the preferred embodiment of the invention Method.
It should be noted that accompanying drawing is used to illustrate the present invention, it is not intended to limit the present invention.Note, represent that the accompanying drawing of structure can Can be not necessarily drawn to scale.Also, in accompanying drawing, same or similar element indicates same or similar label.
Specific embodiment
In order that present disclosure is more clear and understandable, with reference to specific embodiments and the drawings to of the invention interior Appearance is described in detail.
In the fail-safe analysis of semiconductor devices, Negative Bias Temperature Instability NBTI (Negative bias Temperature instability) be it is very important consider parameter, the negative temperature bias for being directed to boost device are unstable Property NBTI, the present invention in grid oxic horizon depositing operation using dry method deposit (Dry oxidation) substitute wet method deposit, and The growth of gate spacer is carried out using the HTO (thermal oxide) for mixing chlorine, so as to reduce the generation of H+, positive oxide layer is reduced and is fallen into The quantity of trap electric charge, improves the Negative Bias Temperature Instability NBTI of device.
Specifically, deposited by the way that the wet method deposition of grid oxic horizon depositing operation in existing processing procedure is changed over into dry method, Steam or H can be reduced2Entrance, reduce the quantity of Si-H and H+, it is to avoid produce interface trap (Si after Si-H fractures Dangling bonds) and the positive oxide trapped charge that produces after H+ is captured, so that the Negative Bias Temperature Instability of boost device NBTI；In addition, using the mode growing film of HTO (high-temperature thermal oxidation) in the growth of gate spacer, exist under high temperature simultaneously Dichlorosilane (SiH is mixed in oxidizing gas2Cl2), the introducing of chlorine improves the speed of oxidation and the quality of oxide layer, in Si and SiO2Interface C l and Si combine generation chlorine silicide, in the case where high temperature is aerobic, chlorine silicide is easily oxidized to SiO2, chlorine Equivalent to the catalyst in oxidizing process, and the hydrogen ion produced after Si-H fractures can be combined, reduce interface trap (Si Dangling bonds) while decrease the number of H+, largely improve the Negative Bias Temperature Instability NBTI of device；Separately Outward, some metallic elements that may be present that chlorine can also be in combination film, improve the quality of film.
Therefore, the present invention is by using the combination changes and improvements boiler tube of dry method depositing operation and high-temperature thermal oxidation technique Technique reduces the generation of H+ in technical process, so as to reduce the interface trap at the interface between gate oxide and substrate (Si dangling bonds), finally reduce the drift of threshold voltage, improve the Negative Bias Temperature Instability NBTI of device.
Specifically, Fig. 1 schematically shows improvement device negative temperature bias shakiness according to the preferred embodiment of the invention Qualitatively method.
As shown in figure 1, in the method for improvement device Negative Bias Temperature Instability according to the preferred embodiment of the invention, Wet deposition process is substituted using dry method depositing operation to deposit grid oxic horizon；And after grid oxic horizon is deposited, profit Oxidizing gas is passed through in the oxidation technology chamber that placed pending device with high-temperature thermal oxidation technique thin to grow gate isolation Film.
Preferably, during using high-temperature thermal oxidation technique growth gate isolation film, mixed in oxidizing gas Dichlorosilane is completing the high-temperature thermal oxidation technique of gate isolation film.
The above method can be used to manufacture PMOS, NMOS or CMOS etc..
It should be noted that unless stated otherwise or pointing out, term " first ", " second ", " otherwise in specification The description such as three " is used only for distinguishing each component, element, step in specification etc., without being intended to indicate that each component, unit Logical relation or ordinal relation between element, step etc..
Although it is understood that the present invention is disclosed as above with preferred embodiment, but above-described embodiment and being not used to Limit the present invention.For any those of ordinary skill in the art, in the case where technical solution of the present invention ambit is not departed from, Many possible variations and modification are all made to technical solution of the present invention using the technology contents of the disclosure above, or is revised as With the Equivalent embodiments of change.Therefore, every content without departing from technical solution of the present invention, according to technical spirit pair of the invention Any simple modification, equivalent variation and modification made for any of the above embodiments, still fall within the scope of technical solution of the present invention protection It is interior.

Claims (4)

1. a kind of method for improving device Negative Bias Temperature Instability, wherein substituting wet method deposition work using dry method depositing operation Skill deposits grid oxic horizon；And deposit grid oxic horizon after, using high-temperature thermal oxidation technique placed it is pending Oxidizing gas is passed through to grow gate isolation film in the oxidation technology chamber of device, wherein mixing dichloro silicon in oxidizing gas Alkane, the introducing of chlorine improves the speed of oxidation and the quality of oxide layer, in Si and SiO2Interface C l and Si combine generation chlorine silicon Compound, chlorine silicide is easily oxidized to SiO2, chlorine equivalent to the catalyst in oxidizing process, and can combine Si-H fracture after produce Raw hydrogen ion, decreases hydrionic number while interface trap is reduced.
2. it is according to claim 1 improve device Negative Bias Temperature Instability method, it is characterised in that the improvement The method of device Negative Bias Temperature Instability is used to manufacture PMOS.
3. it is according to claim 1 improve device Negative Bias Temperature Instability method, it is characterised in that the improvement The method of device Negative Bias Temperature Instability is used to manufacture NMOS.
4. it is according to claim 1 improve device Negative Bias Temperature Instability method, it is characterised in that the improvement The method of device Negative Bias Temperature Instability is used to manufacture CMOS.
CN201410162847.XA 2014-04-22 2014-04-22 Method for avoiding negative bias temperature instability of device Active CN103943481B (en)

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CN110867376A (en) * 2019-11-25 2020-03-06 上海华力集成电路制造有限公司 Method and structure for improving NBTI of semiconductor strain device
CN112582272A (en) * 2020-12-11 2021-03-30 长江存储科技有限责任公司 Semiconductor device and method for manufacturing the same
CN114999907B (en) * 2022-08-08 2023-03-17 合肥新晶集成电路有限公司 Manufacturing method of grid oxide layer and manufacturing method of field effect transistor

Citations (5)

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CN1855376A (en) * 2005-04-18 2006-11-01 力晶半导体股份有限公司 Formation of slotted grid dielectric layer
CN1967780A (en) * 2005-10-20 2007-05-23 应用材料公司 Method for fabricating a gate dielectric of a field effect transistor
CN101320691A (en) * 2007-06-05 2008-12-10 联华电子股份有限公司 Method for fabricating MOS transistor
CN103094325A (en) * 2011-11-02 2013-05-08 中芯国际集成电路制造(北京)有限公司 Semiconductor device and manufacturing method thereof
CN103390559A (en) * 2012-05-09 2013-11-13 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device

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US20050202659A1 (en) * 2004-03-12 2005-09-15 Infineon Technologies North America Corp. Ion implantation of high-k materials in semiconductor devices

Patent Citations (5)

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Publication number Priority date Publication date Assignee Title
CN1855376A (en) * 2005-04-18 2006-11-01 力晶半导体股份有限公司 Formation of slotted grid dielectric layer
CN1967780A (en) * 2005-10-20 2007-05-23 应用材料公司 Method for fabricating a gate dielectric of a field effect transistor
CN101320691A (en) * 2007-06-05 2008-12-10 联华电子股份有限公司 Method for fabricating MOS transistor
CN103094325A (en) * 2011-11-02 2013-05-08 中芯国际集成电路制造(北京)有限公司 Semiconductor device and manufacturing method thereof
CN103390559A (en) * 2012-05-09 2013-11-13 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device

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