CN101320691A - Method for fabricating MOS transistor - Google Patents
Method for fabricating MOS transistor Download PDFInfo
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- CN101320691A CN101320691A CNA2007101088787A CN200710108878A CN101320691A CN 101320691 A CN101320691 A CN 101320691A CN A2007101088787 A CNA2007101088787 A CN A2007101088787A CN 200710108878 A CN200710108878 A CN 200710108878A CN 101320691 A CN101320691 A CN 101320691A
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Abstract
The invention discloses a method of manufacturing a strained silicon PMOS or a CMOS transistor; wherein, silane with at least substituent selected from a group composed of alkyl, hydroxyl, carbonyl, aldehyde group, carboxyl and halogen reacts with ammonia to form a compression stress film, or a known compression stress film is injected into fluorine atom, oxygen atom or carbon atom so as to improve instability of bias-temperature.
Description
Technical field
The present invention relates to a kind of manufacture method of metal oxide semiconductor transistor, especially finger is a kind of can reduce Negative Bias Temperature Instability (negative bias temperature instability, the manufacture method of strain silicon metal oxide semiconductor transistor NBTI).
Background technology
Along with semiconductor technology enters deep-submicron (for example 45 nanometers and the following) epoch, (metal-oxide-semiconductor, MOS) transistorized drive current (drive current) becomes a heat subject gradually to utilize high stress films to promote metal-oxide semiconductor (MOS) in semiconductor technology.The drive current that utilizes high stress films to promote metal oxide semiconductor transistor at present can generally be divided into two aspects: it is applied in the polysilicon stressor layers (poly stressor) before metal silicide such as nickel silicon forms on the one hand; Then be applied on the other hand contact etch stop layer after metal silicides such as nickel silicon form (contact etch stop layer, CESL).
On the technology of contact etch stop layer (CESL), owing to need be impatient at the cause of higher thermal effect during consideration formation nickel silicon, so must limit technological temperature less than 430 ℃.So in known technology, when making the high stress films of contact etch stop layer (CESL), generally can deposit the film of being formed by silicon nitride (SiN) earlier, and then promote the drive current of metal oxide semiconductor transistor by this film.
Please refer to Fig. 1 and Fig. 2, Fig. 1 and Fig. 2 are that known manufacturing high compression stress film is in P-type mos (P-type metal-oxide semiconductor, PMOS) the method schematic diagram on transistor surface.As shown in Figure 1, at first provide the semiconductor-based end 10, silicon base for example, and include grid structure 12 at the semiconductor-based end 10.Wherein, grid structure 12 includes grid oxic horizon (gate oxide) 14, is positioned at grid 16 on the grid oxic horizon 14, is positioned at the cover layer (cap layer) 18 and the clearance wall (spacer) 20 of grid 16 top surfaces.Generally speaking, grid oxic horizon 14 is by silicon dioxide (silicon dioxide, SiO
2) constitute, grid 16 is made of doped polycrystalline silicon (doped polysilicon), cover layer 18 then is made up of silicon nitride layer, in order to the protection grid 16.In addition, be surrounded with shallow trench isolation in addition from (STI) 22 at the semiconductor-based end 10 of the active region at grid structure 12 places (active area) periphery.Carry out ion subsequently and inject (ion implantation) technology, in the semiconductor-based end 10 around the clearance wall 20, to form regions and source 26.Then at the semiconductor-based end 10 and grid structure 12 surperficial jet-plating metallization layers (figure does not show), for example nickel metal layer.Being rapidly heated then, (rapid thermal annealing, RTA) technology make metal level become metal silicide layer with the partial reaction that grid 16 and regions and source 26 contact in annealing.Remove the unreacted metal layer at last again.
Then, as shown in Figure 2, in reative cell (chamber), feed silicomethane (silane, SiH
4) and ammonia (ammonia, NH
3), and carry out plasma enhanced chemical vapor deposition (plasma enhancedchemical vapor deposition, PECVD) technology is to form high compression stress film (highcompressive stress film) 28 (also as CESL) to be covered in grid structure 12 and regions and source 26 surfaces.Compress grid 16 belows by high compression stress film 28, that is the lattice arrangement at the semiconductor-based end 10 of channel region (channelregion), and then the hole mobility and the transistorized drive current of strained silicon (strained-silicon) PMOS (drive current) of lifting channel region.
Yet as in the above-mentioned known technology, serious NBTI deterioration when making SiN compression stress film with the PECVD method, easily takes place based on the material of silicomethane in use.As shown in Figure 3, to have compression stress be respectively-0.2 ,-2.4, and-the semiconductor chip sample lot number 1,2 of the SiN compression stress film of 2.7GPa, and 3 apply a coercive voltage (stress voltage) with a Measuring Time, measure starting voltage (threshold voltage) changing value of the MOS transistor on this semiconductor chip then.When the stress of the stress Da Yue-0.2Gpa of SiN compression stress film is above, the starting voltage changing value greater than 80mV is promptly arranged, show the deterioration of NBTI.
Therefore, still need the manufacture method of a kind of PMOS of novelty, have the strained silicon PMOS of the NBTI performance of improvement with manufacturing.
Summary of the invention
A purpose of the present invention provides the transistorized method of a kind of manufacturing PMOS, and provide a kind of technology relevant manufacturing CMOS (Complementary Metal Oxide Semiconductor) (complementary metal-oxidesemiconductor, CMOS) transistorized method, the strained silicon PMOS and the CMOS transistor that have the NBTI performance of improvement with manufacturing.
In an aspect of the present invention,, comprise the following steps according to the transistorized method of manufacturing PMOS of the present invention.At first, provide the semiconductor-based end.Form grid structure and source/drain on the semiconductor-based end.Then, provide to have at least one substituent silane (hereinafter being sometimes referred to as " silane that is substituted (substituted silane) "), this substituting group is selected from alkyl (hydrocarbyl), oxyl, carbonyl, aldehyde radical, carboxyl, ester group, reaches a kind of of group that halogen is formed.Ammonia is provided.Make this silane that is substituted and ammonia gas react, to form the compression stress film to be covered in grid structure and regions and source surface.
In another aspect of the present invention,, comprise the following steps according to the transistorized method of manufacturing PMOS of the present invention.At first, provide the semiconductor-based end.Form grid structure, reach regions and source on the semiconductor-based end.Then, form the compression stress film to be covered in grid structure and regions and source surface.At last, inject fluorine (F) atom, oxygen (O) atom or carbon (C) atom at the compression stress film.
In another aspect of the present invention,, comprise the following steps according to the transistorized method of manufacturing CMOS of the present invention.At first, provide the semiconductor-based end, the semiconductor-based end, comprise N type active region and P type active region.Form tensile stress film to cover N type active region.Secondly, provide have at least onely be selected from alkyl, oxyl (hydrocarboxy), carbonyl (carbonyl), aldehyde radical (formyl), carboxyl (carboxylicgroup), ester group (ester group), and halogen (halo group) institute composition group is a kind of as substituent silane.Ammonia is provided.Make this silane that is substituted and ammonia gas react, to form the compression stress film to cover the semiconductor-based end, tensile stress film, to reach P type active region.Then, form mask is positioned at P type active region with covering compression stress film.Remove the compression stress membrane portions of not masked covering.At last, remove mask, and make the CMOS transistor.
In another aspect of the present invention,, comprise the following steps according to the transistorized method of manufacturing CMOS of the present invention.At first, provide the semiconductor-based end, it comprises N type active region and P type active region.Secondly, form tensile stress film to cover N type active region.Form the compression stress film to cover the semiconductor-based end, tensile stress film, to reach P type active region.Then, inject fluorine atom, oxygen atom or carbon atom at the compression stress film.Then, form mask is positioned at P type active region with covering compression stress film.Remove the compression stress membrane portions of not masked covering.At last, remove mask, and make the CMOS transistor.
In another aspect of the present invention, the method according to manufacturing CMOS of the present invention comprises the following steps.At first, provide the semiconductor-based end, it comprises N type active region and P type active region.Secondly, provide silane, silane have at least onely be selected from alkyl, oxyl, carbonyl, aldehyde radical, carboxyl, ester group, and cohort that halogen is formed is a kind of as substituting group.Ammonia is provided.Make this silane that is substituted and ammonia gas react, to form the compression stress film to cover the semiconductor-based end, N type active region, to reach P type active region.Then, form mask is positioned at P type active region with covering compression stress film.Then, remove the compression stress membrane portions of not masked covering.Remove mask.At last, form tensile stress film, make the CMOS transistor to cover N type active region.
In another aspect of the present invention,, comprise the following steps according to the transistorized method of manufacturing CMOS of the present invention.At first, provide the semiconductor-based end, it comprises N type active region and P type active region.Secondly, form the compression stress film to cover N type active region, P type active region, to reach the semiconductor-based end.Then, inject fluorine atom, oxygen atom or carbon atom at the compression stress film.Then, form mask is positioned at P type active region with covering compression stress film.Remove the compression stress membrane portions of not masked covering.Then, remove mask.At last, form tensile stress film, make the CMOS transistor to cover N type active region.
Description of drawings
Fig. 1 to Fig. 2 is that known manufacturing high compression stress film is in the method schematic diagram on PMOS transistor surface.
Fig. 3 be on the transistor compression stress to the mapping of starting voltage (threshold voltage) changing value.
The schematic diagram of Fig. 4 to 6 for having the transistorized method of PMOS of high compression stress film according to manufacturing of the present invention.
Fig. 7 shows its NBTI performance of device comparison that the device with high compression stress film (SiN film) that will make according to method of the present invention and known method make.
Fig. 8 is Fourier transform infrared spectroscopy (Fourier TransformInfrared Spectroscopy, the FTIR) schematic diagram of high compression stress film of the present invention.
Fig. 9 shows the specific embodiment of another aspect of the present invention.
Figure 10 to 15 has the method schematic diagram of the CMOS of dual contact etch stop layer (dualCESL) for further embodiment of this invention manufacturing.
Figure 16 shows the specific embodiment of another aspect of the present invention.
Description of reference numerals
10 grid structures of the semiconductor-based ends 12
14 grid oxic horizons, 16 grids
18 cover layers, 20 clearance walls
22 shallow trench isolations are from 26 regions and source
The 60 semiconductor-based ends of 28 high compression stress films
62 shallow trench isolations are from 63 grid structures
64 gate dielectrics, 66 grids
68 cover layers, 70 clearance walls
74 regions and source, 76 high compression stress films
80 grid structures of the semiconductor-based ends 82
84 compression stress films, 86 gate dielectrics
88 grids, 90 layings
92 cover layers, 94 light doping sections
The 100 semiconductor-based ends of 96 heavily doped regions
102NMOS transistor area 104PMOS transistor area
106 shallow trench isolations are from the 108NMOS grid
114 gate dielectrics, 115 metal silicide layers
116 regions and source, 117 regions and source
118 lightly doped drains, 119 lightly doped drains
120 high tensile stress film 122 patterning photoresist layers
124 high compression stress films, 125 high compression stress films
126 patterning photoresist layers
Embodiment
Please refer to Fig. 4 to 6, Fig. 4 to 6 has the schematic diagram of the transistorized method of PMOS of high compression stress film for manufacturing of the present invention.As shown in Figure 4, at first provide the semiconductor-based end 60, for example silicon wafer (silicon wafer) or silicon-coated insulated (SOI) substrate, and include grid structure 63 at the semiconductor-based end 60.Grid structure generally can comprise grid, and can further comprise for example gate dielectric, cover layer, self-aligned metal silicate layer (being called salicide again), laying or clearance wall.As shown in Figure 4, grid structure 63 includes grid 66, and further comprises at grid 66 and the gate dielectric at the semiconductor-based end 60 64, the cover layer 68 that is positioned at grid 66 top surfaces and clearance wall 70.Generally speaking, gate dielectric 64 can be megohmite insulants such as formed silica such as the technology of utilizing thermal oxidation or deposition or nitrogen silicon compound and constitutes, and cover layer 68 then can be by being formed in order to the silicon nitride layer of protection grid 66.In addition, the active region (AA) at grid structure 63 places at peripheral the semiconductor-based end 60 also around shallow trench isolation from (STI) 62, be used for making these other elements of PMOS transistor AND gate isolated.
As shown in Figure 5, then carry out ion and inject (ion implantation) technology, in the semiconductor-based end 60 around the grid structure 63, to form regions and source 74.Annealing (rapid thermal annealing) technology then is rapidly heated, utilize 900 to 1050 ℃ high temperature to activate impurity in the regions and source 74, and repair the lattice structure on surface, the semiconductor-based ends 60 impaired in each ion implantation technology simultaneously.In addition, also visual product demand and functional consideration, between regions and source 74 and grid structure 63, form lightly doped drain (LDD) or source/drain in addition respectively and extend (source/drain extension), perhaps form again and aim at metal silicide (salicide) voluntarily on regions and source 74 and grid structure 63 surfaces, this is all known related art techniques person and knows that the knowledgeable knows usually, does not add to give unnecessary details at this.
Then as shown in Figure 6, carry out pecvd process, to form high compression stress film 76 on grid structure 63 and regions and source 74 surfaces.In a preferred embodiment of the invention, this PECVD earlier places cvd reactive chamber with the semiconductor-based end 60, then feed have at least one be selected from alkyl, oxyl, carbonyl, aldehyde radical, carboxyl, ester group, and a kind of of group that halogen is formed be that substituent silane is as predecessor (precursor).Feed ammonia subsequently again, make this silane that is substituted and ammonia gas react, carry out plasma enhanced chemical vapor deposition, to form high compression stress film 76 on grid structure 63 and regions and source 74 surfaces.Wherein, the flow of predecessor can be between per minute 30 to 3000 grams, and the flow of ammonia can (standard cubic centimeter per minute be sccm) between the 20000sccm between per minute 30 standard cubic centimeters.In addition, form the power of the high and low frequency radio wave of high compression stress film 76 can be respectively between 50 watts (watts) to 3000 watts.
The employed in the present invention silane that is substituted can have one or more silicon atom, for example is single silane, disilane, three silane, tetrasilane, and five silane etc., and has at least one or more a plurality of substituting group.Substituting group can be and independently is selected from alkyl, oxyl, carbonyl, aldehyde radical, carboxyl, ester group, and the group formed of halogen is a kind of.Wherein, alkyl can be exemplified as alkyl, thiazolinyl or alkynyl.Oxyl can-OR represents that R can be exemplified as alkyl, thiazolinyl or alkynyl.Carbonyl can-COR represents that R can be exemplified as alkyl, thiazolinyl or alkynyl.Aldehyde radical is-CHO.Carboxyl is-COOH.Ester group can-COOR represents that R can be exemplified as alkyl, thiazolinyl or alkynyl.Halogen can be exemplified as fluorine (F), chlorine (Cl), bromine (Br) or iodine (I).The preferred employed silane that is substituted can be gas under compression stress membrane process condition, for example can be gaseous state in low pressure or under heating, and can utilize among convenient the present invention.
Use has above-mentioned substituent silane and makes the high compression stress film as predecessor with methods such as PECVD, as for example impurity such as oxygen atom, fluorine atom, carbon atom that mix in original position (in-situ) in the high compression stress film, so can seize the H+ ion that obtains in (trap) film, the NBTI performance of the PMOS that is greatly improved.The method that forms the high compression stress film still can have Low Pressure Chemical Vapor Deposition (LPCVD) and high density plasma CVD method (HDP CVD) for example except PECVD.
Table 1 show to use high compression stress film (SiN film) device performance that tetramethylsilane (tetramethylsilane abbreviates 4MS herein sometimes as) makes as predecessor and uses silicomethane to be master (SiH
4-predecessor based) makes the comparison of high compression stress film (SiN film) device performance.Use tetramethylsilane, can make the high compression stress film of pact-3.6GPa, the silane that use is unsubstituted then makes-device of the high compression stress film (SiN film) of 3.0GPa as predecessor, and the two all can obtain about 53% PMOS ion gain (ion gain).
Table 1
The device that will use tetramethylsilane to make high compression stress film (SiN film) compares its NBTI performance with using silane for the main device that makes high compression stress film (SiN film), as shown in Figure 7, use tetramethylsilane to make the device of high compression stress film (SiN film), the stress of its high compression stress film is-2.75GPa, record greater than 10 years the useful life of device, shows good NBTI performance.And using silane to be the main device that makes high compression stress film (SiN film), the stress of its high compression stress film is pact-0.65GPa, about 5 years of the useful life of device, its NBTI poor-performing as can be known.
See also Fig. 8, Fig. 8 is Fourier transform infrared spectroscopy (Fourier Transform Infrared Spectroscopy, the FTIR) schematic diagram of high compression stress film of the present invention.As shown in Figure 8, by using tetramethylsilane as predecessor and ammonia gas react, the high compression stress film 76 that produces in plasma enhanced chemical vapor deposition technology has Si-CH
3Bond shows because of producing by original position (in-situ) doping C impurity when the manufacturing SiN film, can help to seize to obtain the H+ ion.Therefore the NBTI character of PMOS improve, and also can obtain the high compression stress film simultaneously.
Make high compression stress film impurity to seize the method that obtains the H+ ion, except above-mentioned use precursor is in-situ doped, still the mode that can use dystopy (ex-situ) to mix, F, O or C atom are injected the high compression stress film that (implantation) made, will be present in the H+ ion trap in the film.The ability of F, O or C atom seizure H+ ion can be decided according to its electronegative, generally is F＞O＞C.Therefore, see also Fig. 9, it shows the specific embodiment of another aspect of the present invention.According to the transistorized method of manufacturing PMOS of the present invention, can comprise the following steps.At first, provide the semiconductor-based end 80.Then, form grid structure 82.Grid structure generally can comprise grid, and can further comprise for example gate dielectric, cover layer, self-aligned metal silicate layer, laying or clearance wall.As shown in Figure 9, grid structure 82 comprises grid 88, gate dielectric 86, laying 90, reaches cover layer 92.And forming regions and source on the semiconductor-based end, regions and source can comprise further that light doping section 94 is as LDD and heavily doped region 96.Regions and source also can further form with the grid structure surface and aim at metal silicide voluntarily.Then, form compression stress film 84 to be covered in grid structure 82 and regions and source surface.The formation of compression stress film 84 can be by for example known feeding silicomethane and ammonia, and carries out pecvd process and reach.At last, carry out implantation step, inject fluorine atom, oxygen atom or carbon atom in compression stress film 84, its amount in the film of flowing into for example can be 10
12Atom/cm
2To 10
17Atom/cm
2, be preferably 10
14Atom/cm
2To 10
16Atom/cm
2The method of injecting can be used for example high current injection method (high current injection, HI), middle current injection method (medium currentinjection, MI), the high energy injection method (high energy injection, HEI) or its fellow carry out.The chemicals (fluorine-, oxygen-, or carbon-containing chemicals) that the source of F, O or C atom can be is for example fluorine-containing, contain oxygen or carbon containing.
See also Figure 10 to Figure 15, Figure 10 to Figure 15 has the method schematic diagram of the CMOS of dual contact etch stop layer (dual CESL) for another embodiment of the present invention manufacturing.As shown in figure 10, at first provide one to separate out the semiconductor-based end 100 of nmos pass transistor district 102 and PMOS transistor area 104 from (STI) 106, and respectively have NMOS grid 108, PMOS grid 110 on each nmos pass transistor district 102 and the PMOS transistor area 104 and be arranged at each grid and the gate dielectric at the semiconductor-based end 100 114 with shallow trench isolation.Then at the sidewall surfaces out of the ordinary laying 112 that form by silica layer and silicon nitride layer constituted of NMOS grid 108 with PMOS grid 110.
Carry out ion implantation technology then, following NMOS grid 108 respectively forms regions and source 116 and 117 with PMOS grid 110 at the semiconductor-based end 100 on every side.And then the annealing process that is rapidly heated utilizes 900 to 1050 ℃ high temperature to activate impurities in regions and source 116 and 117, and repairs the lattice structure on surface, the semiconductor-based ends 100 impaired in each ion implantation technology simultaneously.In addition, also visual product demand and functional consideration form lightly doped drain (LDD) 118 and 119 respectively in addition between regions and source 116,117 and each grid 108,110.
Then at the surperficial jet-plating metallization layer in the semiconductor-based ends 100 (figure does not show), nickel metal layer for example, annealing (RTA) technology then is rapidly heated, make metal level become metal silicide layer 115, finish and aim at metal silicide technology (salicide) voluntarily with the partial reaction that NMOS grid 108, PMOS grid 110 and regions and source 116 contact with 117.
After removing the unreacted metal layer, then carry out pecvd process, form high tensile stress film (high tensile stress film) 120 with 115 surfaces of the metal silicide layer in nmos pass transistor district 102 and PMOS transistor area 104.
Then as shown in figure 11, carry out photoresist coating, exposure and developing process, to form patterning photoresist floor 122 and to cover whole nmos pass transistor district 102.Then carry out etch process as mask with patterning photoresist layer 122, remove and be not patterned the zone that photoresist layer 122 covers, that is be covered in high tensile stress film 120 on the PMOS transistor area 104, so that only stay high tensile stress film 120 in NMOS grid 108 and regions and source 116 surfaces.
As shown in figure 12, then remove the patterning photoresist floor 122 that is covered in the nmos pass transistor district 102.Then, as shown in figure 13, in the reative cell (not shown), carry out pecvd process: feed have at least one be selected from alkyl, oxyl, carbonyl, aldehyde radical, carboxyl, ester group, and a kind of of cohort that halogen is formed be substituent silane (as above-mentioned), as predecessor.Feed ammonia subsequently again, make this silane that is substituted and ammonia gas react, carry out plasma enhanced chemical vapor deposition, on nmos pass transistor district 102 and PMOS transistor area 104, to form high compression stress film 124.Wherein, the flow of predecessor is between per minute 30 to 3000 grams, and the flow of ammonia is between 30sccm to 20000sccm.In addition, the power of the high and low frequency radio wave of formation high compression stress film 124 is all between 50 watts to 3000 watts.
As previous described embodiment, has for example Si-CH in the high compression stress film 124 of present embodiment
3Bond can be seized by these bonds and obtain the H+ ion, to improve the NBTI performance of element.
Then as shown in figure 14, carry out photoresist coating, exposure and developing process, to form patterning photoresist layer 126 and to cover whole PMOS transistor area 104.Then carry out etch process as mask with patterning photoresist layer 126, remove and be not patterned the zone that photoresist layer 126 covers, that is be covered in high compression stress film 124 in the nmos pass transistor district 102, to form high compression stress film 124 in PMOS grid 110 and regions and source 117 surfaces.Remove the patterning photoresist layer 126 that is covered on the PMOS transistor area 104 subsequently.Make CMOS as shown in figure 15.
Perhaps, according to another aspect of the present invention, the compression stress film in the PMOS district of the CMOS of the foregoing description for example can pass through known method earlier by silicomethane (SiH
4) make via PECVD with ammonia, the fluorine that reinjects, oxygen or carbon atom are to seize the H+ ion.For example, at the fabrication schedule that carries out CMOS extremely as shown in figure 12, form high tensile stress film 120 after NMOS grid 108 and regions and source 116 surfaces, then as shown in figure 16, feed silicomethane and ammonia, and carry out pecvd process, on nmos pass transistor district 102 and PMOS transistor area 104, to form high compression stress film 125.The flow of silicomethane can be between 30sccm to 300sccm, and the flow of ammonia can be between 30sccm to 2000sccm, uses respectively the high and low frequency radio wave power between 50 watts to 3000 watts.Then, carry out implantation step, inject fluorine atom, oxygen atom or carbon atom in compression stress film 125, the amount of its injection for example can be 10
12Atom/cm
2To 10
17Atom/cm
2, be preferably 10
14Atom/cm
2To 10
16Atom/cm
2The method of injecting can use for example high current injection method, current injection method, high energy injection method or its fellow to carry out.The chemicals that the source of F, O or C atom can be is for example fluorine-containing, contain oxygen or carbon containing.Then, carry out and same steps as shown in Figure 14, remove the high compression stress film 125 that is covered in the nmos pass transistor district 102,, make CMOS as shown in figure 15 to form high compression stress film 125 in PMOS grid 110 and regions and source 117 surfaces.
In addition, be not limited to the described order of making high tensile stress film earlier and then making the high compression stress film of previous Figure 10 to Figure 15, the present invention can form the high compression stress film again earlier on the PMOS transistor, forms high tensile stress film then after carrying out corresponding etch process on nmos pass transistor.That is, according to another aspect of the present invention, on the semiconductor-based end, feed as precursor as the above-mentioned silane that is substituted with N type active region and P type active region, and feeding ammonia, make the silane and the ammonia gas react that are substituted, to form the compression stress film to cover the semiconductor-based end, N type active region, to reach P type active region.The silane that is substituted has at least one substituting group that is selected from alkyl, oxyl, carbonyl, aldehyde radical, carboxyl, ester group, reaches group that halogen is formed.Form mask then and be positioned at the compression stress film of P type active region,, remove the part of the compression stress film of not masked covering to carry out corresponding etch process with covering.After removing mask, form high tensile stress film on the compression stress film of N type active region and P type active region.Carry out corresponding etch process again, remove the part of the tensile stress film of not masked covering, make CMOS.
Perhaps, according to another aspect of the present invention, the present invention can form the high compression stress film earlier on the PMOS transistor again, forms high tensile stress film then after carrying out corresponding etch process on nmos pass transistor.And form the high compression stress film in the transistorized mode of PMOS, and be to form general high compression stress film earlier, the fluorine that reinjects, oxygen or carbon atom are to film, so that the high compression stress film is doped with fluorine, oxygen or carbon atom.
In sum, the method that has the PMOS or the CMOS of high compression stress film compared to known manufacturing, prepared in the present invention high compression stress film Yin Qinei is doped with F, C or O atom, can seize and obtain the H+ ion that residues in when the high compression stress film is made in the film, therefore the NBTI performance be can improve, and then the rate of finished products and the usefulness of metal oxide semiconductor transistor effectively improved.
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (46)
1. make the transistorized method of P-type mos for one kind, comprising:
The semiconductor-based end, be provided;
Form grid structure, reach regions and source on this semiconductor-based end;
Silane is provided, and this silane has at least one substituting group, and this substituting group is selected from alkyl, oxyl, carbonyl, aldehyde radical, carboxyl, ester group, and the group formed of halogen is a kind of;
Ammonia is provided; And
Make this silane and this ammonia gas react, to form the compression stress film to be covered in this grid structure and this regions and source surface.
2. the method for claim 1, wherein this grid structure comprise grid, at this grid and the gate dielectric between this semiconductor-based end and be positioned at cover layer on this grid.
3. the method for claim 1, wherein this grid structure comprise grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the cover layer on this grid and be positioned at least one laying on the sidewall of this grid.
4. the method for claim 1, wherein this grid structure comprise grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the cover layer on this grid and be positioned at least one clearance wall on the sidewall of this grid.
5. the method for claim 1, wherein this grid structure comprise grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the metal silicide layer on this grid and be positioned at least one laying on the sidewall of this grid.
6. the method for claim 1, wherein this regions and source comprises a source and a lightly doped drain.
7. the method for claim 1, wherein this regions and source also comprises and is positioned at its surperficial metal silicide layer.
8. make the transistorized method of P-type mos for one kind, comprising:
The semiconductor-based end, be provided;
Form grid structure, reach regions and source on this semiconductor-based end;
Form the compression stress film to be covered in this grid structure and this regions and source surface; And
Inject fluorine atom, oxygen atom or carbon atom at this compression stress film.
9. method as claimed in claim 8, wherein this grid structure comprise grid, at this grid and the gate dielectric between this semiconductor-based end and be positioned at cover layer on this grid.
10. method as claimed in claim 8, wherein this grid structure comprise grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the cover layer on this grid and be positioned at least one laying on the sidewall of this grid.
11. method as claimed in claim 8, wherein this grid structure comprise grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the cover layer on this grid and be positioned at least one clearance wall on the sidewall of this grid.
12. method as claimed in claim 8, wherein this grid structure comprise grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the metal silicide layer on this grid and be positioned at least one laying on the sidewall of this grid.
13. method as claimed in claim 8, wherein this regions and source comprises source/drain and lightly doped drain.
14. method as claimed in claim 8, wherein this regions and source also comprises and is positioned at its surperficial metal silicide layer.
15. a method of making CMOS transistor comprises:
The semiconductor-based end is provided, and this semiconductor-based end, comprise N type active region and P type active region;
Form tensile stress film to cover this N type active region;
Silane is provided, and this silane has at least one substituting group, and this substituting group is selected from alkyl, oxyl, carbonyl, aldehyde radical, carboxyl, ester group, reaches a kind of of group that halogen is formed;
Ammonia is provided;
Make this silane and this ammonia gas react, to form the compression stress film to cover this semiconductor-based end, this tensile stress film, to reach this P type active region;
Form mask is positioned at this P type active region with covering this compression stress film;
Remove this compression stress membrane portions that is not covered by this mask; And
Remove this mask.
16. method as claimed in claim 15, wherein this N type active region comprises the first grid structure and first regions and source, and this P type active region comprises the second grid structure and second regions and source.
17. method as claimed in claim 16, wherein first grid structure and second grid structure include grid, at this grid and the gate dielectric between this semiconductor-based end and be positioned at cover layer on this grid.
18. method as claimed in claim 16, wherein first grid structure and second grid structure include grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the cover layer on this grid and be positioned at least one laying on the sidewall of this grid.
19. method as claimed in claim 16, wherein first grid structure and second grid structure include grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the cover layer on this grid and be positioned at least one clearance wall on the sidewall of this grid.
20. method as claimed in claim 16, wherein first grid structure and second grid structure include grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the metal silicide layer on this grid and be positioned at least one laying on the sidewall of this grid.
21. method as claimed in claim 16, wherein first regions and source and second regions and source include source/drain and lightly doped drain.
22. method as claimed in claim 16, wherein first regions and source and second regions and source all also comprise and are positioned at its surperficial metal silicide layer.
23. a method of making CMOS transistor comprises:
The semiconductor-based end is provided, and this semiconductor-based end, comprise N type active region and P type active region;
Form tensile stress film to cover this N type active region;
Form the compression stress film to cover this semiconductor-based end, this tensile stress film, to reach this P type active region;
Inject fluorine atom, oxygen atom or carbon atom at this compression stress film;
Form mask is positioned at this P type active region with covering this compression stress film;
Remove this compression stress membrane portions that is not covered by this mask; And
Remove this mask.
24. method as claimed in claim 23, wherein this N type active region comprises the first grid structure and first regions and source, and this P type active region comprises the second grid structure and second regions and source.
25. method as claimed in claim 24, wherein first grid structure and second grid structure include grid, at this grid and the gate dielectric between this semiconductor-based end and be positioned at cover layer on this grid.
26. method as claimed in claim 24, wherein first grid structure and second grid structure include grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the cover layer on this grid and be positioned at least one laying on the sidewall of this grid.
27. method as claimed in claim 24, wherein first grid structure and second grid structure include grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the cover layer on this grid and be positioned at least one clearance wall on the sidewall of this grid.
28. method as claimed in claim 24, wherein first grid structure and second grid structure include grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the metal silicide layer on this grid and be positioned at least one laying on the sidewall of this grid.
29. method as claimed in claim 24, wherein first regions and source and second regions and source include source/drain and lightly doped drain.
30. method as claimed in claim 24, wherein first regions and source and second regions and source all also comprise and are positioned at its surperficial metal silicide layer.
31. a method of making CMOS transistor comprises:
The semiconductor-based end is provided, and this semiconductor-based end, comprise N type active region and P type active region;
Silane is provided, and this silane has at least one substituting group, and this substituting group is selected from alkyl, oxyl, carbonyl, aldehyde radical, carboxyl, ester group, reaches a kind of of group that halogen is formed;
Ammonia is provided;
Make this silane and this ammonia gas react, to form the compression stress film to cover this semiconductor-based end, this N type active region, to reach this P type active region;
Form mask is positioned at this P type active region with covering this compression stress film;
Remove this compression stress membrane portions that is not covered by this mask;
Remove this mask; And
Form tensile stress film to cover this N type active region.
32. method as claimed in claim 31, wherein this N type active region comprises the first grid structure and first regions and source, and this P type active region comprises the second grid structure and second regions and source.
33. method as claimed in claim 32, wherein first grid structure and second grid structure include grid, at this grid and the gate dielectric between this semiconductor-based end and be positioned at cover layer on this grid.
34. method as claimed in claim 32, wherein first grid structure and second grid structure include grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the cover layer on this grid and be positioned at least one laying on the sidewall of this grid.
35. method as claimed in claim 32, wherein first grid structure and second grid structure include grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the cover layer on this grid and be positioned at least one clearance wall on the sidewall of this grid.
36. method as claimed in claim 32, wherein first grid structure and second grid structure include grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the metal silicide layer on this grid and be positioned at least one laying on the sidewall of this grid.
37. method as claimed in claim 32, wherein first regions and source and second regions and source include source/drain and lightly doped drain.
38. method as claimed in claim 32, wherein first regions and source and second regions and source all also comprise and are positioned at its surperficial metal silicide layer.
39. a method of making CMOS transistor comprises:
The semiconductor-based end is provided, and this semiconductor-based end, comprise N type active region and P type active region;
Form the compression stress film to cover this N type active region, this P type active region, to reach this semiconductor-based end;
Inject fluorine atom, oxygen atom or carbon atom at this compression stress film;
Form mask is positioned at this P type active region with covering this compression stress film;
Remove this compression stress membrane portions that is not covered by this mask;
Remove this mask; And
Form tensile stress film to cover this N type active region.
40. method as claimed in claim 39, wherein this N type active region comprises the first grid structure and first regions and source, and this P type active region comprises the second grid structure and second regions and source.
41. method as claimed in claim 40, wherein first grid structure and second grid structure include grid, at this grid and the gate dielectric between this semiconductor-based end and be positioned at cover layer on this grid.
42. method as claimed in claim 40, wherein first grid structure and second grid structure include grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the cover layer on this grid and be positioned at least one laying on the sidewall of this grid.
43. method as claimed in claim 40, wherein first grid structure and second grid structure include grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the cover layer on this grid and be positioned at least one clearance wall on the sidewall of this grid.
44. method as claimed in claim 40, wherein first grid structure and second grid structure include grid, at this grid and the gate dielectric between this semiconductor-based end, be positioned at the metal silicide layer on this grid and be positioned at least one laying on the sidewall of this grid.
45. method as claimed in claim 40, wherein first regions and source and second regions and source include source/drain and lightly doped drain.
46. method as claimed in claim 40, wherein first regions and source and second regions and source all also comprise and are positioned at its surperficial metal silicide layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101088787A CN101320691A (en) | 2007-06-05 | 2007-06-05 | Method for fabricating MOS transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101088787A CN101320691A (en) | 2007-06-05 | 2007-06-05 | Method for fabricating MOS transistor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237869A (en) * | 2010-04-28 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Integrated circuit and method for eliminating negative bias temperature instability |
| CN103943481A (en) * | 2014-04-22 | 2014-07-23 | 上海华力微电子有限公司 | Method for avoiding negative bias temperature instability of device |
-
2007
- 2007-06-05 CN CNA2007101088787A patent/CN101320691A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237869A (en) * | 2010-04-28 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Integrated circuit and method for eliminating negative bias temperature instability |
| CN102237869B (en) * | 2010-04-28 | 2016-08-10 | 台湾积体电路制造股份有限公司 | Integrated circuit and the method eliminating negative bias temperature instability |
| CN103943481A (en) * | 2014-04-22 | 2014-07-23 | 上海华力微电子有限公司 | Method for avoiding negative bias temperature instability of device |
| CN103943481B (en) * | 2014-04-22 | 2017-05-24 | 上海华力微电子有限公司 | Method for avoiding negative bias temperature instability of device |
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