201207958 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種金氧半導體電晶體的製造方法’尤指 一種能夠降低負偏壓溫度不穩定性（ne§ative bias temperature instability，NBTI)之應變矽金氧半導體電晶體的製造方法。 【先前技術】 隨著半導體製程進入深次微米（例如45奈米及以下）時 代’在半導體製程中利用一高應力膜來提升金氧半導體 (metal-oxide-semiconductor ’ MOS)電晶體的驅動電流（drive current)已逐漸成為一熱門課題。目前利用高應力膜來提升金 氧半導體電晶體的驅動電流可概分為兩方面：其一方面係應 用在鎳化矽等金屬矽化物形成前的多晶矽應力層（p〇ly stressor);另一方面則係應用在鎳化矽等金屬矽化物形成後之 接觸洞触刻停止層（contact etch stop layer，CESL)。 在接觸洞關停止層（CESL)的製程上，由於需考量形成 鎳化石夕時錢忍受較高熱效應的緣故，因此必須限制製程溫 度小於43叱。所以於f知技術中’在製造接觸㈣刻停止層 (CESL)之高應力膜時，一般會先沈積—由氣化石夕(腿)所組成 的4膜’然後再藉由此4膜來提升金氧半導體電晶體的驅動 201207958 電流。 請參考第1及2圖，第1及2圖為習知製造一高壓縮應力膜 於P型金氧半導體(P-type metal-oxide semiconductor，PMOS) 電晶體表面的方法示意圖。如第1圖所示，首先提供一半導體 基底10 ’例如一矽基底，且半導體基底10上包含有一閘極結 構12。其中’閘極結構12包含有一閘極氧化層（gate oxide) 14、一位於閘極氧化層14上之閘極16、一位於閘極16頂表面 之覆蓋層（cap layer) 18、以及一側壁子（spacer) 20。一般而 言’閘極氧化層14係由二氧化石夕（silicon dioxide，Si〇2)所構 成，閘極16係由摻雜多晶石夕(doped polysilicon)所構成，而覆 蓋層18則係由氮化石夕層所組成，用以保護閘極16。此外，間 極結構12所在之主動區域(active area)外圍的半導體基底1〇内 另環繞有一淺溝隔離(STI) 22。隨後進行一離子佈植(ion implantation)製程，以於側壁子20周圍之半導體基底1〇内形成 一源極/汲極區域2 6。接著於半導體基底1 〇與閘極結構12表面 游:鑛一金屬層（圖未示），例如一鎳金屬層。然後進行一快速 升溫退火(rapid thermal annealing，RTA)製程，使金屬層與間 極16以及源極/>及極區域26接觸的部分反應成；s夕化金屬層。最 後再去除未反應的金屬層。 接著，如第2圖所示，在反應室（chamber)中通入石夕曱燒 (silane，SiH4)與氨氣(ammonia，NH3) ’並進行一電渡増強化 4 201207958 學氣相沈積（plasma enhanced chemical vapor deposition， PECVD)製程，以形成一高壓縮應力膜（high compressive stress film) 28 (亦做為CESL)覆蓋於閘極結構12與源極/汲極區域26 表面。藉由高壓縮應力膜28來壓縮閘極16下方，亦即通道區 (channel region)之半導體基底10的晶格排列，進而提升通道 區的電洞遷移率以及應變石夕（strained-silicon) PMOS電晶體之 驅動電流（drive current)。 然而如上述之習知技術中，使用以矽曱烷為主的材料， 以PECVD方法製造SiN壓縮應力膜時，易發生嚴重的NBTI劣 化。如第3圖所示，係將具有壓縮應力分別為_〇.2、-2.4、及-2.7 GPa之SiN壓縮應力膜之半導體晶片樣品批號1、2、及3以一 測量時間施加一強制電壓（stress voltage)，然後量測該半導體 晶片上之MOS電晶體之起始電壓（threshold voltage)變化值。 當SiN壓細應力膜之應力達約-0.2 Gpa之應力以上時，即有大 於80 mV的起始電壓變化值，顯示NBTI的惡化。 因此’仍需要一種新穎的PM0S之製造方法，以製造具 有改善之NBT1性能之應變矽PM0S。 【發明内容】 本發明之一目的是提供一種製造PMOS電晶體之方法， 並提供一種技術相關之製造互補式金氧半導體(complementary 201207958 metal-oxide semiconductor，CMOS)電晶體之方法，以製造具 有改良之NBTI性能之應變矽PMOS及CMOS電晶體。 於本發明的一態樣中，依據本發明之製造PMOS電晶體 之方法，包括下列步驟。首先，提供一半導體基底。形成一 閘極結構、及一源極/汲極區域於半導體基底上。然後，形成 一壓縮應力膜覆蓋於閘極結構與源極/汲極區域表面。最後， 於壓縮應力臈植入氟(F)原子或碳(C)原子。 於本發明的另一態樣中，依據本發明之製造CM〇s電晶 體之方法，包括下列步驟。首先，提供一半導體基底，其包 括一 N型主動區域及一 P型主動區域。其次，形成一伸張應力 膜覆蓋N型主動區域。形成一麇縮應力膜覆蓋半導體基底、 伸張應力膜、及P型主動區域。接著’於壓缩應力膜植入說原 —主動區域之壓縮 應力膜。移除未被遮罩覆蓋之壓縮應力膜部分。最後，移除 遮罩，而製得一CMOS電晶體。 於本發明之又一態樣，依據本發明之製造CM〇s電晶體 之方法，包括下列步驟。首先，提供-半導體基底，其包括 動區域型主動欠’形成—壓縮應力 膜覆蓋N型主動區域、P型主動區域、及半導體某底。接著， 於壓縮應力膜植入氟原子或碳原子。然後，形成一遮罩^蓋 201207958 位於P 5L主動d域之壓縮應力膜。移除未被遮罩覆蓋之壓縮 應力膜部分。然後，移除遮罩。最後，形成一伸張應力膜覆 蓋N型主動區域，製得一 CM〇s電晶體。 【實施方式】 請參照第4至6圖，第4至6圖為本發明製造一具有高壓縮 應力膜之PMOS電晶體之方法之示意圖。如第*圖所示，首先 提供-半導體基底6G，例如—石夕晶圓（siu_戰㈣或一石夕覆 '邑、、束(S〇I)基底且半導體基底60上包含有-閘極結構63。閘 極、、-。構般可匕括問極，及可進—步包括例如間極介電詹、 覆盖層、自對準金屬石夕化物層（又稱為salidde)、襯塾層、或 側壁子。如第4圖所示，閘極結構63包含有-閘極66,並進-步包含-閘極介電層64位於間極的與半導體基底6〇之間、一 位於閘極66頂表面之覆蓋層仍、以及一側壁子％。一般而言， 閘極介電層64可為-利用熱氧化或沈料製程所形成之氧化 矽或氮矽化合物等絕緣物質所構成，而覆蓋層68則可由一用 以保濩閘極66之氮化砂層所組成。此外，閘極結構63所在之 主動區域(AA)外圍之+導體基底_ #王衰繞一淺溝隔離(STI) 62，用來使此pM〇S電晶體與其他元件相隔離。 如第5圖所示’接著進行一離子佈植（ion implantation)製 程，以於閘極結構63周圍之半導體基底6〇中形成一源極/汲極 201207958 區或接著進行一快速升溫退火（rapid therma丨annealing) 衣私利用9GG至的高溫來活化源極级極區域74内的 摻雜質，並同時修補在各離子佈植製程中受損之半導體基底 60表面的晶格結構。此外，亦可視產品需求及功能性考量， 另於源極/沒極區域74與閘極結構63之間分別形成一輕摻雜 汲極（LDD)或源極/汲極延伸（s〇urce/drai n extension) > 或者於 源極/汲極區域74與祕結構63表面再形成一自行對準金屬 石夕化物（sahcide)，此皆為習知相關技藝者與通常知識者所熟 知，在此不多加贅述。 然後如第6圖所示，進行— PECVD製程，以於閘極結構 63與源極/汲極區域74表面形成一高壓縮應力膜％。在本發明 之一較佳實施例中，此PECVD是先將半導體基底6〇置於一沉 積反應室中，接著通入一具有至少一選自烴基、烴氧基、羰 基、醛基、羧基、酯基、及_基所組成組群之一者為取代基 之矽烷做為一前驅物（precurs〇r)。隨後再通入氨氣，使此經取 代之带烧與氨氣反應，進行電漿增強化學氣相沈積，以於閘 極結構63與源極/汲極區域74表面形成一高壓縮應力膜76。其 中’前驅物之流量可介於每分鐘3〇至3000克，氨氣之流量可 "於母分鐘3〇標準立方公分（stancjarcj cubic centimeter per m_te ’ sccm)至20000 sccm之間。此外，形成高壓縮應力膜 76之高、低頻無線電波的功率可分別介於5〇瓦(watts)至3000 201207958 於本發明中所使用之經取代之矽烷，可具有一或多個矽原 子，例如為單矽烷、二矽烷、三矽烷、四矽烷、及五矽烷等， 並具有至少一個或更多個取代基。取代基可為獨立選自烴基、 烴氧基、羰基、醛基、羧基、酯基、及函基所組成組群之一者。 其中’烴基可舉例為烷基、烯基、或炔基。烴氧基可以—◦尺表 示’ R可舉例為烷基、烯基、或炔基。羰基可以-COR表示，R 可舉例為烷基、烯基、或炔基。醛基即為-CHO。羧基即為 -CO〇H。酯基可以_c〇〇R表示，R可舉例為烧基、稀基、或快 基。鹵基可舉例為氟(F)、氣(C1)、溴(Br)、或碘⑴。較佳所使 用之經取代之矽烷在壓縮應力膜製程條件下可為氣體，例如在 低壓或加溫下可為氣態，即可便利於本發明中利用。 使用具有上述取代基之矽烷做為前驅物以pECVD等方 法製造高壓縮應力膜，如同於在高壓縮應力膜中原位（in_situ) 摻雜例如氧原子、氟原子、碳原子等雜質，如此可攫獲(trap) 膜中的H+離子，大為改善PMOS之NBT1性能。形成高壓縮應 力膜之方法除了 PECVD之外，尚可舉例有低壓化學氣相沉積 法(LPCVD)及高密度電漿化學氣相沉積法(HDP cVD)。 表1顯示使用四曱基石夕烧(如]^〗116出丫15如116，本文中有時 簡稱為4MS)做為前驅物製得之高壓縮應力膜（siN膜）裴置性 月匕與使用矽曱故為主（SiHq-based)之前驅物製得高壓縮應力 201207958 膜（SiN膜）裝置性能之比較。使用四甲基矽烷，可製得約_36 GPa的高壓縮應力膜，使用未經取代的矽烷做為前驅物則製 得-3.0GPa之高壓縮應力膜（SiN膜）之裝置，二者均可獲得約 53%的PMOS離子增益（i〇n gain)。 表1 膜 處理 溫度CC) 裝置晶圓device Wafer) 毯覆ϊΐϊΐ (Blanket Wafer) 離子 (μΑ/μηι) 離子增益 離子增益 % 低應力 基準膜 400 390.38 應力 (GPa) -----—^· -0.2 厚度(埃) 以SiH4製得 -3.0GPa 400 599.99 209.61 53.69 -3.0 1013 以4MS製得 —2.7GPa 400 554.52 164.14 42.05 2.73 1011 以4MS製得 -3.0GPa 400 550.45 160.06 41.00 -3.06 977 以4MS製得 —3.6 GPa 480 597.89 207.51 53.16 -3.55 1029 將使用四甲基石夕烷製得高壓 使用錢為主製得高㈣應力臈⑽⑽之跋置比較抑抓 性能，如第7圖所示，使用四曱基料製得高壓縮應力膜（Sii 膜)之裝置’其高壓縮應力膜之應力為_2 75咖，教置之使拜 10 201207958 壽命測得大於十年’顯示有良好的NBTI性能。而使用石夕烧為 主製得高壓縮應力膜（SiN膜）之裝置，其高壓縮應力膜之應力 為約-0.65 GPa，裝置之使用壽命約五年，可知其NBTI性能較 差。 請參閱第8圖，第8圖為本發明之高壓縮應力膜之傅立葉 轉換紅外光譜（l ourier Transform Infrared Spectroscopy，FTIR) 示意圖。如第8圖所示，藉由使用四曱基矽烷做為前驅物與氨 氣反應’於電漿增強化學氣相沈積製程中產生的高壓縮應力 膜76，具有Si-CH3鍵結，顯示因於製造SiN膜時藉由原位 (in-situ)摻雜C雜質而產生，可幫助攫獲ηη·離子。PMOS之NBTI 性質因此而改良，並且同時亦可獲得高壓縮應力膜。 使高壓縮應力膜摻雜雜質以攫獲Η+離子之方法，除了上 述使用先驅物原位摻雜之外，尚可使用異位（ex-situ)摻雜的方 式將 〇 成C原子植入(implantation)已製得的高壓縮應 力膜中’ ^將存在於膜中的H+離子捕獲。F、0、或C原子捕 獲H+:子的能力，可依其陰 電性而定，一般是F > 〇〉C。因 此’清參閱第9圖，其顯示本發明之另一態樣之一具體實施 例。依據本發明之製造PMOS電晶體之方法，可包括下列步 驟。首先，提供—半導體基底80。然後，形成一閘極結構82。 閘極結構-般可包括閘極 ，及可進一步包括例如閘極介電 層、覆盍層、自對準金屬矽化物層、襯墊層、或側壁子。如 201207958 第9圖所示，閘極結構82包括閘極88、閘極介電層86、襯塾層 90、及覆蓋層92。及形成一源極/汲極區域於半導體基底上， 源極/汲極區域可進一步包括輕摻雜區94做為LDD與重摻雜 區96。源極/汲極區域與閘極結構表面亦吁進一步形成一自行 對準金屬矽化物。然後’形成一壓縮應力膜84覆蓋於閘極結 構82與源極/汲極區域表面。壓縮應力膜84的形成可藉由例如 習知之通入石夕曱坑與氨氣，並進行pecvd製程而達成。最 後’進行一佈植步驟，於壓縮應力膜84中植入一氟原子、氧 原子、或碳原子，其植入於膜内的量可為例如1〇12原子/cm2 至1017原子/cm2 ’較佳為ι〇ΐ4原子/(^2至1〇16原子/cm2。植入的 方法可使用例如高電流注入法（high current injection，HI)、中 電流注入法（medium current injection，Ml)、南能注入法（high energy injection，HEI)、或其類似者進行。F、Ο、或C原子的 來源可為例如含氟、含氧、或含碳的化學品(fluorine-，oxygen-, or carbon-containing chemicals) ° 請參閱第10圖至第15圖，第10圖至第15圖為本發明另一 實施例製造具有雙接觸洞蝕刻停止層（dual CESL)之CMOS之 方法示意圖。如第1〇圖所示，首先提供一個以淺溝隔離(STI) 106區隔出NMOS電晶體區1〇2以及pm〇S電晶體區1〇4的半導 體基底100，且各NMOS電晶體區1〇2及pM〇s電晶體區1〇4上 各具有一NMOS閘極108、一PMOS閘極no以及一設置於各閘 極與半導體基底100之間的閘極介電層114。接著於NMOS閘 12 201207958 極108與PMOS閘極110的側壁表面各別形成一由矽氧層與氮 化石夕層所構成的襯墊層112。 然後進行一離子佈植製程，以kNM0S閘極1〇8與PM〇s 閘極lio周圍的半導體基底丨咐各形成―源極/及極區域116 與117。I、接著進行-快速升溫退火製程，利用觸至1〇5〇。〇 的高溫來活化源極/汲極區域116與117内的摻雜質，並同時修 補在各離子佈植製程巾受損之半導體基底1()味面的晶格結 構。此外’亦可視產品需求及功能性考量，另於源極/沒極區 域H6、117與各閘極108、11〇之間分別形成一輕摻雜沒極 (LDD) 118 與 119。 接著於半導體基底〗00表面濺鍍一金屬層（圖未示），例如 -鎳金屬層’紐進行-快速升溫退火(RTA)製程，使金屬層 與NM0S閘極108、PM0S間極110以及源極/汲極區域116與 1Π接觸的部分反應成魏金屬層115，完成自行對準金屬石夕 化物製程(salicide)。 在去除未反應之金屬層之後，接著進行一pECVD製程， 以於NMOS電晶體區102與權〇8電晶體區！ 〇4中的矽化金屬 層115表面形成一高拉伸應力膜(high tensile st謂film) 120。 然後如第11®所示’進行—総塗佈、曝光以及顯影製 13 201207958 程’以形成一圖案化光阻層122並覆蓋整個NMOS電晶體區 102。接著以圖案化光阻層〖22做為遮罩進行一蝕刻製程，去 除未被圖案化光阻層122覆蓋的區域，亦即覆蓋於pM〇s電晶 體區104上的高拉伸應力膜12〇，以便僅留下高拉伸應力膜12〇 於NMOS閘極108與源極/汲極區域丨16表面。 如第12圖所示’接著移除覆蓋於NMOS電晶體區102上的 圖案化光阻層122。然後，如第π圖所示，於一反應室（未示出） 中進行PECVD製程：通入一具有至少一選自烴基、烴氧基、 羰基、醛基、羧基、酯基、及_基所組成組群之一者為取代 基之矽烷(如上述）’做為前驅物。隨後再通入氨氣，使此經取 代之石夕烧與氣氣反應’進行電漿增強化學氣相沈積，以於 NMOS電晶體區102與PMOS電晶體區1 〇4上形成一高壓縮應 力膜124。其中，前驅物之流量係介於每分鐘3〇至3〇〇〇克，氨 氣之流量係介於30 seem至20000 seem。此外，形成高壓縮應 力膜124之高、低頻無線電波的功率均係介於％瓦至⑽瓦。 如同先前所述之實施例，本實施例之高壓縮應力膜124 中具有例如Si-CH3鍵結，可藉由這些鍵結攫獲離子，以改 善元件之NBTI性能。 然後如第14圖所示，進行一光阻塗佈、曝光以及顯影製 程，以形成一圖案化光阻層126並覆蓋整個PM〇s電晶體區 104。接者以圖案化光阻層126做為遮罩進行一触刻製程，去 14 201207958 除未被圖案化光阻層126覆蓋的區域，亦即覆蓋於NMOS電晶 體區102丰的高壓縮應力膜124，以形成一高壓縮應力膜124 於PMOS閘極110與源極/汲極區域117表面。隨後移除覆蓋於 PMOS電晶體區104上的圖案化光阻層126。製得如第15圖所 示之CMOS。 或者，依據本發明之另一態樣，上述實施例之CMOS之 PMOS區的壓縮應力膜可先藉由例如習知方法由矽曱烷（SiH4) 與氨經由PECVD製得，再植入氟、氧、或碳原子以攫取H+離 子。例如，在進行CMOS之製造程序至如第12圖所示，形成 一高拉伸應力膜120於NMOS閘極108與源極/汲極區域116表 面之後，接著如第16圖所示’通入石夕曱烧與氨氣，並進行一 PECVD製程，以於NMOS電晶體區102與PMOS電晶體區104 上形成一高壓縮應力膜125。矽曱烷之流量可介於30 SCCm至 300 seem，氨氣之流量可介於30 seem至2000 seem，使用分別 〇 介於50瓦至3000瓦之高、低頻無線電波功率。接著，進行一 佈植步驟，於壓縮應力膜125中植入一氟原子、氧原子、或碳 原子，其植入的量可為例如1〇12原子/cm2至1017原子/cm2，較 佳為1014原子/cm2至1016原子/cm2。植入的方法可使用例如高 電流注入法、中電流注入法、高能注入法、或其類似者進行。 F、Ο、或C原子的來源可為例如含氟、含氧、或含碳的化學 品。然後’進行與第14圖所示之相同步驟，去除覆蓋於nm〇S 電晶體區102上的高壓縮應力膜125，以形成一高壓縮應力膜 15 201207958 125於PMOS閘極110與源極/汲極區域117表面’製得z士第15 圖所示之CMOS。 此外，不侷限於先前第10圖至第15圖所述先製邊问拉伸 應力膜然後再製造高壓縮應力膜的順序’本發明又外先形成 一高壓縮應力膜於PMOS電晶體上，然後於進行相對應之蝕 刻製程後形成一高拉伸應力膜於NMOS電晶體上。办即’依 據本發明之另一態樣，係於具有N型主動區域及P变主動區域 之半導體基底上通入一如上述之經取代之矽烷做為先驅物， 及通入氨氣，使經取代之矽烷與氨氣反應，以形成一壓縮應 力膜覆蓋半導體基底、N型主動區域、及P型主動區域。經取 代之矽烷具有至少一選自烴基、烴氧基、羰基、醛基、羧基、 酯基、及鹵基所組成組群之取代基。然後形成一遮罩覆蓋位 於P型主動區域之壓縮應力膜，以進行相對應之蝕刻製程，移 除未被遮罩覆蓋之壓縮應力膜的部分。移除遮罩後，形成— 高拉伸應力膜於N型主動區域及P型主動區域之壓縮應力膜 上。再進行相對應之蝕刻製程，移除未被遮罩覆蓋之拉伸應 力膜的部分，製得一CMOS。 或者’又依據本發明之另一態樣，本發明可先形成一高 壓縮應力膜於PMOS電晶體上，然後於進行相對應之姓刻製 程後形成一高拉伸應力膜於NMOS電晶體上。而形成一高壓 縮應力膜於PMOS電晶體之方式，是先形成一般之高壓縮廯 16 201207958 力膜’再植人氟、氧、或碳原子至財，以使高壓縮應力膜 摻雜有氟、氧、或碳原子。 、_、所迷，相較於習知製造具有高麗縮應力膜之pm〇S 或CMOS的方法，於本發明中所製得之高壓縮應力膜因其内 摻雜有F+、C、或〇原子，可攫獲高壓縮應力膜製造時殘留於 膜中的H離子，因此可改善NBTI性能，進而有效改良金氧半 導體電晶體的良率與效能。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第2圖為習知製造一高壓縮應力膜於PMOS電晶 體表面的方法示意圖。 第3圖為電晶體上壓縮應力對起始電壓（thresh〇ld v〇Uage) 變化值之作圖。 第4至6圖為依據本發明之製造一具有高壓縮應力膜之 PMOS電晶體之方法之示意圖。 第7圖顯示將依據本發明之方法製得之具有高壓縮應力 膜（SiN膜）之裝置與習知之方法製得之裝置比較其NBTI性能。 第8圖為本發明之高壓縮應力膜之傅立葉轉換紅外光譜 (Fourier Transform Infrared Spectroscopy，FTIR)示意圖。 17 201207958 第9圖顯示本發明之另一態樣之一具體實施例。 第10至15圖為本發明又一實施例製造具有雙接觸洞蝕刻 停止層（dual CESL)之CMOS之方法示意圖。 第16圖顯示本發明之另一態樣之一具體實施例。 【主要元件符號說明】 18 201207958 10 半導體基底 90 襯墊層 12 閘極結構 92 覆蓋層 14 閘極氧化層 94 輕摻雜區 16 閘極 96 重摻雜區 18 覆蓋層 100 半導體基底 20 側壁子 102 NMOS電晶體區 22 淺溝隔離 104 PMOS電晶體區 26 源極/汲極區域 106 淺溝隔離 28 高壓縮應力膜 108 NMOS閘極 60 半導體基底 110 PMOS閘極 62 淺溝隔離 112 概塾層 63 閘極結構 114 閘極介電層 64 閘極介電層 115 石夕化金屬層 66 閘極 116 源極/及極區域 68 覆蓋層 117 源極/;及極區域 70 側壁子 118 輕摻雜汲極 74 源極/汲極區域 119 輕摻雜没極 76 高壓縮應力膜 120 高拉伸應力膜 80 半導體基底 122 圖案化光阻層 82 閘極結構 124 高壓縮應力膜 84 壓縮應力膜 125 高壓縮應力膜 86 閘極介電層 126 圖案化光阻層 88 閘極 19201207958 VI. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a MOS transistor, in particular, a method capable of reducing negative bias temperature instability (NBTI) A method of manufacturing a strained germanium oxynitride transistor. [Prior Art] As the semiconductor process enters the deep sub-micron (eg, 45 nm and below) era, a high stress film is used in the semiconductor process to enhance the drive current of a metal-oxide-semiconductor 'MOS transistor. (drive current) has gradually become a hot topic. At present, the use of a high-stress film to enhance the driving current of a MOS transistor can be roughly divided into two aspects: one is applied to a polycrystalline ruthenium stress layer before formation of a metal ruthenium such as nickel ruthenium; The aspect is applied to a contact etch stop layer (CESL) after formation of a metal telluride such as nickel bismuth. In the process of contacting the hole stop layer (CESL), it is necessary to limit the process temperature to less than 43 由于 because of the need to consider the formation of nickel fossils in the case of high heat effects. Therefore, in the high-stress film of the contact (four) stop layer (CESL), it is generally deposited first—the 4 film consisting of gasification stone (leg) and then lifted by the 4 film. The MOS transistor drives the 201207958 current. Please refer to Figures 1 and 2. Figures 1 and 2 are schematic views showing a method for fabricating a high compressive stress film on the surface of a P-type metal-oxide semiconductor (PMOS) transistor. As shown in Fig. 1, a semiconductor substrate 10', such as a germanium substrate, is first provided, and a semiconductor structure 10 includes a gate structure 12. Wherein the gate structure 12 includes a gate oxide 14, a gate 16 on the gate oxide layer 14, a cap layer 18 on the top surface of the gate 16, and a sidewall. Spacer 20. In general, the gate oxide layer 14 is composed of silicon dioxide (Si 2 ), the gate 16 is composed of doped polysilicon, and the cover layer 18 is It is composed of a layer of nitride nitride to protect the gate 16. In addition, a shallow trench isolation (STI) 22 is surrounded by a semiconductor substrate 1 in the periphery of the active area where the interlayer structure 12 is located. An ion implantation process is then performed to form a source/drain region 26 in the semiconductor substrate 1A around the sidewall spacer 20. Then, a surface of the semiconductor substrate 1 and the gate structure 12 is etched: a metal layer (not shown), such as a nickel metal layer. Then, a rapid thermal annealing (RTA) process is performed to react the metal layer with the portion of the electrode 16 and the source/> and the polar region 26 to form a metal layer. Finally, the unreacted metal layer is removed. Next, as shown in Fig. 2, silane (SiH4) and ammonia (NH3) are introduced into the chamber, and an electric ferrolysis is carried out 4 201207958 A plasma enhanced chemical vapor deposition (PECVD) process is performed to form a high compressive stress film 28 (also referred to as CESL) overlying the gate structure 12 and the source/drain regions 26. The lattice structure of the semiconductor substrate 10 under the gate region, that is, the channel region, is compressed by the high compressive stress film 28, thereby improving the hole mobility of the channel region and the strained-silicon PMOS. The drive current of the transistor. However, in the above-mentioned conventional technique, when a SiN compressive stress film is produced by a PECVD method using a material mainly composed of decane, serious NBTI deterioration is liable to occur. As shown in FIG. 3, a semiconductor wafer sample batch number 1, 2, and 3 having a SiN compressive stress film having compressive stresses of _〇.2, -2.4, and -2.7 GPa, respectively, is applied with a forcing voltage at a measurement time. (stress voltage), then measuring the threshold voltage change value of the MOS transistor on the semiconductor wafer. When the stress of the SiN compact stress film is above the stress of about -0.2 Gpa, there is an initial voltage change value of more than 80 mV, indicating deterioration of NBTI. Therefore, there is still a need for a novel manufacturing method for PMOS to produce strain 矽 PMOS having improved NBT1 performance. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for fabricating a PMOS transistor, and to provide a method for fabricating a complementary metal oxide semiconductor (CMOS) transistor, which is improved in manufacturing. NBTI performance strain 矽 PMOS and CMOS transistors. In one aspect of the invention, a method of fabricating a PMOS transistor in accordance with the present invention comprises the following steps. First, a semiconductor substrate is provided. A gate structure and a source/drain region are formed on the semiconductor substrate. Then, a compressive stress film is formed to cover the surface of the gate structure and the source/drain region. Finally, a fluorine (F) atom or a carbon (C) atom is implanted under compressive stress. In another aspect of the invention, a method of making a CM〇s electroforming body in accordance with the present invention comprises the following steps. First, a semiconductor substrate is provided that includes an N-type active region and a P-type active region. Next, a tensile stress film is formed to cover the N-type active region. A shrinkage stress film is formed to cover the semiconductor substrate, the tensile stress film, and the P-type active region. Then, a compressive stress film is implanted into the original stress-active film. The portion of the compressive stress film that is not covered by the mask is removed. Finally, the mask is removed and a CMOS transistor is fabricated. In still another aspect of the invention, a method of making a CM〇s transistor in accordance with the present invention comprises the following steps. First, a semiconductor substrate is provided which includes a dynamic region type active under-forming-compressive stress film covering an N-type active region, a P-type active region, and a semiconductor substrate. Next, a fluorine atom or a carbon atom is implanted in the compressive stress film. Then, a mask is formed. 201207958 A compressive stress film located in the P 5L active d domain. Remove the portion of the compressive stress film that is not covered by the mask. Then, remove the mask. Finally, a tensile stress film is formed to cover the N-type active region, and a CM〇s transistor is obtained. [Embodiment] Referring to Figures 4 to 6, Figures 4 through 6 are schematic views of a method of fabricating a PMOS transistor having a high compressive stress film. As shown in FIG. 1, first, a semiconductor substrate 6G is provided, for example, a Si Xi wafer (siu_war (4) or a shi 邑 、, 束 (S〇I) substrate and the semiconductor substrate 60 includes a - gate Structure 63. The gate, the - structure can include the question pole, and the advance step includes, for example, the inter-electrode dielectric, the cover layer, the self-aligned metallurgical layer (also known as salidde), the lining a layer or a sidewall. As shown in FIG. 4, the gate structure 63 includes a gate 66, and the step-by-step includes a gate dielectric layer 64 between the interpole and the semiconductor substrate 6? The cover layer of the top surface of the pole 66 is still and a side wall %. In general, the gate dielectric layer 64 may be an insulating material such as a ruthenium oxide or a ruthenium compound formed by a thermal oxidation or a sinking process. The cover layer 68 may be composed of a nitriding sand layer for protecting the gate 66. In addition, the + conductor base of the active region (AA) where the gate structure 63 is located _ #王衰绕一 shallow trench isolation (STI 62, used to isolate the pM〇S transistor from other components. As shown in Figure 5, 'Ion ion implantation (ion implantation) a process for forming a source/drain 201290958 region in the semiconductor substrate 6〇 around the gate structure 63 or subsequently performing a rapid temperature rise annealing (rapid therma丨annealing) using a high temperature of 9GG to activate the source level The doping in the polar region 74, and at the same time repairing the lattice structure of the surface of the semiconductor substrate 60 damaged in each ion implantation process. In addition, depending on product requirements and functional considerations, and in the source/drain region A lightly doped drain (LDD) or a source/drain extension (s〇urce/drai n extension) is formed between the 74 and the gate structure 63, respectively, or in the source/drain region 74 and the secret structure 63. The surface is further formed with a self-aligned metal sahcide, which is well known to those skilled in the art and will not be described here. Then, as shown in Fig. 6, a PECVD process is performed to Forming a high compressive stress film % on the surface of the gate structure 63 and the source/drain region 74. In a preferred embodiment of the present invention, the PECVD is performed by first placing the semiconductor substrate 6 in a deposition reaction chamber. And then accessing one having at least one selected from One of the group consisting of a base group, a hydrocarbyloxy group, a carbonyl group, an aldehyde group, a carboxyl group, an ester group, and a group is a precursor of a decane as a precursor (precurs〇r), and then an ammonia gas is introduced thereto. The substituted ribbon is reacted with ammonia gas to perform plasma enhanced chemical vapor deposition to form a high compressive stress film 76 on the surface of the gate structure 63 and the source/drain region 74. The flow of the precursor can be Between 3 〇 and 3000 gram per minute, the flow rate of ammonia gas can be between 3 cc and 3,200 cmcm in the mother's minute (stancjarcj cubic centimeter per m_te 'sccm). In addition, the high and low frequency radio waves forming the high compressive stress film 76 may have a power ranging from 5 watts to 3000 201207958. The substituted decane used in the present invention may have one or more germanium atoms. For example, it is monodecane, dioxane, trioxane, tetradecane, pentadecane, etc., and has at least one or more substituents. The substituent may be one selected from the group consisting of a hydrocarbon group, a hydrocarbyloxy group, a carbonyl group, an aldehyde group, a carboxyl group, an ester group, and a functional group. Wherein the hydrocarbon group can be exemplified by an alkyl group, an alkenyl group or an alkynyl group. The alkoxy group may be represented by a scale of 'R' which may be exemplified by an alkyl group, an alkenyl group or an alkynyl group. The carbonyl group may be represented by -COR, and R may be exemplified by an alkyl group, an alkenyl group, or an alkynyl group. The aldehyde group is -CHO. The carboxyl group is -CO〇H. The ester group may be represented by _c 〇〇 R, and R may be exemplified by an alkyl group, a dilute group, or a fast group. The halogen group can be exemplified by fluorine (F), gas (C1), bromine (Br), or iodine (1). Preferably, the substituted decane used may be a gas under compressive stress film processing conditions, such as a gaseous state at low pressure or elevated temperature, which may be conveniently utilized in the present invention. Using a decane having the above substituent as a precursor, a high compressive stress film is produced by a method such as pECVD, as in the case of in-situ doping an impurity such as an oxygen atom, a fluorine atom or a carbon atom in a high compressive stress film. Trapping the H+ ions in the film greatly improves the NBT1 performance of the PMOS. In addition to PECVD, low pressure chemical vapor deposition (LPCVD) and high density plasma chemical vapor deposition (HDP cVD) can be exemplified in addition to PECVD. Table 1 shows the use of a tetrarule-based shovel (such as ] ^ 116 116 丫 15 such as 116, sometimes referred to herein as 4MS) as a precursor of the high compressive stress film (siN film) 裴 性 匕 匕A comparison of the performance of a high compressive stress 201207958 membrane (SiN membrane) device was prepared using a SiHq-based precursor. Using tetramethyl decane, a high compressive stress film of about _36 GPa can be obtained, and an unsubstituted decane is used as a precursor to prepare a high compressive stress film (SiN film) of -3.0 GPa, both of which are used. A PMOS ion gain of about 53% is obtained. Table 1 Membrane Processing Temperature CC) Device Wafer) Blanket Wafer Ion (μΑ/μηι) Ion Gain Ion Gain % Low Stress Reference Film 400 390.38 Stress (GPa) -----—^· - 0.2 Thickness (Angstrom) Manufactured as SiH4 -3.0GPa 400 599.99 209.61 53.69 -3.0 1013 Manufactured in 4MS - 2.7GPa 400 554.52 164.14 42.05 2.73 1011 Manufactured from 4MS -3.0GPa 400 550.45 160.06 41.00 -3.06 977 Made with 4MS —3.6 GPa 480 597.89 207.51 53.16 -3.55 1029 The high-pressure use of tetramethyl oxalate is used to produce high (four) stress 臈 (10) (10), which is more effective, as shown in Figure 7, using four 曱The device for producing a high compressive stress film (Sii film) with a base material has a high compressive stress film with a stress of _2 75 ga, and the teachings of 10 10 079 10 201207958 lifetime measured more than ten years 'have good NBTI performance. The device using the high-compression stress film (SiN film) prepared by using Shi Xizhuo has a stress of about -0.65 GPa in the high compressive stress film and a service life of about five years in the device, and the NBTI performance is poor. Please refer to FIG. 8. FIG. 8 is a schematic diagram of the Fourier Transform Infrared Spectroscopy (FTIR) of the high compressive stress film of the present invention. As shown in Fig. 8, by using tetradecyl decane as a precursor to react with ammonia gas, a high compressive stress film 76 produced in a plasma enhanced chemical vapor deposition process has a Si-CH3 bond, showing It is produced by in-situ doping C impurities during the fabrication of the SiN film, which helps to capture ηη· ions. The NBTI nature of the PMOS is thus improved, and at the same time a high compressive stress film is also obtained. The method of doping the high compressive stress film with impurities to sequester Η+ ions, in addition to the above-mentioned in situ doping using the precursor, can also be implanted into the C atom using an ex-situ doping method. (implantation) The high compressive stress film that has been produced '^ captures the H+ ions present in the film. The ability of F, 0, or C atoms to capture H+: can depend on its electrical properties, generally F > 〇 > C. Therefore, referring to Fig. 9, there is shown a specific embodiment of another aspect of the present invention. The method of fabricating a PMOS transistor in accordance with the present invention may include the following steps. First, a semiconductor substrate 80 is provided. Then, a gate structure 82 is formed. The gate structure can generally include a gate, and can further include, for example, a gate dielectric layer, a germanium layer, a self-aligned metal telluride layer, a liner layer, or a sidewall spacer. As shown in FIG. 9 of 201207958, the gate structure 82 includes a gate 88, a gate dielectric layer 86, a lining layer 90, and a cap layer 92. And forming a source/drain region on the semiconductor substrate, the source/drain region may further include a lightly doped region 94 as the LDD and heavily doped region 96. The source/drain regions and the gate structure surface also urge further formation of a self-aligned metal telluride. Then, a compressive stress film 84 is formed to cover the surface of the gate structure 82 and the source/drain regions. The formation of the compressive stress film 84 can be achieved by, for example, conventionally introducing a stone pit and ammonia gas and performing a pecvd process. Finally, an implantation step is performed to implant a fluorine atom, an oxygen atom, or a carbon atom into the compressive stress film 84, and the amount thereof implanted in the film may be, for example, 1 〇 12 atoms/cm 2 to 10 17 atoms/cm 2 ' It is preferably ι 4 atoms / (^2 to 1 〇 16 atoms / cm 2 . The implantation method can use, for example, high current injection (HI), medium current injection (Ml), High energy injection (HEI), or the like. The source of the F, Ο, or C atom can be, for example, a fluorine-containing, oxygen-containing, or carbon-containing chemical (fluorine-, oxygen-, or Carbon-containing chemicals) Please refer to FIGS. 10 to 15 , and FIGS. 10 to 15 are schematic views showing a method of fabricating a CMOS having a double contact hole etch stop layer (dual CESL) according to another embodiment of the present invention. As shown in the first figure, a semiconductor substrate 100 in which the NMOS transistor region 1〇2 and the pm〇S transistor region 1〇4 are separated by a shallow trench isolation (STI) 106 region is provided first, and each NMOS transistor region is 1〇. 2 and pM〇s transistor region 1〇4 each has an NMOS gate 108, a PMOS gate no and a setting a gate dielectric layer 114 between each of the gates and the semiconductor substrate 100. Then, a lining composed of a silicon oxide layer and a nitride layer is formed on the sidewalls of the NMOS gate 12 201207958 and the sidewalls of the PMOS gate 110. The pad layer 112. Then, an ion implantation process is performed to form source-/and-pole regions 116 and 117 with the semiconductor substrate 周围 around the kNM0S gate 1〇8 and the PM〇s gate lio. I, then proceed- The rapid temperature annealing process utilizes a high temperature of 1〇5〇. 活化 to activate the dopants in the source/drain regions 116 and 117, and simultaneously repair the damaged semiconductor substrate 1 in each ion implantation process towel ( The lattice structure of the noodles. In addition, depending on the product requirements and functional considerations, a lightly doped immersion (LDD) is formed between the source/drain regions H6 and 117 and the gates 108 and 11〇, respectively. 118 and 119. Then, a metal layer (not shown) is sputtered on the surface of the semiconductor substrate 00, for example, a nickel metal layer 'new-speed rapid annealing (RTA) process, the metal layer and the NM0S gate 108, PM0S The interpole 110 and the source/drain region 116 are in contact with the 1Π portion to form a Wei metal layer. 115. Complete self-alignment of the salicide. After removing the unreacted metal layer, a pECVD process is performed to form the NMOS transistor region 102 and the weight 8 transistor region! A high tensile st film 120 is formed on the surface of the deuterated metal layer 115 in the crucible 4. Then, as shown in Fig. 11®, the coating is applied, exposed, and developed to form a patterned photoresist layer 122 and cover the entire NMOS transistor region 102. Then, an etching process is performed by using the patterned photoresist layer 22 as a mask to remove the region not covered by the patterned photoresist layer 122, that is, the high tensile stress film 12 covering the pM〇s transistor region 104. That is, so as to leave only the high tensile stress film 12 on the surface of the NMOS gate 108 and the source/drain region 丨16. As shown in Fig. 12, the patterned photoresist layer 122 overlying the NMOS transistor region 102 is then removed. Then, as shown in FIG. π, a PECVD process is carried out in a reaction chamber (not shown): one having at least one selected from the group consisting of a hydrocarbon group, a hydrocarbyloxy group, a carbonyl group, an aldehyde group, a carboxyl group, an ester group, and a group One of the constituent groups is a substituent of decane (as described above) as a precursor. Subsequently, ammonia gas is introduced to cause the substituted stone gas to react with the gas gas to perform plasma enhanced chemical vapor deposition to form a high compressive stress on the NMOS transistor region 102 and the PMOS transistor region 1 〇4. Film 124. Among them, the flow rate of the precursor is between 3 〇 and 3 每 per minute, and the flow rate of ammonia is between 30 seem and 20000 seem. In addition, the high and low frequency radio waves forming the high compression stress film 124 are between 10,000 watts and 10 watts. As in the previously described embodiment, the high compressive stress film 124 of the present embodiment has, for example, Si-CH3 bonds, and ions can be sequestered by these bonds to improve the NBTI performance of the device. Then, as shown in Fig. 14, a photoresist coating, exposure and development process is performed to form a patterned photoresist layer 126 and cover the entire PM?s transistor region 104. The receiver performs a etch process by using the patterned photoresist layer 126 as a mask, and removes the region not covered by the patterned photoresist layer 126, that is, the high compressive stress film covering the NMOS transistor region 102. 124 to form a high compressive stress film 124 on the surface of the PMOS gate 110 and source/drain regions 117. The patterned photoresist layer 126 overlying the PMOS transistor region 104 is then removed. A CMOS as shown in Fig. 15 is obtained. Alternatively, according to another aspect of the present invention, the compressive stress film of the PMOS region of the CMOS of the above embodiment may be first prepared by PECVD by decane (SiH4) and ammonia by a conventional method, and then implanted with fluorine. Oxygen, or carbon atoms, to extract H+ ions. For example, after performing the CMOS fabrication process to form a high tensile stress film 120 on the surface of the NMOS gate 108 and the source/drain region 116 as shown in FIG. 12, then as shown in FIG. The stone is burned with ammonia gas and subjected to a PECVD process to form a high compressive stress film 125 on the NMOS transistor region 102 and the PMOS transistor region 104. The flow rate of decane can range from 30 SCCm to 300 seem, and the flow rate of ammonia gas can range from 30 seem to 2000 seem, using high-frequency, low-frequency radio wave power of 瓦 between 50 watts and 3,000 watts. Next, an implantation step is performed to implant a fluorine atom, an oxygen atom, or a carbon atom into the compressive stress film 125, which may be implanted in an amount of, for example, 1 〇 12 atoms/cm 2 to 10 17 atoms/cm 2 , preferably 1014 atoms/cm2 to 1016 atoms/cm2. The method of implantation can be performed using, for example, a high current injection method, a medium current injection method, a high energy injection method, or the like. The source of the F, hydrazine, or C atom can be, for example, a fluorine-containing, oxygen-containing, or carbon-containing chemical. Then, the same steps as shown in FIG. 14 are performed to remove the high compressive stress film 125 overlying the nm〇S transistor region 102 to form a high compressive stress film 15 201207958 125 at the PMOS gate 110 and the source/ The surface of the bungee region 117 'produces the CMOS shown in Figure 15. In addition, it is not limited to the order of the first tensile stress film and then the high compressive stress film described in the previous FIGS. 10 to 15 '. The present invention further forms a high compressive stress film on the PMOS transistor. Then, a high tensile stress film is formed on the NMOS transistor after performing the corresponding etching process. According to another aspect of the present invention, a substituted base of decane is used as a precursor on a semiconductor substrate having an N-type active region and a P-active region, and an ammonia gas is introduced. The substituted decane reacts with ammonia gas to form a compressive stress film covering the semiconductor substrate, the N-type active region, and the P-type active region. The substituted decane has at least one substituent selected from the group consisting of a hydrocarbon group, a hydrocarbyloxy group, a carbonyl group, an aldehyde group, a carboxyl group, an ester group, and a halogen group. A mask is then formed overlying the compressive stress film in the P-type active region for a corresponding etch process to remove portions of the compressive stress film that are not covered by the mask. After the mask is removed, a high tensile stress film is formed on the compressive stress film of the N-type active region and the P-type active region. A corresponding etch process is then performed to remove portions of the tensile stress film that are not covered by the mask to produce a CMOS. Or in accordance with another aspect of the present invention, the present invention may first form a high compressive stress film on a PMOS transistor, and then form a high tensile stress film on the NMOS transistor after performing a corresponding process. . The way to form a high compressive stress film in a PMOS transistor is to form a general high compression 廯16 201207958 force film 'replanting human fluorine, oxygen, or carbon atoms to the rich, so that the high compressive stress film is doped with fluorine. , oxygen, or carbon atoms. _, 迷迷, compared to the conventional method of manufacturing pm 〇 S or CMOS with a high stress film, the high compressive stress film produced in the present invention is doped with F+, C, or 〇 The atom can capture the H ions remaining in the film during the manufacture of the high compressive stress film, thereby improving the NBTI performance and effectively improving the yield and performance of the MOS transistor. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the patent scope of the present invention are intended to be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 to Fig. 2 are schematic views showing a method of manufacturing a high compressive stress film on the surface of a PMOS transistor. Figure 3 is a plot of the compressive stress on the transistor versus the change in the starting voltage (thresh〇ld v〇Uage). Figures 4 through 6 are schematic views of a method of fabricating a PMOS transistor having a high compressive stress film in accordance with the present invention. Fig. 7 shows the NBTI performance of a device having a high compressive stress film (SiN film) obtained by the method of the present invention compared with a device obtained by a conventional method. Figure 8 is a schematic diagram of Fourier Transform Infrared Spectroscopy (FTIR) of a high compressive stress film of the present invention. 17 201207958 Figure 9 shows a specific embodiment of another aspect of the invention. 10 to 15 are schematic views showing a method of fabricating a CMOS having a double contact hole etch stop layer (dual CESL) according to still another embodiment of the present invention. Figure 16 shows a specific embodiment of another aspect of the present invention. [Main component symbol description] 18 201207958 10 Semiconductor substrate 90 liner layer 12 gate structure 92 cladding layer 14 gate oxide layer 94 lightly doped region 16 gate 96 heavily doped region 18 cladding layer 100 semiconductor substrate 20 sidewall spacer 102 NMOS transistor region 22 shallow trench isolation 104 PMOS transistor region 26 source/drain region 106 shallow trench isolation 28 high compressive stress film 108 NMOS gate 60 semiconductor substrate 110 PMOS gate 62 shallow trench isolation 112 profile layer 63 gate Pole structure 114 gate dielectric layer 64 gate dielectric layer 115 Sihua metal layer 66 gate 116 source/pole region 68 cap layer 117 source/; and pole region 70 sidewall spacer 118 lightly doped bungee 74 Source/drain region 119 Lightly doped immersion 76 High compressive stress film 120 High tensile stress film 80 Semiconductor substrate 122 Patterned photoresist layer 82 Gate structure 124 High compressive stress film 84 Compressive stress film 125 High compressive stress Membrane 86 gate dielectric layer 126 patterned photoresist layer 88 gate 19