CN103928448A - 芯片装置和用于制造芯片装置的方法 - Google Patents
芯片装置和用于制造芯片装置的方法 Download PDFInfo
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- CN103928448A CN103928448A CN201410019271.1A CN201410019271A CN103928448A CN 103928448 A CN103928448 A CN 103928448A CN 201410019271 A CN201410019271 A CN 201410019271A CN 103928448 A CN103928448 A CN 103928448A
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Classifications
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
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Abstract
本发明涉及芯片装置和用于制造芯片装置的方法。提供了一种芯片装置,所述芯片装置包括:载体;电连接到载体的第一芯片;设置在载体之上的陶瓷层;以及设置在陶瓷层之上的第二芯片;其中所述陶瓷层具有处于从大约3%到大约70%的范围内的孔隙率。
Description
技术领域
各种实施例总体上涉及芯片装置和用于制造芯片装置的方法。
背景技术
各种电子应用和芯片封装可以包括多于一个半导体芯片。这种应用可以包括引线框,所述引线框可以承载诸如功率半导体芯片之类的芯片,并且可能必要的是,另一个芯片(例如控制器芯片)可以与引线框电隔离。可被用于电绝缘且可包括电绝缘材料(例如,电绝缘胶)的芯片粘附材料可以拥有一些所需要的一般热机的机械性质,然而它们可能未展现出足以使足够大的热量损耗能够从电子电路中移除的散热。期望热量从芯片且离开引线框高效地消散。未被当前技术所满足的其他期望特性包括能够将电绝缘隔离岛精确地放置在引线框上。进一步期望降低加工成本。
直到现在,如图1A和1B中所示,逻辑芯片和功率芯片可以连接到引线框。例如,当在外壳中的引线框105之上连接逻辑芯片时,可以在功率芯片103之上形成在图1A中被示为顶芯片的逻辑芯片101。该装置可以例如适用于TO-220外壳中的Cool MOS芯片。隔离漏极(isodrain)107(例如金属(Cu)-陶瓷-金属(Cu)夹层,也被称为双铜接合(DCB)层)可以被布置在芯片之间,例如,如图1B中所示在功率芯片和引线框之间。
图2A到2C示出芯片相邻(chip-by-chip)装置和具有隔离的功率芯片的隔离漏极107(DCB)。图2A和2B示出在集成电路中设置在功率芯片103之上的逻辑芯片101的顶视图。图2C示出在功率芯片103和引线框105之间实现的DCB 107的侧视图。DCB金属-陶瓷-金属夹层的实现可以包括复杂且昂贵的工艺。DCB的最高成本因素之一是用于陶瓷工艺和甚至陶瓷到芯片背面的连接的双软焊接工艺。此外,针对每个芯片尺寸而适配的设计修改是冗长且昂贵的。
发明内容
各种实施例提供了一种芯片装置,包括:载体;电连接到所述载体的第一芯片;设置在所述载体之上的陶瓷层;以及设置在所述陶瓷层之上的第二芯片;其中所述陶瓷层具有处于从大约3%到大约70%的范围内的孔隙率。
附图说明
在附图中,遍及不同的视图,相似的附图标记通常指代相同的部分。附图不必按比例绘制,而是重点通常在于图示本发明的原理。在下面的描述中,参考下面的附图来描述本发明的各种实施例,在附图中:
图1A和1B示出多芯片封装;
图2A到2C示出多芯片封装;
图3示出根据实施例的芯片装置;
图4示出根据实施例的用于制造芯片装置的方法;
图5A到5E示出根据实施例的用于制造芯片装置的方法;
图6示出根据实施例的芯片装置;
图7示出根据实施例的芯片装置。
具体实施方式
下面的详细描述参考了附图,附图以图示的方式示出在其中可以实施本发明的实施例和特定细节。
词语“示例性”在本文中用于意指“用作示例、实例或说明”。本文中描述为“示例性”的任何实施例或设计不必然被理解为与其他实施例或设计相比优选或有利。
词语“在……之上”在本文中用于描述“在”面或表面“之上”形成特征(例如,层),并可以用于意指可以“直接在”所暗指的面或表面“上”(例如与其直接接触地)形成该特征(例如,层)。词语“在……之上”在本文中还可以用于描述“在”面或表面“之上”形成特征(例如,层),并可以用于意指可以“不直接在”所暗指的面或表面“上”形成该特征(例如,层),其中一个或多个附加层被布置在所暗指的面或表面和所形成的层之间。
各种实施例提供了一种用于制造芯片装置的方法。所述方法可以包括选择性地将不同孔隙率的薄层沉积在彼此之上以将多芯片模块中的芯片(例如,逻辑芯片)电绝缘。
各种实施例提供了一种芯片装置,其包括一个或多个陶瓷或塑料层和/或处于所述陶瓷或塑料层之上的一个或多个上覆的导电层,其中所述一个或多个层可以与多芯片模块中的芯片(例如,逻辑芯片)电绝缘和/或从其中耗散热量。
各种实施例提供了一种用于使用粒子沉积工艺(例如,等离子体尘埃(dust)方法)制造多芯片模块以制造用于散热并将多芯片模块中的芯片(例如,逻辑芯片)电绝缘的一个或多个层的方法。
各种实施例提供了一种芯片封装(例如,单芯片或多芯片封装),其在半导体外壳内包括一个或多个芯片,其中,包括有机材料(例如,纯有机材料)的陶瓷材料可以被用于散热。
图3示出根据实施例的芯片装置302。
芯片装置302(例如,芯片封装)可以包括载体304。芯片装置302可以包括:电连接到载体304的第一芯片306;设置在载体304之上的陶瓷层308;和设置在陶瓷层308之上的第二芯片312,其中陶瓷层308具有处于从大约3%到大约70%的范围内的孔隙率。
图4示出根据各种实施例的用于制造芯片装置(诸如芯片装置302)的方法400。
方法400可以包括:
将第一芯片电连接到载体(在410中);
将具有处于从大约3%到大约70%的范围内的孔隙率的陶瓷层设置在载体之上(在420中);以及
将第二芯片设置在陶瓷层之上(在403中)。
图5A到5E示出根据各种实施例的用于制造芯片装置(诸如,芯片装置302)的方法500。
如图5A中所示,方法500可以包括将第一芯片306电连接到载体304。载体304可以包括芯片载体。例如,载体304可以包括导电板和/或衬底。载体304可以包括引线框,所述引线框包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:铜、镍、铁、铜合金、镍合金、铁合金。
载体304可以具有在从大约80μm到大约1500μm的范围内变化的厚度 ,例如大约100μm到大约500μm,例如大约120μm到大约200μm。
第一芯片306(例如,半导体芯片,例如半导体管芯)可以被设置在载体顶面514之上。载体304可以包括载体底面516,其中载体底面516面对与载体顶面514所面对的方向相反的方向。
第一芯片306可以具有在从大约20μm到大约450μm的范围内变化的厚度,例如大约20μm到大约250μm,例如大约40μm到大约60μm。
第一芯片306可以经由导电介质518(例如,管芯附着材料)电连接到载体304。导电介质518可以包括来自下述材料组的至少一种材料,所述组由以下各项构成:焊料、软焊料、扩散焊料、浆料(paste)、纳米浆料(nanopaste)、粘合剂、导电粘合剂、导热粘合剂。导电介质518可以包括来自下述元素组的至少一种元素,所述元素组由以下元素构成:Ag、Zn、Sn、Pb、Bi、In、Cu、Au、Ni。
可选地,除将第一芯片306粘附到载体304的导电介质518外,可以不在第一芯片306和载体304之间布置其他层,那么第一芯片306可以被理解为直接形成在载体304上。
导电介质518可以被配置成将第一芯片底面522粘附到载体顶面514。第一芯片306可以包括第一芯片顶面524,其中第一芯片顶面524可以面对与第一芯片底面522所面对的方向相反的方向。第一芯片306可以包括在芯片底面522之上形成的芯片背面金属化层517,其也可以被称作背面接触焊盘。第一芯片306的芯片背面金属化层517可以经由导电介质518而粘附到载体304。
第一芯片306可以包括功率半导体芯片,例如能够承载在从大约20V到大约5000V的范围内变化的电压的器件,例如从大约100V到大约3000V,例如从大约500V到大约1500V。
功率半导体芯片可以包括来自由以下各项构成的组的至少一个功率半导体器件:功率晶体管、功率MOS晶体管、功率双极型晶体管、功率场效应晶体管、功率绝缘栅双极型晶体管、晶闸管、MOS控制晶闸管、可控硅整流器(silicon controlled rectifier)、功率肖特基(schottky)二极管、碳化硅二极管、氮化镓器件。
顶面也可以被称为芯片的“第一面”、“前面”或“上面”。术语“顶面”、“第一面”、“前面”或“上面”可以在后文中可互换地使用。底面也可以被称为芯片的“第二面”或“背面”。术语“第二面”、“背面”或“底面”可以在后文中可互换地使用。
如本文关于半导体功率器件所使用的,术语“顶面”、“第一面”、“前面”或“上面”可以被理解为指代芯片的其中可以形成栅极区和至少一个第一源极/漏极区的面。术语“第二面”、“背面”或“底面”可以被理解为指代芯片的其中可以形成第二源极/漏极区(例如,芯片背面金属化部517)的面。因此,半导体功率晶体管可以支持经过芯片的垂直电流流动,例如在第一芯片顶面524和第一芯片底面522之间。
在图5B中,陶瓷层308可以被设置在载体304之上。陶瓷层308可以被设置在载体顶面514之上。在陶瓷层308被沉积之前,第一芯片306可能已经被设置在载体304之上。可替代地,当陶瓷层308被沉积时,第一芯片306可能还未被设置在载体304之上。如果在陶瓷层308被沉积之前第一芯片306可能已经被设置在载体304之上,则可以将陶瓷层308沉积在载体304的与第一芯片306隔开分隔距离设置的区域之上。分隔距离可以定义将在载体304之上形成的第二芯片312与第一芯片306分离的最终距离,而与第一芯片306和第二芯片312中的哪个首先被形成在载体304之上无关。分隔距离可以在从大约10μm到大约10mm的范围内变化,例如从大约50μm到大约5mm,例如从大约100μm到大约1mm。
陶瓷层308可以具有在从大约40μm到大约300μm的范围内变化的厚度,例如大约45μm到大约150μm,例如大约50μm到大约100μm。
沉积陶瓷层308的工艺可以包括使用用于沉积一种或多种粒子的等离子体尘埃方法或者任何其他合适的粒子沉积方法,例如冷喷涂方法,例如热喷涂方法。
陶瓷层308的沉积可以包括沉积可包括一种或多种粒子的陶瓷层308,其中所述一种或多种粒子可以包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:玻璃、氧化铝和氮化铝、二氧化硅、氮化硅、碳化硅、二氧化钛、氮化钛、二氧化锆、氮化硼、碳化硼。
陶瓷层308可以进一步包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:有机材料、塑料、环氧树脂、聚酰亚胺、热固料、聚丙烯酸酯、硅树脂和硅石。
例如,陶瓷层308可以被沉积,其中,包括来自下述材料组的至少一种材料的一种或多种粒子可以被沉积在304上,所述材料组由以下各项构成:玻璃、氧化铝和氮化铝。随后,来自下述材料组的至少一种材料可以被沉积以填充一种或多种粒子之间的一个或多个空间并穿透或相互扩散到多孔陶瓷层内,所述材料组由以下各项构成:塑料、环氧树脂、聚酰亚胺、热固料、聚丙烯酸酯、硅树脂和硅石。
可以执行陶瓷层308的加热,并且可以烧结一种或多种粒子,使其粘附于载体304。所述一种或多种粒子可以被加热直到处于大约20℃到大约150℃的范围内的温度,以引起对粒子的烧结。烧结温度低于针对当前焊接处理而使用的温度。基本粘附机制可以是化学和/或物理主导的粘附。
陶瓷层308可以包括第一部分,例如填充部分,其中所述第一部分可以包括一种或多种粒子,所述一种或多种粒子包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:玻璃、氧化铝和氮化铝、二氧化硅、氮化硅、碳化硅、二氧化钛、氮化钛、二氧化锆、氮化硼、碳化硼。这些一种或多种粒子可以包括陶瓷材料。陶瓷层308可以包括第二部分,例如基质部分,其中所述第二部分包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:有机材料、塑料、环氧树脂、聚酰亚胺、热固料、聚丙烯酸酯、硅树脂和硅石。
陶瓷层308可以具有在从大约3%到大约70%的范围内变化的孔隙率,例如大约10%到大约50%,例如大约20%到大约30%。孔隙率可以指代陶瓷层308的总体积中可被空隙(例如,空间)占用的百分比。所述空隙可以是被空气所占据的空间。
图7示出使用等离子体尘埃沉积形成的典型涂覆层的图像。可以期望陶瓷层308包括可使用等离子体尘埃沉积而沉积的导热粒子,其中导热粒子可以被电绝缘材料包围。如从图7中显而易见,一个或多个空隙或空间748可以占据陶瓷层308的总体积;空隙或空间748从而影响或贡献于陶瓷层308的孔隙率。
陶瓷层308可以包括电绝缘材料(例如,基质部分或第二部分)和导热材料(例如,第一部分或填充部分)中的至少一种。陶瓷层308可以展现出电绝缘性质和/或导热性质。
陶瓷层308可以通过粘合剂材料525而被直接粘附在载体304上。由于除将陶瓷层308粘附到载体304的粘合剂材料525外,可以不在陶瓷层308和载体304之间布置其他层,因此陶瓷层308可以被理解为直接形成在载体304上。可替代地,陶瓷层308也可以由于烧结而被粘附到载体304,所述烧结可以使陶瓷层308(例如,陶瓷层308中的粒子)甚至在没有粘合剂材料525的情况下粘附到载体304。
尽管图中仅示出一个陶瓷层,即仅示出陶瓷层308,但是根据其他实施例,使多个陶瓷层308形成在载体304和第二芯片312之间可以是可能的。例如,该多个陶瓷层可以均具有彼此不同的孔隙率。
如图5C中所示,可选地,导电层526可以被沉积。导电层526可以被沉积在陶瓷层308之上。导电层526可以包括金属。导电层526可以包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:锡、铅、银、铜、镍、钯、锌和铝,可选地,可以添加金、锑、无机元素和有机元素。导电层526可以包括一种或多种粒子,所述一种或多种粒子包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:锡、铅、银、铜、镍、钯、锌、铝、金、锑、无机元素和有机元素。导电层526可以包括来自由以下各项构成的粒子组的一种或多种粒子:结构、纳米结构、微结构、纳米粒、微粒、纤维、纳米纤维、微纤维。
导电层526可以被直接沉积在陶瓷层308上。可以理解的是,导电层526可以因此被形成在载体顶面514之上,其中陶瓷层308可以处于导电层526和载体304之间。导电层526可以被形成在陶瓷层顶面528之上(例如,直接在其上),其中陶瓷层顶面528可以与载体顶面514面对相同的方向。
可以使用用于沉积一种或多种粒子的等离子体尘埃方法或者任何其他合适的粒子沉积方法(例如冷喷涂)来沉积导电层526。
导电层526可以具有在从大约100μm到大约0.5μm的范围内变化的厚度,例如大约50μm到大约1μm,例如大约30μm到大约10μm。
在图5D中,第二芯片312可以被沉积在陶瓷层308之上。如果导电层526已经被沉积在陶瓷层308之上,那么第二芯片312可以被设置在导电层526之上或者直接设置在其上。
第二芯片312(例如,半导体芯片,例如半导体管芯)可以包括半导体集成电路逻辑芯片,其中半导体集成电路逻辑芯片可以包括来自半导体逻辑器件组的至少一个半导体逻辑器件,所述组由以下各项构成:专用集成芯片(ASIC)、驱动器、控制器和传感器。可以理解的是,半导体逻辑芯片(即,逻辑集成电路芯片)可以包括低功率半导体器件,例如能够承载高达100V到150V或更低的器件。
第二芯片312可以具有在从大约100μm到大约300μm的范围内变化的厚度,例如大约120μm到大约250μm,例如大约150μm到大约200μm。
可选地,第二芯片312可以通过粘合剂材料532而被粘附(例如,胶合)到导电层526。粘合剂材料532可以包括以下各项中的至少一种:焊料、软焊料、扩散焊料、浆料、纳米浆料、粘合剂、导电粘合剂、导热粘合剂。根据另一个实施例,粘合剂材料532可以不是必需的。导电层526自身可以包括以下各项中的至少一种:焊料、软焊料、扩散焊料、浆料、纳米浆料、粘合剂、导电粘合剂、导热粘合剂;从而消除对粘合剂材料532的需要。换句话说,第二芯片底面534可以经由导电层526而被粘附到陶瓷层308。因此,导电层526自身可以包括以下各项中的至少一种:焊料、软焊料、扩散焊料、浆料、纳米浆料、粘合剂、导电粘合剂和/或导热粘合剂;由来自下述材料组的至少一种材料形成,所述组由以下各项构成:锡、铅、银、铜、镍、钯、锌、铝、金、锑、无机元素和有机元素。
第二芯片底面534可以面对载体底面516所面对的方向。第二芯片顶面536可以面对与第二芯片底面534所面对的方向相反的方向。
可以执行温度工艺(例如,烧结工艺),其中可以使用烧结工艺来烧结陶瓷层308。即使在陶瓷层308和第二芯片312被沉积之前第一芯片306已经位于载体304之上可能不是必要的,也可以使用烧结工艺来烧结陶瓷层308,甚至其中,第一芯片306可能已经位于载体304之上(例如,直接在其上)。也就是说,在陶瓷层308中形成粒子的烧结所需的温度工艺可以不将热负载放置在第一芯片306或第二芯片312上。烧结可以导致导电层526被粘附(例如,强粘附)到陶瓷层308。
如本文关于较低功率半导体逻辑器件所使用的,第二芯片顶面536可以被理解为指代承载一个或多个接触焊盘或电接触部的芯片的面,其中接合焊盘或电连接部可以被附着;或者其中该面是可大部分被金属化层覆盖的芯片的面。第二芯片底面534可以被理解为指代可没有金属化或接触焊盘或电接触部的芯片的面。
可以理解的是,第二芯片312可以与载体304电绝缘。换句话说,陶瓷层308和/或陶瓷层308与导电层526结合可以将第二芯片312与载体304电绝缘。同时,陶瓷层308和/或陶瓷层308与导电层526结合可以在将第二芯片312与载体304电绝缘的同时提供卓越的散热质量。
沉积陶瓷层308和至少一个其他导电层(例如,导电层526和/或另外的导电层646)中的至少一个可以允许第二芯片312连接到引线框。使用等离子体尘埃方法,可以容易地控制陶瓷层308和至少一个其他导电层(例如,导电层526和/或另外的导电层646)中的至少一个的厚度。使用等离子体尘埃方法,陶瓷层308的厚度可以得到使用上文已经描述的材料的包括陶瓷或塑料的薄层。
仅需要几个工艺来沉积陶瓷层308和至少一个其他导电层(例如,导电层526和/或另外的导电层646)中的至少一个。因此,在实现逻辑或MOSFET芯片与引线框的电绝缘的同时,加工成本低。
在图5E中,第一芯片306可以经由一个或多个电互连部538而电连接到第二芯片312。一个或多个电互连部538可以包括来自下述电互连部组的至少一种电互连部,所述组由以下各项构成:线、导电线、接合线、夹、导电夹。一个或多个电互连部538可以包括来自下述材料组的至少一种材料、元素或合金,所述组由以下各项构成:铜、铝、银、锡、金、锌、镍。一个或多个电互连部538可以将在第一芯片顶面524之上形成的一个或多个第一芯片接触焊盘542电连接到在第二芯片顶面536之上形成的一个或多个第二芯片接触焊盘544。一个或多个第一芯片接触焊盘542和/或一个或多个第二芯片接触焊盘544可以包括来自下述材料组的至少一种材料、元素或合金,所述组由以下各项构成:铜、铝、银、锡、金、锌、镍。
除一个或多个电互连部538外,第二芯片312可以与第一芯片306隔离(例如,电绝缘)。例如,可以利用电绝缘材料来封装和/或部分地包围第二芯片312,以使得其与第一芯片306隔离。此外,第二芯片312可以通过陶瓷层308和/或导电层526与载体304隔离。第一芯片306、第二芯片312和一个或多个电互连部538可以电连接,其中第一芯片306和第二芯片312可以形成半桥电路装置。
作为方法500的结果,可以形成芯片装置502。如图5E中示出的芯片装置502可以包括载体304。芯片装置502可以包括:电连接到载体304的第一芯片306;设置在载体304之上的陶瓷层308;和设置在陶瓷层308之上的第二芯片312;其中陶瓷层308具有在从大约3%到大约70%的范围内变化的孔隙率。
芯片装置502可以包括半桥电路装置,所述半桥电路装置包括在模块内布置的功率半导体芯片(例如,第一芯片306)和控制器芯片(例如,第二芯片312)。
图6示出根据另一个实施例的芯片装置602。芯片装置602可以包括已关于芯片装置502描述的一个或多个或者所有特征。根据另一个实施例,可选地,可以执行附加工艺,其中另外的导电层646可以在沉积陶瓷层308之前被沉积在载体304之上(例如,直接在其上)。如果在另外的导电层646被沉积之前第一芯片306可能已经位于载体304上,则另外的导电层646可以被沉积在载体304的与第一芯片306隔开分隔距离设置的区域之上,其中如前所述,分隔距离可以定义将在载体304之上形成的第二芯片312与第一芯片306分离的最终距离。另外的导电层646可以包括已经关于导电层526描述的一个或多个或者所有特征。
陶瓷层308和至少一个其他导电层(例如,导电层526和/或另外的导电层646)中的至少一个可以通过旋转(spin)沉积(例如,粒子的旋涂)而沉积。所述粒子可以包括处于微米范围内和/或处于纳米范围内的粒子。所述粒子可以最终与后续的温度工艺(例如,后文描述的烧结工艺)组合。
导电层526和/或另外的导电层646可以包括但不限于包括铜。类似于导电层526,另外的导电层646可以包括一种或多种粒子,所述一种或多种粒子包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:锡、铅、银、铜、镍、钯、锌、铝、金、锑、无机元素和有机元素。
另外的导电层646可以通过诸如粘合剂532之类的粘合剂而被粘附到载体304。
可替代地,另外的导电层646可以没有接合材料,例如没有粘合剂,例如没有胶。例如,另外的导电层646可以包括由来自下述材料组的至少一种材料形成的焊料、软焊料、扩散焊料、浆料、纳米浆料、粘合剂、导电粘合剂、导热粘合剂中的至少一种,所述组由以下各项构成:锡、铅、银、铜、镍、钯、锌、铝、金、锑、无机元素和有机元素。
另外的导电层646可以具有在从大约100μm到大约0.5μm的范围内变化的厚度,例如大约50μm到大约1μm,例如大约30μm到大约10μm。
然后,可以随后执行例如如关于工艺410到430描述的和/或如关于图5B到5E描述的工艺。如420和图5B中所述,陶瓷层308可以被沉积在载体304之上,且甚至被直接沉积在另外的导电层646上。第二芯片312到陶瓷层308的粘附可以使用单个工艺进行,例如其中可以大致在相同的时间处(例如,同时地)执行烧结和/或焊接,其中导电层526和/或另外的导电层646可以被固定到陶瓷层308。
陶瓷层308和/或陶瓷层308与导电层526和/或另外的导电层646结合可以将第二芯片312与载体304电绝缘。同时,陶瓷层308和/或陶瓷层308与导电层526和/或另外的导电层646结合可以在将第二芯片312与载体304电绝缘的同时提供卓越的散热质量。陶瓷层308和/或陶瓷层308与导电层526和/或另外的导电层646结合可以具有处于1W/(m·K)到大约400W/(m·K)的范围内的热导率。
芯片装置602可以包括芯片封装(例如,芯片封装模块)的至少一部分。芯片装置602可以包括载体304。芯片装置602可以包括:电连接到载体304的第一芯片306;设置在载体304之上的另外的导电层646;设置在另外的导电层646之上的陶瓷层308;以及设置在陶瓷层308之上的第二芯片312;其中陶瓷层308具有处于从大约3%到大约70%的范围内的孔隙率。
根据各种实施例,芯片装置602可以包括处于第二芯片底面534和载体304之间的夹层装置,例如铜524-陶瓷308-铜646夹层装置,其中第二芯片312可以被设置在夹层装置之上。另外的导电层646(即,第二铜层)可以被设置在载体304(即,引线框)和陶瓷层308之间。
导电层526和另外的导电层646中的至少一个可以充当焊接材料,例如充当软焊料,例如充当扩散焊接材料。
导电层526和另外的导电层646中的至少一个可能不必然被需要。可替代地,陶瓷层304可以通过粘合剂材料(例如,电绝缘粘合剂,例如导电粘合剂、环氧树脂、胶、浆料、粘合箔片、粘合膜)粘附到载体304。
第一芯片306和第二芯片312可以均包括半导体芯片,例如半导体管芯。第一芯片306和第二芯片312可以均包括半导体芯片,例如管芯,该半导体芯片包括晶片衬底。半导体芯片可以包括在晶片衬底之上形成的一个或多个电子组件。晶片衬底可以包括各种材料,例如半导体材料。晶片衬底可以包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:硅、锗、III到V族材料、聚合物。根据实施例,晶片衬底可以包括掺杂或非掺杂的硅。根据另一个实施例,晶片衬底可以包括绝缘体上硅SOI晶片。根据实施例,晶片衬底可以包括半导体化合物材料,例如砷化镓(GaAs)、磷化铟(InP)。根据实施例,晶片衬底可以包括四元半导体化合物材料,例如铟镓砷(InGaAs)。
可以理解的是,分隔距离可以定义将在载体304之上形成的第二芯片312与第一芯片306分离的距离。换句话说,第一芯片306可以被形成在载体304的第一部分之上,第二芯片312可以被形成在载体304的第二部分之上,其中载体304的第一部分可以与载体304的第二部分不同。还可以理解的是,载体304的第一部分可以与载体304的第二部分分离分隔距离。因此可以理解的是,第一芯片306可以被形成在载体304的第一部分之上,并且陶瓷层308和/或至少一个其他导电层(例如,导电层526和/或另外的导电层646)中的至少一个可以被形成在载体304的第二部分之上,其中载体304的第一部分可以与载体304的第二部分不同,即载体304的第一部分可以与载体304的第二部分分离分隔距离。
各种实施例提供了一种用于制造需要沉积设备的简化集合(例如,仅一个设备)以加工和生产电绝缘介质(例如,陶瓷层308和至少一个其他导电层(例如,导电层526和/或另外的导电层646)中的至少一个)的芯片装置的方法。
各种实施例提供了一种芯片装置和用于制造芯片装置的方法,这带来了低生产成本和低加工成本,例如成本减少到至多1/15到1/10。
各种实施例提供了一种芯片装置和用于制造芯片装置的方法,其中材料可以被容易地改变,并被适配于芯片装置上的特定设计,并且其中该方法提供了在该芯片装置中适配和改变材料以用作层组件的灵活性。
各种实施例提供了一种芯片装置和用于制造芯片装置的方法,需要材料和/或材料成分的简单制备以便容易地改进层功能。这种材料成分的示例可以包括例如将焊接材料沉积在导电层526和/或另外的导电层646中,所述导电层526和/或另外的导电层646可以均包括铜。另外的示例包括将玻璃和/或陶瓷填充粒子与塑料和/或环氧树脂混合以形成陶瓷层308。另外的示例包括将聚合物基质(polymer matrix)混合到陶瓷层308中。
各种实施例提供了一种芯片装置和用于制造芯片装置的方法,其中层厚度(例如,陶瓷层308和至少一个其他导电层(例如,导电层526和/或另外的导电层646)中的至少一个的厚度)可以在涂覆工艺的时间期间被容易地改变。
各种实施例提供了一种芯片装置和用于制造芯片装置的方法,其中陶瓷层308和至少一个其他导电层(例如,导电层526和/或另外的导电层646)中的至少一个可以通过在第一芯片306和/或第二芯片312上几乎不放置或不放置热负载的工艺而在该工艺期间产生,例如,使用冷涂覆工艺,例如冷喷涂工艺。
各种实施例提供了一种用于制造芯片装置的方法,其中快速的设计改变是可能的,例如,通过使沉积设备的喷嘴变化,例如通过对涂覆喷嘴进行编程。
各种实施例提供了一种用于制造芯片装置的方法,其中陶瓷层308和至少一个其他导电层(例如,导电层526和/或另外的导电层646)中的至少一个的位置(即,隔离岛的位置)可以被精确地放置在载体304之上。
各种实施例提供了一种用于制造芯片装置的方法,其中可以避免焊接材料的伸展的问题,从而消除该芯片装置内短路的危险。
各种实施例提供了一种用于在陶瓷材料之上(例如在陶瓷材料308之上,例如直接在陶瓷材料308上)沉积焊接层的方法。
各种实施例提供了一种芯片装置,包括:载体;电连接到载体的第一芯片;设置在载体之上的陶瓷层;以及设置在陶瓷层之上的第二芯片;其中所述陶瓷层具有处于从3%到70%的范围内的孔隙率。
根据实施例,第一芯片包括功率半导体芯片。
根据实施例,功率半导体芯片包括来自由以下各项构成的组的至少一个功率半导体器件:功率晶体管、功率MOS晶体管、功率双极型晶体管、功率场效应晶体管、功率绝缘栅双极型晶体管、晶闸管、MOS控制晶闸管、可控硅整流器、功率肖特基二极管、碳化硅二极管、氮化镓器件。
根据实施例,第二芯片包括半导体逻辑芯片和半导体存储芯片中的至少一个。
根据实施例,半导体逻辑芯片包括来自由以下各项构成的组的至少一个半导体逻辑器件:专用集成电路、驱动器、控制器、传感器。
根据实施例,第一芯片面经由导电介质电连接到载体。
根据实施例,导电介质包括来自下述材料组的至少一种材料,所述组由以下各项构成:焊料、软焊料、扩散焊料、浆料、纳米浆料、粘合剂、导电粘合剂和导热粘合剂。
根据实施例,陶瓷层通过粘合剂材料而直接粘附在载体上。
根据实施例,陶瓷层包括电绝缘材料和导热材料中的至少一种。
根据实施例,陶瓷层包括一种或多种粒子,所述一种或多种粒子包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:氧化铝和氮化铝、二氧化硅、氮化硅、碳化硅、二氧化钛、氮化钛、二氧化锆、氮化硼、碳化硼。
根据实施例,陶瓷层进一步包括填充材料,所述填充材料包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:有机材料、塑料、环氧树脂、聚酰亚胺、热固料、聚丙烯酸酯、硅树脂和硅石。
根据实施例,载体包括导电材料。
根据实施例,载体包括引线框,所述引线框包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:铜、镍、铁、银、金、钯、磷、铜合金、镍合金、铁合金、银合金、金合金、钯合金、磷合金。
根据实施例,芯片装置进一步包括设置在载体之上的密封材料,其中所述密封材料至少部分地包围第一芯片和第二芯片、以及载体的一个或多个侧面。
根据实施例,芯片装置进一步包括在陶瓷层之上和之下中的至少一个形成的至少一个导电层。
根据实施例,所述至少一个导电层包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:锡、铅、银、铜、镍、钯、锌、铝、金、锑、无机元素和有机元素。
各种实施例提供了一种用于制造芯片装置的方法,所述方法包括:将第一芯片电连接到载体;在载体之上设置具有处于从3%到70%的范围内的孔隙率的陶瓷层;以及在陶瓷层之上设置第二芯片。
根据实施例,所述方法包括通过粘合剂材料将陶瓷层直接粘附在载体上。
根据实施例,陶瓷层包括电绝缘材料和导热材料中的至少一种。
根据实施例,陶瓷层包括一种或多种粒子,所述一种或多种粒子包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:氧化铝和氮化铝、二氧化硅、氮化硅、碳化硅、二氧化钛、氮化钛、二氧化锆、氮化硼、碳化硼。
根据实施例,载体包括引线框,所述引线框包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:铜、镍、铁、银、金、钯、磷、铜合金、镍合金、铁合金、银合金、金合金、钯合金、磷合金。
根据实施例,所述方法进一步包括在载体之上设置密封材料,其中所述密封材料至少部分地包围第一芯片和第二芯片、以及载体的一个或多个侧面。
根据实施例,所述方法进一步包括:在沉积陶瓷层之前在载体之上形成至少一个导电层;以及将陶瓷层沉积在所述至少一个导电层之上。
根据实施例,所述方法进一步包括:在陶瓷层之上形成至少一个导电层;以及在所述至少一个导电层之上形成第二芯片。
根据实施例,所述方法进一步包括经由导电介质将第一芯片电连接到载体,所述导电介质包括来自下述材料组的至少一种材料,所述组由以下各项构成:焊料、软焊料、扩散焊料、浆料、纳米浆料、粘合剂、导电粘合剂、导热粘合剂。
根据实施例,所述第一芯片包括功率半导体芯片。
根据实施例,所述第二芯片包括半导体逻辑芯片和半导体存储芯片中的至少一种。
尽管已经参考特定实施例特别示出和描述本发明,但是本领域技术人员应该理解的是,可以在不背离如所附权利要求所限定的本发明的精神和范围的情况下对本发明作出形式和细节上的各种改变。本发明的范围从而由所附权利要求指示,并且,落在权利要求的等同物的含义和范围内的所有改变因此意在被包含在内。
Claims (27)
1.一种芯片装置,包括:
载体;
电连接到载体的第一芯片;
设置在载体之上的陶瓷层;以及
设置在陶瓷层之上的第二芯片;
其中所述陶瓷层具有处于从3%到70%的范围内的孔隙率。
2.根据权利要求1所述的芯片装置,
其中所述第一芯片包括功率半导体芯片。
3.根据权利要求2所述的芯片装置,
其中功率半导体芯片包括来自由以下各项构成的组的至少一个功率半导体器件:功率晶体管、功率MOS晶体管、功率双极型晶体管、功率场效应晶体管、功率绝缘栅双极型晶体管、晶闸管、MOS控制晶闸管、可控硅整流器、功率肖特基二极管、碳化硅二极管、氮化镓器件。
4.根据权利要求1所述的芯片装置,
其中所述第二芯片包括半导体逻辑芯片或半导体存储芯片。
5.根据权利要求4所述的芯片装置,
其中所述半导体逻辑芯片包括来自由以下各项构成的组的半导体逻辑器件:专用集成电路、驱动器、控制器和传感器。
6.根据权利要求1所述的芯片装置,
其中第一芯片面经由导电介质电连接到载体。
7.根据权利要求6所述的芯片装置,
其中所述导电介质包括来自下述材料组的至少一种材料,所述组由以下各项构成:焊料、软焊料、扩散焊料、浆料、纳米浆料、粘合剂、导电粘合剂和导热粘合剂。
8.根据权利要求1所述的芯片装置,
其中所述陶瓷层通过粘合剂材料而直接粘附在载体上。
9.根据权利要求1所述的芯片装置,
其中所述陶瓷层包括电绝缘材料和导热材料中的至少一种。
10.根据权利要求1所述的芯片装置,
其中所述陶瓷层包括一种或多种粒子,所述一种或多种粒子包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:氧化铝、氮化铝、二氧化硅、氮化硅、碳化硅、二氧化钛、氮化钛、二氧化锆、氮化硼、碳化硼。
11.根据权利要求10所述的芯片装置,
其中所述陶瓷层进一步包括填充材料,所述填充材料包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:有机材料、塑料、环氧树脂、聚酰亚胺、热固料、聚丙烯酸酯、硅树脂和硅石。
12.根据权利要求1所述的芯片装置,
其中所述载体包括导电材料。
13.根据权利要求1所述的芯片装置,
其中所述载体包括引线框,所述引线框包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:铜、镍、铁、银、金、钯、磷、铜合金、镍合金、铁合金、银合金、金合金、钯合金、磷合金。
14.根据权利要求1所述的芯片装置,进一步包括:
设置在载体之上的密封材料,其中所述密封材料至少部分地包围第一芯片和第二芯片、以及载体的一个或多个侧面。
15.根据权利要求1所述的芯片装置,进一步包括:
在陶瓷层之上和之下中的至少一个形成的至少一个导电层。
16.根据权利要求1所述的芯片装置,
其中所述至少一个导电层包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:锡、铅、银、铜、镍、钯、锌、铝、金、锑、无机元素和有机元素。
17.一种用于制造芯片装置的方法,所述方法包括:
将第一芯片电连接到载体;
在载体之上设置具有处于从3%到70%的范围内的孔隙率的陶瓷层;以及
在陶瓷层之上设置第二芯片。
18.根据权利要求17所述的方法,包括:
通过粘合剂材料将陶瓷层直接粘附在载体上。
19.根据权利要求17所述的方法,
其中所述陶瓷层包括电绝缘材料和导热材料中的至少一种。
20.根据权利要求17所述的方法,
其中所述陶瓷层包括一种或多种粒子,所述一种或多种粒子包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:氧化铝、氮化铝、二氧化硅、氮化硅、碳化硅、二氧化钛、氮化钛、二氧化锆、氮化硼、碳化硼。
21.根据权利要求17所述的方法,
其中所述载体包括引线框,所述引线框包括来自下述材料组的至少一种材料,所述材料组由以下各项构成:铜、镍、铁、银、金、钯、磷、铜合金、镍合金、铁合金、银合金、金合金、钯合金、磷合金。
22.根据权利要求17所述的方法,进一步包括:
在载体之上设置密封材料,其中所述密封材料至少部分地包围第一芯片和第二芯片、以及载体的一个或多个侧面。
23.根据权利要求17所述的方法,进一步包括:
在沉积陶瓷层之前在载体之上形成至少一个导电层;以及
将陶瓷层沉积在所述至少一个导电层之上。
24.根据权利要求17所述的方法,进一步包括:
在陶瓷层之上形成至少一个导电层;以及
在所述至少一个导电层之上形成第二芯片。
25.根据权利要求17所述的方法,包括:
经由导电介质将第一芯片电连接到载体,所述导电介质包括来自下述材料组的至少一种材料,所述组由以下各项构成:焊料、软焊料、扩散焊料、浆料、纳米浆料、粘合剂、导电粘合剂、导热粘合剂。
26.根据权利要求17所述的方法,
其中所述第一芯片包括功率半导体芯片。
27.根据权利要求17所述的方法,
其中所述第二芯片包括半导体逻辑芯片或半导体存储芯片。
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US (2) | US20140197527A1 (zh) |
CN (1) | CN103928448A (zh) |
DE (1) | DE102014100278A1 (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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CN105336718A (zh) * | 2014-08-04 | 2016-02-17 | 英飞凌科技股份有限公司 | 源极向下半导体器件及其制造方法 |
CN108063127A (zh) * | 2016-11-07 | 2018-05-22 | 罗伯特·博世有限公司 | 芯片和功率晶体管 |
CN116053239A (zh) * | 2023-04-03 | 2023-05-02 | 中科华艺(天津)科技有限公司 | 一种多芯片组件的封装结构 |
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US9397018B2 (en) | 2013-01-16 | 2016-07-19 | Infineon Technologies Ag | Chip arrangement, a method for manufacturing a chip arrangement, integrated circuits and a method for manufacturing an integrated circuit |
US9230889B2 (en) | 2013-01-16 | 2016-01-05 | Infineon Technologies Ag | Chip arrangement with low temperature co-fired ceramic and a method for forming a chip arrangement with low temperature co-fired ceramic |
US9365414B2 (en) * | 2014-04-21 | 2016-06-14 | Freescale Semiconductor, Inc. | Sensor package having stacked die |
EP3422401B1 (en) * | 2016-02-26 | 2023-11-15 | National Institute of Advanced Industrial Science and Technology | Heat dissipating substrate |
DE102019120872A1 (de) * | 2019-08-01 | 2021-02-04 | Infineon Technologies Ag | Löten eines Leiters an eine Aluminiumschicht |
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CN1577907A (zh) * | 2003-07-09 | 2005-02-09 | 日亚化学工业株式会社 | 发光器件和发光器件的制造方法以及照明装置 |
US20080296782A1 (en) * | 2007-06-04 | 2008-12-04 | Infineon Technologies Ag | Semiconductor device |
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US20130229777A1 (en) * | 2012-03-01 | 2013-09-05 | Infineon Technologies Ag | Chip arrangements and methods for forming a chip arrangement |
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2013
- 2013-01-16 US US13/742,455 patent/US20140197527A1/en not_active Abandoned
-
2014
- 2014-01-13 DE DE102014100278.4A patent/DE102014100278A1/de not_active Ceased
- 2014-01-16 CN CN201410019271.1A patent/CN103928448A/zh active Pending
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2016
- 2016-09-19 US US15/268,674 patent/US9984897B2/en active Active
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US5561322A (en) * | 1994-11-09 | 1996-10-01 | International Business Machines Corporation | Semiconductor chip package with enhanced thermal conductivity |
CN1577907A (zh) * | 2003-07-09 | 2005-02-09 | 日亚化学工业株式会社 | 发光器件和发光器件的制造方法以及照明装置 |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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CN105336718A (zh) * | 2014-08-04 | 2016-02-17 | 英飞凌科技股份有限公司 | 源极向下半导体器件及其制造方法 |
US9911686B2 (en) | 2014-08-04 | 2018-03-06 | Infineon Technologies Ag | Source down semiconductor devices and methods of formation thereof |
CN105336718B (zh) * | 2014-08-04 | 2018-06-15 | 英飞凌科技股份有限公司 | 源极向下半导体器件及其制造方法 |
CN108063127A (zh) * | 2016-11-07 | 2018-05-22 | 罗伯特·博世有限公司 | 芯片和功率晶体管 |
CN116053239A (zh) * | 2023-04-03 | 2023-05-02 | 中科华艺(天津)科技有限公司 | 一种多芯片组件的封装结构 |
Also Published As
Publication number | Publication date |
---|---|
US9984897B2 (en) | 2018-05-29 |
US20140197527A1 (en) | 2014-07-17 |
DE102014100278A1 (de) | 2014-07-17 |
US20170004979A1 (en) | 2017-01-05 |
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